2 PCI Host Bridge Definitions
4 Copyright (c) 2013-2015 Intel Corporation.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 Name(PBRS, ResourceTemplate() {
18 WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
19 ResourceProducer, // bit 0 of general flags is 1
20 MinFixed, // Range is fixed
21 MaxFixed, // Range is fixed
22 PosDecode, // PosDecode
23 0x0000, // Granularity
26 0x0000, // Translation
27 0x0020 // Range Length = Max-Min+1
30 WORDIO( //Consumed-and-produced resource (all I/O below CF8)
31 ResourceProducer, // bit 0 of general flags is 0
32 MinFixed, // Range is fixed
33 MaxFixed, // Range is fixed
36 0x0000, // Granularity
39 0x0000, // Translation
40 0x0cf8 // Range Length
43 IO( //Consumed resource (CF8-CFF)
51 WORDIO( //Consumed-and-produced resource (all I/O above CFF)
52 ResourceProducer, // bit 0 of general flags is 0
53 MinFixed, // Range is fixed
54 MaxFixed, // Range is fixed
57 0x0000, // Granularity
60 0x0000, // Translation
61 0xf300 // Range Length
64 DWORDMEMORY( // descriptor for dos area(0->0xa0000)
65 ResourceProducer, // bit 0 of general flags is 0
67 MinFixed, // Range is fixed
68 MaxFixed, // Range is Fixed
71 0x00000000, // Granularity
74 0x00000000, // Translation
75 0x00020000 // Range Length
78 DWORDMemory( // Consumed-and-produced resource for pci memory mapped memory
79 ResourceProducer, // bit 0 of general flags is 0
80 PosDecode, // positive Decode
81 MinFixed, // Range is fixed
82 MaxFixed, // Range is fixed
85 0x00000000, // Granularity
86 0x00000000, // Min (calculated dynamically)
88 0xfebfffff, // Max = IO Apic base address - 1
89 0x00000000, // Translation
90 0xfec00000, // Range Length (calculated dynamically)
91 , // Optional field left blank
92 , // Optional field left blank
93 MEM1 // Name declaration for this descriptor
96 }) // end of CRES Buffer
99 Method(_CRS, 0x0, NotSerialized)
101 CreateDWordField(PBRS, \_SB.PCI0.MEM1._MIN, MMIN)
102 CreateDWordField(PBRS, \_SB.PCI0.MEM1._MAX, MMAX)
103 CreateDWordField(PBRS, \_SB.PCI0.MEM1._LEN, MLEN)
105 // HMBOUND is PCI memory base
106 And(MNRD(0x03, 0x08), 0xFFFFF000, MMIN)
107 Add(Subtract(MMAX, MMIN), 1, MLEN)
112 // Message Nework Registers
113 OperationRegion(MNR, PCI_Config, 0xD0, 0x10)
114 Field(MNR, DWordAcc, NoLock, Preserve)
116 MCR, 32, // Message Control Register
117 MDR, 32 // Message Data Register
120 // Message Nework Read Method
123 // return 32 bit register value
124 Method(MNRD, 2, Serialized)
126 Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
127 Or(Local0, 0x100000F0, Local0)
132 // Message Nework Write Method
135 // Arg2 = 32 bit write value
136 Method(MNWR, 3, Serialized)
139 Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
140 Or(Local0, 0x110000F0, Local0)
144 Method(_PRT, 0, NotSerialized)
146 If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
151 // Bus 0, Device 20 - IOSFAHB Bridge
152 Package() {0x0014ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
153 Package() {0x0014ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
154 Package() {0x0014ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
155 Package() {0x0014ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
157 // Bus 0, Device 21 - IOSFAHB Bridge
158 Package() {0x0015ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
159 Package() {0x0015ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
160 Package() {0x0015ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
161 Package() {0x0015ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
163 // Bus 0, Device 23 - PCIe port 0
164 Package() {0x0017ffff, 0, \_SB.PCI0.LPC.LNKE, 0}, // INTA
165 Package() {0x0017ffff, 1, \_SB.PCI0.LPC.LNKF, 0}, // INTB
166 Package() {0x0017ffff, 2, \_SB.PCI0.LPC.LNKG, 0}, // INTC
167 Package() {0x0017ffff, 3, \_SB.PCI0.LPC.LNKH, 0}, // INTD
170 Package() {0x001fffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // LPC Bridge
178 // Bus 0, Device 20 - IOSFAHB Bridge
179 Package() {0x0014ffff, 0, 0, 16}, // INTA
180 Package() {0x0014ffff, 1, 0, 17}, // INTB
181 Package() {0x0014ffff, 2, 0, 18}, // INTC
182 Package() {0x0014ffff, 3, 0, 19}, // INTD
184 // Bus 0, Device 21 - IOSFAHB Bridge
185 Package() {0x0015ffff, 0, 0, 16}, // INTA
186 Package() {0x0015ffff, 1, 0, 17}, // INTB
187 Package() {0x0015ffff, 2, 0, 18}, // INTC
188 Package() {0x0015ffff, 3, 0, 19}, // INTD
190 // Bus 0, Device 23 - PCIe port 0
191 Package() {0x0017ffff, 0, 0, 20}, // INTA
192 Package() {0x0017ffff, 1, 0, 21}, // INTB
193 Package() {0x0017ffff, 2, 0, 22}, // INTC
194 Package() {0x0017ffff, 3, 0, 23}, // INTD
197 Package() {0x001fffff, 0, 0, 16}, // LPC Bridge