QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.h

   1 /** @file
   2
   3 Processor power management initialization code.
   4
   5 Copyright (c) 2013-2015 Intel Corporation.
   6
   7 This program and the accompanying materials
   8 are licensed and made available under the terms and conditions of the BSD License
   9 which accompanies this distribution.  The full text of the license may be found at
  10 http://opensource.org/licenses/bsd-license.php
  11
  12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15
  16 **/
  17
  18 #ifndef _PPM_H
  19 #define _PPM_H
  20
  21 //
  22 // Bit definitions of PPMFlags
  23 //
  24 #define PPM_GV3         (1 << 0)  // Geyserville 3
  25 #define PPM_TURBO       (1 << 1)  // Turbo Mode
  26 #define PPM_SUPER_LFM   (1 << 2)  // N/2 Ratio
  27 #define PPM_C1          (1 << 4)  // C1 Capable, Enabled
  28 #define PPM_C2          (1 << 5)  // C2 Capable, Enabled
  29 #define PPM_C3          (1 << 6)  // C3 Capable, Enabled
  30 #define PPM_C4          (1 << 7)  // C4 Capable, Enabled
  31 #define PPM_C5          (1 << 8)  // C5/Deep C4 Capable, Enabled
  32 #define PPM_C6          (1 << 9)  // C6 Capable, Enabled
  33 #define PPM_C1E         (1 << 10) // C1E Enabled
  34 #define PPM_C2E         (1 << 11) // C2E Enabled
  35 #define PPM_C3E         (1 << 12) // C3E Enabled
  36 #define PPM_C4E         (1 << 13) // C4E Enabled
  37 #define PPM_HARD_C4E    (1 << 14) // Hard C4E Capable, Enabled
  38 #define PPM_TM1         (1 << 16) // Thermal Monitor 1
  39 #define PPM_TM2         (1 << 17) // Thermal Monitor 2
  40 #define PPM_PHOT        (1 << 19) // Bi-directional ProcHot
  41 #define PPM_MWAIT_EXT   (1 << 21) // MWAIT extensions supported
  42 #define PPM_CMP         (1 << 24) // CMP supported, Enabled
  43 #define PPM_TSTATE      (1 << 28) // CPU T states supported
  44
  45 #define PPM_C_STATES    (PPM_C1 + PPM_C2 + PPM_C3 + PPM_C4 + PPM_C5 + PPM_C6)
  46 #define PPM_CE_STATES   (PPM_C1E + PPM_C2E + PPM_C3E + PPM_C4E + PPM_HARD_C4E)
  47
  48
  49 #define MAX_P_STATES_NUM    12
  50
  51 #define AML_NAME_OP         0x08
  52 #define AML_SCOPE_OP        0x10
  53 #define AML_PACKAGE_OP      0x12
  54 #define AML_METHOD_OP       0x14
  55
  56 #define S3_CPU_REGISTER_TABLE_GUID \
  57   { \
  58     0xc4ef988d, 0xe5e, 0x4403, { 0xbe, 0xeb, 0xf1, 0xbb, 0x6, 0x79, 0x6e, 0xdf } \
  59   }
  60
  61 #pragma pack(1)
  62 typedef struct {
  63   UINT8   StartByte;
  64   UINT32  NameStr;
  65   UINT8   OpCode;
  66   UINT16  Size;                // Hardcode to 16bit width because the table we use is fixed size
  67   UINT8   NumEntries;
  68 } EFI_ACPI_NAME_COMMAND;
  69
  70 typedef struct {
  71   UINT8   PackageOp;
  72   UINT8   PkgLeadByte;
  73   UINT8   NumEntries;
  74   UINT8   DwordPrefix0;
  75   UINT32  CoreFreq;
  76   UINT8   DwordPrefix1;
  77   UINT32  Power;
  78   UINT8   DwordPrefix2;
  79   UINT32  TransLatency;
  80   UINT8   DwordPrefix3;
  81   UINT32  BMLatency;
  82   UINT8   DwordPrefix4;
  83   UINT32  Control;
  84   UINT8   DwordPrefix5;
  85   UINT32  Status;
  86 } EFI_PSS_PACKAGE;
  87 #pragma pack()
  88
  89 typedef struct {
  90   UINT32  Index;
  91   UINT64  Value;
  92 } S3_CPU_REGISTER;
  93
  94 //
  95 // Function prototypes
  96 //
  97
  98 /**
  99   This function is the entry of processor power management initialization code.
 100   It initializes the processor's power management features based on the user
 101   configurations and hardware capablities.
 102 **/
 103 VOID
 104 PpmInit (
 105   VOID
 106   );
 107
 108 /**
 109   This function is to determine the Processor Power Management Flags
 110   based on the hardware capability.
 111 **/
 112 VOID
 113 PpmDetectCapability (
 114   VOID
 115   );
 116
 117 /**
 118   This function is to determine the user configuration mask
 119 **/
 120 VOID
 121 PpmGetUserConfigurationMask (
 122   VOID
 123   );
 124
 125 /**
 126   This function is to patch and publish power management related acpi tables.
 127 **/
 128 VOID
 129 PpmPatchAndPublishAcpiTables (
 130   VOID
 131   );
 132
 133 /**
 134   This function is to patch PLvl2Lat and PLvl3Lat to enable C2, C3 support in OS.
 135 **/
 136 VOID
 137 PpmPatchFadtTable (
 138   VOID
 139   );
 140
 141 /**
 142   This function is to load all the power management acpi tables and patch IST table.
 143 **/
 144 VOID
 145 PpmLoadAndPatchPMTables (
 146   VOID
 147   );
 148
 149 /**
 150   This function is to save cpu registers for s3 resume.
 151 **/
 152 VOID
 153 PpmS3SaveRegisters (
 154   VOID
 155   );
 156 #endif