QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.h

   1 /** @file
   2
   3 Processor power management initialization code.
   4
   5 Copyright (c) 2013-2015 Intel Corporation.
   6
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9
  10 **/
  11
  12 #ifndef _PPM_H
  13 #define _PPM_H
  14
  15 //
  16 // Bit definitions of PPMFlags
  17 //
  18 #define PPM_GV3         (1 << 0)  // Geyserville 3
  19 #define PPM_TURBO       (1 << 1)  // Turbo Mode
  20 #define PPM_SUPER_LFM   (1 << 2)  // N/2 Ratio
  21 #define PPM_C1          (1 << 4)  // C1 Capable, Enabled
  22 #define PPM_C2          (1 << 5)  // C2 Capable, Enabled
  23 #define PPM_C3          (1 << 6)  // C3 Capable, Enabled
  24 #define PPM_C4          (1 << 7)  // C4 Capable, Enabled
  25 #define PPM_C5          (1 << 8)  // C5/Deep C4 Capable, Enabled
  26 #define PPM_C6          (1 << 9)  // C6 Capable, Enabled
  27 #define PPM_C1E         (1 << 10) // C1E Enabled
  28 #define PPM_C2E         (1 << 11) // C2E Enabled
  29 #define PPM_C3E         (1 << 12) // C3E Enabled
  30 #define PPM_C4E         (1 << 13) // C4E Enabled
  31 #define PPM_HARD_C4E    (1 << 14) // Hard C4E Capable, Enabled
  32 #define PPM_TM1         (1 << 16) // Thermal Monitor 1
  33 #define PPM_TM2         (1 << 17) // Thermal Monitor 2
  34 #define PPM_PHOT        (1 << 19) // Bi-directional ProcHot
  35 #define PPM_MWAIT_EXT   (1 << 21) // MWAIT extensions supported
  36 #define PPM_CMP         (1 << 24) // CMP supported, Enabled
  37 #define PPM_TSTATE      (1 << 28) // CPU T states supported
  38
  39 #define PPM_C_STATES    (PPM_C1 + PPM_C2 + PPM_C3 + PPM_C4 + PPM_C5 + PPM_C6)
  40 #define PPM_CE_STATES   (PPM_C1E + PPM_C2E + PPM_C3E + PPM_C4E + PPM_HARD_C4E)
  41
  42
  43 #define MAX_P_STATES_NUM    12
  44
  45 #define AML_NAME_OP         0x08
  46 #define AML_SCOPE_OP        0x10
  47 #define AML_PACKAGE_OP      0x12
  48 #define AML_METHOD_OP       0x14
  49
  50 #define S3_CPU_REGISTER_TABLE_GUID \
  51   { \
  52     0xc4ef988d, 0xe5e, 0x4403, { 0xbe, 0xeb, 0xf1, 0xbb, 0x6, 0x79, 0x6e, 0xdf } \
  53   }
  54
  55 #pragma pack(1)
  56 typedef struct {
  57   UINT8   StartByte;
  58   UINT32  NameStr;
  59   UINT8   OpCode;
  60   UINT16  Size;                // Hardcode to 16bit width because the table we use is fixed size
  61   UINT8   NumEntries;
  62 } EFI_ACPI_NAME_COMMAND;
  63
  64 typedef struct {
  65   UINT8   PackageOp;
  66   UINT8   PkgLeadByte;
  67   UINT8   NumEntries;
  68   UINT8   DwordPrefix0;
  69   UINT32  CoreFreq;
  70   UINT8   DwordPrefix1;
  71   UINT32  Power;
  72   UINT8   DwordPrefix2;
  73   UINT32  TransLatency;
  74   UINT8   DwordPrefix3;
  75   UINT32  BMLatency;
  76   UINT8   DwordPrefix4;
  77   UINT32  Control;
  78   UINT8   DwordPrefix5;
  79   UINT32  Status;
  80 } EFI_PSS_PACKAGE;
  81 #pragma pack()
  82
  83 typedef struct {
  84   UINT32  Index;
  85   UINT64  Value;
  86 } S3_CPU_REGISTER;
  87
  88 //
  89 // Function prototypes
  90 //
  91
  92 /**
  93   This function is the entry of processor power management initialization code.
  94   It initializes the processor's power management features based on the user
  95   configurations and hardware capablities.
  96 **/
  97 VOID
  98 PpmInit (
  99   VOID
 100   );
 101
 102 /**
 103   This function is to determine the Processor Power Management Flags
 104   based on the hardware capability.
 105 **/
 106 VOID
 107 PpmDetectCapability (
 108   VOID
 109   );
 110
 111 /**
 112   This function is to determine the user configuration mask
 113 **/
 114 VOID
 115 PpmGetUserConfigurationMask (
 116   VOID
 117   );
 118
 119 /**
 120   This function is to patch and publish power management related acpi tables.
 121 **/
 122 VOID
 123 PpmPatchAndPublishAcpiTables (
 124   VOID
 125   );
 126
 127 /**
 128   This function is to patch PLvl2Lat and PLvl3Lat to enable C2, C3 support in OS.
 129 **/
 130 VOID
 131 PpmPatchFadtTable (
 132   VOID
 133   );
 134
 135 /**
 136   This function is to load all the power management acpi tables and patch IST table.
 137 **/
 138 VOID
 139 PpmLoadAndPatchPMTables (
 140   VOID
 141   );
 142
 143 /**
 144   This function is to save cpu registers for s3 resume.
 145 **/
 146 VOID
 147 PpmS3SaveRegisters (
 148   VOID
 149   );
 150 #endif