QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h

   1 /** @file
   2   SPI flash device header file.
   3
   4   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _SPI_FLASH_DEVICE_H_
  16 #define _SPI_FLASH_DEVICE_H_
  17
  18 #include <PiDxe.h>
  19 #include <Protocol/Spi.h>
  20 #include <Protocol/FirmwareVolumeBlock.h>
  21
  22 //
  23 // Supported SPI Flash Devices
  24 //
  25 typedef enum {
  26   EnumSpiFlash25L3205D,   // Macronix 32Mbit part
  27   EnumSpiFlashW25Q32,     // Winbond 32Mbit part
  28   EnumSpiFlashW25X32,     // Winbond 32Mbit part
  29   EnumSpiFlashAT25DF321,  // Atmel 32Mbit part
  30   EnumSpiFlashQH25F320,   // Intel 32Mbit part
  31   EnumSpiFlash25VF064C,   // SST 64Mbit part
  32   EnumSpiFlashM25PX64,    // NUMONYX 64Mbit part
  33   EnumSpiFlashAT25DF641,  // Atmel 64Mbit part
  34   EnumSpiFlashS25FL064K,  // Spansion 64Mbit part
  35   EnumSpiFlash25L6405D,   // Macronix 64Mbit part
  36   EnumSpiFlashW25Q64,     // Winbond 64Mbit part
  37   EnumSpiFlashW25X64,     // Winbond 64Mbit part
  38   EnumSpiFlashQH25F640,   // Intel 64Mbit part
  39   EnumSpiFlashMax
  40 } SPI_FLASH_TYPES_SUPPORTED;
  41
  42 //
  43 // Flash Device commands
  44 //
  45 // If a supported device uses a command different from the list below, a device specific command
  46 // will be defined just below it's JEDEC id section.
  47 //
  48 #define SPI_COMMAND_WRITE                 0x02
  49 #define SPI_COMMAND_WRITE_AAI             0xAD
  50 #define SPI_COMMAND_READ                  0x03
  51 #define SPI_COMMAND_ERASE                 0x20
  52 #define SPI_COMMAND_WRITE_DISABLE         0x04
  53 #define SPI_COMMAND_READ_S                0x05
  54 #define SPI_COMMAND_WRITE_ENABLE          0x06
  55 #define SPI_COMMAND_READ_ID               0xAB
  56 #define SPI_COMMAND_JEDEC_ID              0x9F
  57 #define SPI_COMMAND_WRITE_S_EN            0x50
  58 #define SPI_COMMAND_WRITE_S               0x01
  59 #define SPI_COMMAND_CHIP_ERASE            0xC7
  60 #define SPI_COMMAND_BLOCK_ERASE           0xD8
  61
  62 //
  63 // Flash JEDEC device ids
  64 //
  65 // SST 8Mbit part
  66 //
  67 #define SPI_SST25VF080B_ID1               0xBF
  68 #define SPI_SST25VF080B_ID2               0x25
  69 #define SPI_SST25VF080B_ID3               0x8E
  70 //
  71 // SST 16Mbit part
  72 //
  73 #define SPI_SST25VF016B_ID1               0xBF
  74 #define SPI_SST25VF016B_ID2               0x25
  75 #define SPI_SST25V016BF_ID3               0x41
  76 //
  77 // Macronix 32Mbit part
  78 //
  79 // MX25 part does not support WRITE_AAI comand (0xAD)
  80 //
  81 #define SPI_MX25L3205_ID1                 0xC2
  82 #define SPI_MX25L3205_ID2                 0x20
  83 #define SPI_MX25L3205_ID3                 0x16
  84 //
  85 // Intel 32Mbit part bottom boot
  86 //
  87 #define SPI_QH25F320_ID1                  0x89
  88 #define SPI_QH25F320_ID2                  0x89
  89 #define SPI_QH25F320_ID3                  0x12  // 32Mbit bottom boot
  90 //
  91 // Intel 64Mbit part bottom boot
  92 //
  93 #define SPI_QH25F640_ID1                  0x89
  94 #define SPI_QH25F640_ID2                  0x89
  95 #define SPI_QH25F640_ID3                  0x13  // 64Mbit bottom boot
  96 //
  97 // QH part does not support command 0x20 for erase; only 0xD8 (sector erase)
  98 // QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)
  99 // 0x40 command ignored if address outside of parameter block range
 100 //
 101 #define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40
 102 //
 103 // Winbond 32Mbit part
 104 //
 105 #define SPI_W25X32_ID1                    0xEF
 106 #define SPI_W25X32_ID2                    0x30  // Memory Type
 107 #define SPI_W25X32_ID3                    0x16  // Capacity
 108 #define SF_DEVICE_ID1_W25Q32              0x16
 109
 110 //
 111 // Winbond 64Mbit part
 112 //
 113 #define SPI_W25X64_ID1                    0xEF
 114 #define SPI_W25X64_ID2                    0x30  // Memory Type
 115 #define SPI_W25X64_ID3                    0x17  // Capacity
 116 #define SF_DEVICE_ID0_W25QXX              0x40
 117 #define SF_DEVICE_ID1_W25Q64              0x17
 118 //
 119 // Winbond 128Mbit part
 120 //
 121 #define SF_DEVICE_ID0_W25Q128             0x40
 122 #define SF_DEVICE_ID1_W25Q128             0x18
 123
 124 //
 125 // Atmel 32Mbit part
 126 //
 127 #define SPI_AT26DF321_ID1                 0x1F
 128 #define SPI_AT26DF321_ID2                 0x47  // [7:5]=Family, [4:0]=Density
 129 #define SPI_AT26DF321_ID3                 0x00
 130
 131 #define SF_VENDOR_ID_ATMEL                0x1F
 132 #define SF_DEVICE_ID0_AT25DF641           0x48
 133 #define SF_DEVICE_ID1_AT25DF641           0x00
 134
 135 //
 136 // SST 8Mbit part
 137 //
 138 #define SPI_SST25VF080B_ID1               0xBF
 139 #define SPI_SST25VF080B_ID2               0x25
 140 #define SPI_SST25VF080B_ID3               0x8E
 141 #define SF_DEVICE_ID0_25VF064C            0x25
 142 #define SF_DEVICE_ID1_25VF064C            0x4B
 143
 144 //
 145 // SST 16Mbit part
 146 //
 147 #define SPI_SST25VF016B_ID1               0xBF
 148 #define SPI_SST25VF016B_ID2               0x25
 149 #define SPI_SST25V016BF_ID3               0x41
 150
 151 //
 152 // Winbond 32Mbit part
 153 //
 154 #define SPI_W25X32_ID1                    0xEF
 155 #define SPI_W25X32_ID2                    0x30  // Memory Type
 156 #define SPI_W25X32_ID3                    0x16  // Capacity
 157
 158 #define  SF_VENDOR_ID_MX             0xC2
 159 #define  SF_DEVICE_ID0_25L6405D      0x20
 160 #define  SF_DEVICE_ID1_25L6405D      0x17
 161
 162 #define  SF_VENDOR_ID_NUMONYX        0x20
 163 #define  SF_DEVICE_ID0_M25PX64       0x71
 164 #define  SF_DEVICE_ID1_M25PX64       0x17
 165
 166 //
 167 // Spansion 64Mbit part
 168 //
 169 #define SF_VENDOR_ID_SPANSION             0xEF
 170 #define SF_DEVICE_ID0_S25FL064K           0x40
 171 #define SF_DEVICE_ID1_S25FL064K           0x00
 172
 173 //
 174 // index for prefix opcodes
 175 //
 176 #define SPI_WREN_INDEX                    0   // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE
 177 #define SPI_EWSR_INDEX                    1   // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN
 178 #define BIOS_CTRL                         0xDC
 179
 180 #define PFAB_CARD_DEVICE_ID               0x5150
 181 #define PFAB_CARD_VENDOR_ID               0x8086
 182 #define PFAB_CARD_SETUP_REGISTER          0x40
 183 #define PFAB_CARD_SETUP_BYTE              0x0d
 184
 185
 186 #endif