2 System On Chip Unit (SOCUnit) routines.
4 Copyright (c) 2013-2015 Intel Corporation.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "CommonHeader.h"
18 /** Early initialisation of the SOC Unit
20 @retval EFI_SUCCESS Operation success.
25 SocUnitEarlyInitialisation (
32 // Set the mixer load resistance
34 NewValue
= QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID
, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0
);
35 NewValue
&= OCFGPIMIXLOAD_1_0_MASK
;
36 QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID
, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0
, NewValue
);
38 NewValue
= QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID
, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1
);
39 NewValue
&= OCFGPIMIXLOAD_1_0_MASK
;
40 QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID
, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1
, NewValue
);
45 /** Tasks to release PCI controller from reset pre wait for PLL Lock.
47 @retval EFI_SUCCESS Operation success.
52 SocUnitReleasePcieControllerPreWaitPllLock (
53 IN CONST EFI_PLATFORM_TYPE PlatformType
59 // Assert PERST# and validate time assertion time.
61 PlatformPERSTAssert (PlatformType
);
62 ASSERT (PCIEXP_PERST_MIN_ASSERT_US
<= (PCIEXP_DELAY_US_POST_CMNRESET_RESET
+ PCIEXP_DELAY_US_WAIT_PLL_LOCK
+ PCIEXP_DELAY_US_POST_SBI_RESET
));
65 // PHY Common lane reset.
67 NewValue
= QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
);
68 NewValue
|= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L
;
69 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
, NewValue
);
72 // Wait post common lane reset.
74 MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET
);
77 // PHY Sideband interface reset.
78 // Controller main reset
80 NewValue
= QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
);
81 NewValue
|= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B
| SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L
);
82 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
, NewValue
);
87 /** Tasks to release PCI controller from reset after PLL has locked
89 @retval EFI_SUCCESS Operation success.
94 SocUnitReleasePcieControllerPostPllLock (
95 IN CONST EFI_PLATFORM_TYPE PlatformType
101 // Controller sideband interface reset.
103 NewValue
= QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
);
104 NewValue
|= SOCCLKEN_CONFIG_SBI_BB_RST_B
;
105 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
, NewValue
);
108 // Wait post sideband interface reset.
110 MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET
);
115 PlatformPERSTDeAssert (PlatformType
);
118 // Wait post de assert PERST#.
120 MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT
);
123 // Controller primary interface reset.
125 NewValue
= QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
);
126 NewValue
|= SOCCLKEN_CONFIG_BB_RST_B
;
127 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
, NewValue
);