QuarkPlatformPkg/Platform/Dxe/Setup/QNCRegTable.c

   1 /** @file
   2 Register initialization table for Ich.
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14
  15 **/
  16
  17
  18 #include "CommonHeader.h"
  19
  20 VOID
  21 PlatformInitQNCRegs (
  22   VOID
  23   )
  24 {
  25   //
  26   // All devices on bus 0.
  27   // Device 0:
  28   //    FNC 0: Host Bridge
  29   // Device 20:
  30   //    FNC 0: IOSF2AHB Bridge
  31   // Device 21:
  32   //    FNC 0: IOSF2AHB Bridge
  33   // Device 23:
  34   //    FNC 0: PCIe Port 0
  35   // Device 24:
  36   //    FNC 0: PCIe Port 1
  37
  38   // Device 31:
  39   //    FNC 0: PCI-LPC Bridge
  40   //
  41   S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_FWH_BIOS_DEC),
  42                 B_QNC_LPC_FWH_BIOS_DEC_F0 | B_QNC_LPC_FWH_BIOS_DEC_F8 |
  43                 B_QNC_LPC_FWH_BIOS_DEC_E0 | B_QNC_LPC_FWH_BIOS_DEC_E8 |
  44                 B_QNC_LPC_FWH_BIOS_DEC_D0 | B_QNC_LPC_FWH_BIOS_DEC_D8 |
  45                 B_QNC_LPC_FWH_BIOS_DEC_C0 | B_QNC_LPC_FWH_BIOS_DEC_C8
  46                 );
  47
  48   //
  49   // Program SCI Interrupt for IRQ9
  50   //
  51   S3PciWrite8 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_ACTL),
  52                V_QNC_LPC_ACTL_SCIS_IRQ9
  53                );
  54
  55   //
  56   // Program Quark Interrupt Route Registers
  57   //
  58   S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT0IR,
  59              PcdGet16(PcdQuarkAgent0IR)
  60              );
  61   S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT1IR,
  62              PcdGet16(PcdQuarkAgent1IR)
  63              );
  64   S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT2IR,
  65              PcdGet16(PcdQuarkAgent2IR)
  66              );
  67   S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT3IR,
  68              PcdGet16(PcdQuarkAgent3IR)
  69              );
  70
  71   //
  72   // Program SVID and SID for QNC PCI devices. In order to boost performance, we
  73   // combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE. The programmed LPC SVID
  74   // will reflect on all internal devices's SVID registers
  75   //
  76   S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_EFI_PCI_SVID),
  77                 (UINT32)(V_INTEL_VENDOR_ID + (QUARK_V_LPC_DEVICE_ID_0 << 16))
  78                 );
  79
  80   //
  81   // Write once on Element Self Description Register before OS boot
  82   //
  83   QNCMmio32And (PcdGet64(PcdRcbaMmioBaseAddress), 0x04, 0xFF00FFFF);
  84
  85   return;
  86 }