QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformErratas.c

   1 /** @file
   2 Platform Erratas performed by early init PEIM driver.
   3
   4 Copyright (c) 2013 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include "CommonHeader.h"
  11 #include "PlatformEarlyInit.h"
  12
  13 //
  14 // Constants.
  15 //
  16
  17 //
  18 // Platform EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs.
  19 //
  20 #define EHCI_OUT_THRESHOLD_VALUE              (0x7f)
  21 #define EHCI_IN_THRESHOLD_VALUE               (0x7f)
  22
  23 //
  24 // Platform init USB device interrupt masks.
  25 //
  26 #define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG    (0x0000007f)
  27 #define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG   (B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK | B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK)
  28
  29 //
  30 // Global variables defined within this source module.
  31 //
  32
  33 UINTN IohEhciPciReg[IOH_MAX_EHCI_USB_CONTROLLERS] = {
  34   PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, 0),
  35 };
  36
  37 UINTN IohUsbDevicePciReg[IOH_MAX_USBDEVICE_USB_CONTROLLERS] = {
  38   PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USBDEVICE_DEVICE_NUMBER, IOH_USBDEVICE_FUNCTION_NUMBER, 0),
  39 };
  40
  41 //
  42 // Routines local to this source module.
  43 //
  44
  45 /** Perform USB erratas after MRC init.
  46
  47 **/
  48 VOID
  49 PlatformUsbErratasPostMrc (
  50   VOID
  51   )
  52 {
  53   UINT32                            Index;
  54   UINT32                            TempBar0Addr;
  55   UINT16                            SaveCmdReg;
  56   UINT32                            SaveBar0Reg;
  57
  58   TempBar0Addr = PcdGet32(PcdPeiQNCUsbControllerMemoryBaseAddress);
  59
  60   //
  61   // Apply EHCI controller erratas.
  62   //
  63   for (Index = 0; Index < IOH_MAX_EHCI_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) {
  64
  65     if ((PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) {
  66       continue;  // Device not enabled, skip.
  67     }
  68
  69     //
  70     // Save current settings for PCI CMD/BAR0 registers
  71     //
  72     SaveCmdReg = PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND);
  73     SaveBar0Reg = PciRead32 (IohEhciPciReg[Index] + R_IOH_USB_MEMBAR);
  74
  75     //
  76     // Temp. assign base address register, Enable Memory Space.
  77     //
  78     PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr);
  79     PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE);
  80
  81
  82     //
  83     // Set packet buffer OUT/IN thresholds.
  84     //
  85     MmioAndThenOr32 (
  86       TempBar0Addr + R_IOH_EHCI_INSNREG01,
  87       (UINT32) (~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK | B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK)),
  88       (UINT32) ((EHCI_OUT_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP) | (EHCI_IN_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP))
  89       );
  90
  91     //
  92     // Restore settings for PCI CMD/BAR0 registers
  93     //
  94     PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg);
  95     PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg);
  96   }
  97
  98   //
  99   // Apply USB device controller erratas.
 100   //
 101   for (Index = 0; Index < IOH_MAX_USBDEVICE_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) {
 102
 103     if ((PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) {
 104       continue;  // Device not enabled, skip.
 105     }
 106
 107     //
 108     // Save current settings for PCI CMD/BAR0 registers
 109     //
 110     SaveCmdReg = PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND);
 111     SaveBar0Reg = PciRead32 (IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR);
 112
 113     //
 114     // Temp. assign base address register, Enable Memory Space.
 115     //
 116     PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr);
 117     PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE);
 118
 119     //
 120     // Erratas for USB Device interrupt registers.
 121     //
 122
 123     //
 124     // 1st Mask interrupts.
 125     //
 126     MmioWrite32 (
 127       TempBar0Addr + R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG,
 128       V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG
 129       );
 130     //
 131     // 2nd RW/1C of equivalent status bits.
 132     //
 133     MmioWrite32 (
 134       TempBar0Addr + R_IOH_USBDEVICE_D_INTR_UDC_REG,
 135       V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG
 136       );
 137
 138     //
 139     // 1st Mask end point interrupts.
 140     //
 141     MmioWrite32 (
 142       TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG,
 143       V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG
 144       );
 145     //
 146     // 2nd RW/1C of equivalent end point status bits.
 147     //
 148     MmioWrite32 (
 149       TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_UDC_REG,
 150       V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG
 151       );
 152
 153     //
 154     // Restore settings for PCI CMD/BAR0 registers
 155     //
 156     PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg);
 157     PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg);
 158   }
 159 }
 160
 161 //
 162 // Routines exported by this source module.
 163 //
 164
 165 /** Perform Platform Erratas after MRC.
 166
 167   @retval   EFI_SUCCESS               Operation success.
 168
 169 **/
 170 EFI_STATUS
 171 EFIAPI
 172 PlatformErratasPostMrc (
 173   VOID
 174   )
 175 {
 176   PlatformUsbErratasPostMrc ();
 177   return EFI_SUCCESS;
 178 }