QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.c

   1 /** @file
   2 Initializes Platform Specific Drivers.
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8
   9 **/
  10
  11 #include "SpiFlashDevice.h"
  12
  13 #define FLASH_SIZE  (FixedPcdGet32 (PcdFlashAreaSize))
  14
  15 SPI_INIT_TABLE  mSpiInitTable[] = {
  16   //
  17   // Macronix 32Mbit part
  18   //
  19   {
  20     SPI_MX25L3205_ID1,
  21     SPI_MX25L3205_ID2,
  22     SPI_MX25L3205_ID3,
  23     {
  24       SPI_COMMAND_WRITE_ENABLE,
  25       SPI_COMMAND_WRITE_S_EN
  26     },
  27     {
  28       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
  29       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
  30       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
  31       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
  32       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle20MHz, EnumSpiOperationReadData},
  33       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
  34       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
  35       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
  36     },
  37     0x400000 - FLASH_SIZE, // BIOS Start Offset
  38     FLASH_SIZE   // BIOS image size in flash
  39   },
  40   //
  41   // Winbond 32Mbit part
  42   //
  43   {
  44     SPI_W25X32_ID1,
  45     SF_DEVICE_ID0_W25QXX,
  46     SF_DEVICE_ID1_W25Q32,
  47     {
  48       SPI_COMMAND_WRITE_ENABLE,
  49       SPI_COMMAND_WRITE_S_EN
  50     },
  51     {
  52       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
  53       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
  54       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
  55       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
  56       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
  57       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
  58       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
  59       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
  60     },
  61     0x400000 - FLASH_SIZE, // BIOS Start Offset
  62     FLASH_SIZE   // BIOS image size in flash
  63   },
  64   //
  65   // Winbond 32Mbit part
  66   //
  67   {
  68     SPI_W25X32_ID1,
  69     SPI_W25X32_ID2,
  70     SPI_W25X32_ID3,
  71     {
  72       SPI_COMMAND_WRITE_ENABLE,
  73       SPI_COMMAND_WRITE_S_EN
  74     },
  75     {
  76       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
  77       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
  78       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
  79       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
  80       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
  81       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},
  82       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
  83       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
  84     },
  85     0x400000 - FLASH_SIZE, // BIOS Start Offset
  86     FLASH_SIZE   // BIOS image size in flash
  87   },
  88   //
  89   // Atmel 32Mbit part
  90   //
  91   {
  92     SPI_AT26DF321_ID1,
  93     SPI_AT26DF321_ID2,  // issue: byte 2 identifies family/density for Atmel
  94     SPI_AT26DF321_ID3,
  95     {
  96       SPI_COMMAND_WRITE_ENABLE,
  97       SPI_COMMAND_WRITE_S_EN
  98     },
  99     {
 100       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
 101       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
 102       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
 103       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
 104       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
 105       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
 106       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
 107       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
 108     },
 109     0x400000 - FLASH_SIZE, // BIOS Start Offset
 110     FLASH_SIZE   // BIOS image size in flash
 111   },
 112
 113   //
 114   // Intel 32Mbit part bottom boot
 115   //
 116   {
 117     SPI_QH25F320_ID1,
 118     SPI_QH25F320_ID2,
 119     SPI_QH25F320_ID3,
 120     {
 121       SPI_COMMAND_WRITE_ENABLE,
 122       SPI_COMMAND_WRITE_ENABLE
 123     },
 124     {
 125       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
 126       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
 127       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
 128       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
 129       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
 130       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
 131       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
 132       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
 133     },
 134     0,           // BIOS Start Offset
 135     FLASH_SIZE   // BIOS image size in flash
 136   },
 137   //
 138   // SST 64Mbit part
 139   //
 140   {
 141     SPI_SST25VF080B_ID1,      // VendorId
 142     SF_DEVICE_ID0_25VF064C,   // DeviceId 0
 143     SF_DEVICE_ID1_25VF064C,   // DeviceId 1
 144     {
 145       SPI_COMMAND_WRITE_ENABLE,
 146       SPI_COMMAND_WRITE_S_EN
 147     },
 148     {
 149       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 150       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 151       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 152       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 153       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 154       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 155       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 156       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 157     },
 158     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 159     FLASH_SIZE   // BIOS image size in flash
 160   },
 161   //
 162   // NUMONYX 64Mbit part
 163   //
 164   {
 165     SF_VENDOR_ID_NUMONYX,     // VendorId
 166     SF_DEVICE_ID0_M25PX64,    // DeviceId 0
 167     SF_DEVICE_ID1_M25PX64,    // DeviceId 1
 168     {
 169       SPI_COMMAND_WRITE_ENABLE,
 170       SPI_COMMAND_WRITE_S_EN
 171     },
 172     {
 173       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 174       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 175       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 176       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 177       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 178       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 179       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 180       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 181     },
 182     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 183     FLASH_SIZE   // BIOS image size in flash
 184   },
 185   //
 186   // Atmel 64Mbit part
 187   //
 188   {
 189     SF_VENDOR_ID_ATMEL,       // VendorId
 190     SF_DEVICE_ID0_AT25DF641,  // DeviceId 0
 191     SF_DEVICE_ID1_AT25DF641,  // DeviceId 1
 192     {
 193       SPI_COMMAND_WRITE_ENABLE,
 194       SPI_COMMAND_WRITE_S_EN
 195     },
 196     {
 197       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 198       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 199       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 200       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 201       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 202       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 203       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 204       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 205     },
 206     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 207     FLASH_SIZE   // BIOS image size in flash
 208   },
 209
 210   //
 211   // Spansion 64Mbit part
 212   //
 213   {
 214     SF_VENDOR_ID_SPANSION,       // VendorId
 215     SF_DEVICE_ID0_S25FL064K,  // DeviceId 0
 216     SF_DEVICE_ID1_S25FL064K,  // DeviceId 1
 217     {
 218       SPI_COMMAND_WRITE_ENABLE,
 219       SPI_COMMAND_WRITE_S_EN
 220     },
 221     {
 222       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 223       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 224       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 225       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 226       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 227       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 228       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 229       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 230     },
 231     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 232     FLASH_SIZE   // BIOS image size in flash
 233   },
 234
 235   //
 236   // Macronix 64Mbit part bottom boot
 237   //
 238   {
 239     SF_VENDOR_ID_MX,          // VendorId
 240     SF_DEVICE_ID0_25L6405D,   // DeviceId 0
 241     SF_DEVICE_ID1_25L6405D,   // DeviceId 1
 242     {
 243       SPI_COMMAND_WRITE_ENABLE,
 244       SPI_COMMAND_WRITE_S_EN
 245     },
 246     {
 247       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 248       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 249       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 250       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 251       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 252       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},
 253       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 254       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 255     },
 256     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 257     FLASH_SIZE   // BIOS image size in flash
 258   },
 259   //
 260   // Winbond 64Mbit part bottom boot
 261   //
 262   {
 263     SPI_W25X64_ID1,
 264     SF_DEVICE_ID0_W25QXX,
 265     SF_DEVICE_ID1_W25Q64,
 266     {
 267       SPI_COMMAND_WRITE_ENABLE,
 268       SPI_COMMAND_WRITE_S_EN
 269     },
 270     {
 271       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 272       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 273       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 274       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 275       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 276       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 277       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 278       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 279     },
 280     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 281     FLASH_SIZE   // BIOS image size in flash
 282   },
 283   //
 284   // Winbond 64Mbit part bottom boot
 285   //
 286   {
 287     SPI_W25X64_ID1,
 288     SPI_W25X64_ID2,
 289     SPI_W25X64_ID3,
 290     {
 291       SPI_COMMAND_WRITE_ENABLE,
 292       SPI_COMMAND_WRITE_S_EN
 293     },
 294     {
 295       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},
 296       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},
 297       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
 298       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
 299       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},
 300       {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
 301       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
 302       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
 303     },
 304     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 305     FLASH_SIZE   // BIOS image size in flash
 306   },
 307   //
 308   // Intel 64Mbit part bottom boot
 309   //
 310   {
 311     SPI_QH25F640_ID1,
 312     SPI_QH25F640_ID2,
 313     SPI_QH25F640_ID3,
 314     {
 315       SPI_COMMAND_WRITE_ENABLE,
 316       SPI_COMMAND_WRITE_S_EN
 317     },
 318     {
 319       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},
 320       {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},
 321       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
 322       {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
 323       {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},
 324       {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
 325       {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
 326       {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
 327     },
 328     0x800000 - FLASH_SIZE,          // BIOS Start Offset
 329     FLASH_SIZE   // BIOS image size in flash
 330   }
 331 };