QuarkSocPkg/QuarkNorthCluster/Include/QNCAccess.h

   1 /** @file
   2 Macros to simplify and abstract the interface to PCI configuration.
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8
   9 **/
  10
  11 #ifndef _QNC_ACCESS_H_
  12 #define _QNC_ACCESS_H_
  13
  14 #include "QuarkNcSocId.h"
  15 #include "QNCCommonDefinitions.h"
  16
  17 #define EFI_LPC_PCI_ADDRESS( Register ) \
  18   EFI_PCI_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, Register)
  19
  20 //
  21 // QNC Controller PCI access macros
  22 //
  23 #define QNC_RCRB_BASE (QNCMmio32 (PciDeviceMmBase (0, PCI_DEVICE_NUMBER_QNC_LPC, 0), R_QNC_LPC_RCBA) & B_QNC_LPC_RCBA_MASK)
  24
  25 //
  26 // Device 0x1f, Function 0
  27 //
  28
  29 #define LpcPciCfg32( Register ) \
  30   QNCMmPci32(0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
  31
  32 #define LpcPciCfg32Or( Register, OrData ) \
  33   QNCMmPci32Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
  34
  35 #define LpcPciCfg32And( Register, AndData ) \
  36   QNCMmPci32And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
  37
  38 #define LpcPciCfg32AndThenOr( Register, AndData, OrData ) \
  39   QNCMmPci32AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
  40
  41 #define LpcPciCfg16( Register ) \
  42   QNCMmPci16( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
  43
  44 #define LpcPciCfg16Or( Register, OrData ) \
  45   QNCMmPci16Or(  0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
  46
  47 #define LpcPciCfg16And( Register, AndData ) \
  48   QNCMmPci16And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
  49
  50 #define LpcPciCfg16AndThenOr( Register, AndData, OrData ) \
  51   QNCMmPci16AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
  52
  53 #define LpcPciCfg8( Register ) \
  54   QNCMmPci8( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
  55
  56 #define LpcPciCfg8Or( Register, OrData ) \
  57   QNCMmPci8Or(  0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
  58
  59 #define LpcPciCfg8And( Register, AndData ) \
  60   QNCMmPci8And(  0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
  61
  62 #define LpcPciCfg8AndThenOr( Register, AndData, OrData ) \
  63   QNCMmPci8AndThenOr(  0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
  64
  65 //
  66 // Root Complex Register Block
  67 //
  68
  69 #define MmRcrb32( Register ) \
  70   QNCMmio32( QNC_RCRB_BASE, Register )
  71
  72 #define MmRcrb32Or( Register, OrData ) \
  73   QNCMmio32Or( QNC_RCRB_BASE, Register, OrData )
  74
  75 #define MmRcrb32And( Register, AndData ) \
  76   QNCMmio32And( QNC_RCRB_BASE, Register, AndData )
  77
  78 #define MmRcrb32AndThenOr( Register, AndData, OrData ) \
  79   QNCMmio32AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
  80
  81 #define MmRcrb16( Register ) \
  82   QNCMmio16( QNC_RCRB_BASE, Register )
  83
  84 #define MmRcrb16Or( Register, OrData ) \
  85   QNCMmio16Or( QNC_RCRB_BASE, Register, OrData )
  86
  87 #define MmRcrb16And( Register, AndData ) \
  88   QNCMmio16And( QNC_RCRB_BASE, Register, AndData )
  89
  90 #define MmRcrb16AndThenOr( Register, AndData, OrData ) \
  91   QNCMmio16AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
  92
  93 #define MmRcrb8( Register ) \
  94   QNCMmio8( QNC_RCRB_BASE, Register )
  95
  96 #define MmRcrb8Or( Register, OrData ) \
  97   QNCMmio8Or( QNC_RCRB_BASE, Register, OrData )
  98
  99 #define MmRcrb8And( Register, AndData ) \
 100   QNCMmio8And( QNC_RCRB_BASE, Register, AndData )
 101
 102 #define MmRcrb8AndThenOr( Register, AndData, OrData ) \
 103   QNCMmio8AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
 104
 105 //
 106 // Memory Controller PCI access macros
 107 //
 108
 109 //
 110 // Device 0, Function 0
 111 //
 112
 113 #define McD0PciCfg64(Register)                              QNCMmPci32           (0, MC_BUS, 0, 0, Register)
 114 #define McD0PciCfg64Or(Register, OrData)                    QNCMmPci32Or         (0, MC_BUS, 0, 0, Register, OrData)
 115 #define McD0PciCfg64And(Register, AndData)                  QNCMmPci32And        (0, MC_BUS, 0, 0, Register, AndData)
 116 #define McD0PciCfg64AndThenOr(Register, AndData, OrData)    QNCMmPci32AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)
 117
 118 #define McD0PciCfg32(Register)                              QNCMmPci32           (0, MC_BUS, 0, 0, Register)
 119 #define McD0PciCfg32Or(Register, OrData)                    QNCMmPci32Or         (0, MC_BUS, 0, 0, Register, OrData)
 120 #define McD0PciCfg32And(Register, AndData)                  QNCMmPci32And        (0, MC_BUS, 0, 0, Register, AndData)
 121 #define McD0PciCfg32AndThenOr(Register, AndData, OrData)    QNCMmPci32AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)
 122
 123 #define McD0PciCfg16(Register)                              QNCMmPci16           (0, MC_BUS, 0, 0, Register)
 124 #define McD0PciCfg16Or(Register, OrData)                    QNCMmPci16Or         (0, MC_BUS, 0, 0, Register, OrData)
 125 #define McD0PciCfg16And(Register, AndData)                  QNCMmPci16And        (0, MC_BUS, 0, 0, Register, AndData)
 126 #define McD0PciCfg16AndThenOr(Register, AndData, OrData)    QNCMmPci16AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)
 127
 128 #define McD0PciCfg8(Register)                               QNCMmPci8            (0, MC_BUS, 0, 0, Register)
 129 #define McD0PciCfg8Or(Register, OrData)                     QNCMmPci8Or          (0, MC_BUS, 0, 0, Register, OrData)
 130 #define McD0PciCfg8And(Register, AndData)                   QNCMmPci8And         (0, MC_BUS, 0, 0, Register, AndData)
 131 #define McD0PciCfg8AndThenOr( Register, AndData, OrData )   QNCMmPci8AndThenOr   (0, MC_BUS, 0, 0, Register, AndData, OrData)
 132
 133
 134 //
 135 // Memory Controller Hub Memory Mapped IO register access ???
 136 //
 137 #define MCH_REGION_BASE                     (McD0PciCfg64 (MC_MCHBAR_OFFSET) & ~BIT0)
 138 #define McMmioAddress(Register)             ((UINTN) MCH_REGION_BASE + (UINTN) (Register))
 139
 140 #define McMmio32Ptr(Register)               ((volatile UINT32*) McMmioAddress (Register))
 141 #define McMmio64Ptr(Register)               ((volatile UINT64*) McMmioAddress (Register))
 142
 143 #define McMmio64(Register)                            *McMmio64Ptr( Register )
 144 #define McMmio64Or(Register, OrData)                  (McMmio64 (Register) |= (UINT64)(OrData))
 145 #define McMmio64And(Register, AndData)                (McMmio64 (Register) &= (UINT64)(AndData))
 146 #define McMmio64AndThenOr(Register, AndData, OrData)  (McMmio64 ( Register ) = (McMmio64( Register ) & (UINT64)(AndData)) | (UINT64)(OrData))
 147
 148 #define McMmio32(Register)                            *McMmio32Ptr (Register)
 149 #define McMmio32Or(Register, OrData)                  (McMmio32 (Register) |= (UINT32)(OrData))
 150 #define McMmio32And(Register, AndData)                (McMmio32 (Register) &= (UINT32)(AndData))
 151 #define McMmio32AndThenOr(Register, AndData, OrData)  (McMmio32 (Register) = (McMmio32 (Register) & (UINT32) (AndData)) | (UINT32) (OrData))
 152
 153 #define McMmio16Ptr(Register)                         ((volatile UINT16*) McMmioAddress (Register))
 154 #define McMmio16(Register)                            *McMmio16Ptr (Register)
 155 #define McMmio16Or(Register, OrData)                  (McMmio16 (Register) |= (UINT16) (OrData))
 156 #define McMmio16And(Register, AndData)                (McMmio16 (Register) &= (UINT16) (AndData))
 157 #define McMmio16AndThenOr(Register, AndData, OrData)  (McMmio16 (Register) = (McMmio16 (Register) & (UINT16) (AndData)) | (UINT16) (OrData))
 158
 159 #define McMmio8Ptr(Register)                          ((volatile UINT8 *)McMmioAddress (Register))
 160 #define McMmio8(Register)                             *McMmio8Ptr (Register)
 161 #define McMmio8Or(Register, OrData)                   (McMmio8 (Register) |= (UINT8) (OrData))
 162 #define McMmio8And(Register, AndData)                 (McMmio8 (Register) &= (UINT8) (AndData))
 163 #define McMmio8AndThenOr(Register, AndData, OrData)   (McMmio8 (Register) = (McMmio8 (Register) & (UINT8) (AndData)) | (UINT8) (OrData))
 164
 165 //
 166 // QNC memory mapped related data structure deifinition
 167 //
 168 typedef enum {
 169   QNCMmioWidthUint8  = 0,
 170   QNCMmioWidthUint16 = 1,
 171   QNCMmioWidthUint32 = 2,
 172   QNCMmioWidthUint64 = 3,
 173   QNCMmioWidthMaximum
 174 } QNC_MEM_IO_WIDTH;
 175
 176 #endif
 177