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git.proxmox.com Git - mirror_edk2.git/blob - QuarkSocPkg/QuarkNorthCluster/Include/QNCCommonDefinitions.h
2 This header file provides common definitions just for MCH using to avoid including extra module's file.
4 Copyright (c) 2013-2015 Intel Corporation.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _QNC_COMMON_DEFINITIONS_H_
17 #define _QNC_COMMON_DEFINITIONS_H_
20 // PCI CONFIGURATION MAP REGISTER OFFSETS
23 #define PCI_VID 0x0000 // Vendor ID Register
24 #define PCI_DID 0x0002 // Device ID Register
25 #define PCI_CMD 0x0004 // PCI Command Register
26 #define PCI_STS 0x0006 // PCI Status Register
27 #define PCI_RID 0x0008 // Revision ID Register
28 #define PCI_IFT 0x0009 // Interface Type
29 #define PCI_SCC 0x000A // Sub Class Code Register
30 #define PCI_BCC 0x000B // Base Class Code Register
31 #define PCI_CLS 0x000C // Cache Line Size
32 #define PCI_PMLT 0x000D // Primary Master Latency Timer
33 #define PCI_HDR 0x000E // Header Type Register
34 #define PCI_BIST 0x000F // Built in Self Test Register
35 #define PCI_BAR0 0x0010 // Base Address Register 0
36 #define PCI_BAR1 0x0014 // Base Address Register 1
37 #define PCI_BAR2 0x0018 // Base Address Register 2
38 #define PCI_PBUS 0x0018 // Primary Bus Number Register
39 #define PCI_SBUS 0x0019 // Secondary Bus Number Register
40 #define PCI_SUBUS 0x001A // Subordinate Bus Number Register
41 #define PCI_SMLT 0x001B // Secondary Master Latency Timer
42 #define PCI_BAR3 0x001C // Base Address Register 3
43 #define PCI_IOBASE 0x001C // I/O base Register
44 #define PCI_IOLIMIT 0x001D // I/O Limit Register
45 #define PCI_SECSTATUS 0x001E // Secondary Status Register
46 #define PCI_BAR4 0x0020 // Base Address Register 4
47 #define PCI_MEMBASE 0x0020 // Memory Base Register
48 #define PCI_MEMLIMIT 0x0022 // Memory Limit Register
49 #define PCI_BAR5 0x0024 // Base Address Register 5
50 #define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register
51 #define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register
52 #define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits
53 #define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits
54 #define PCI_SVID 0x002C // Subsystem Vendor ID
55 #define PCI_SID 0x002E // Subsystem ID
56 #define PCI_IOBASE_U 0x0030 // I/O base Upper Register
57 #define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register
58 #define PCI_CAPP 0x0034 // Capabilities Pointer
59 #define PCI_EROM 0x0038 // Expansion ROM Base Address
60 #define PCI_INTLINE 0x003C // Interrupt Line Register
61 #define PCI_INTPIN 0x003D // Interrupt Pin Register
62 #define PCI_MAXGNT 0x003E // Max Grant Register
63 #define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register
64 #define PCI_MAXLAT 0x003F // Max Latency Register
86 #define BIT16 0x00010000
87 #define BIT17 0x00020000
88 #define BIT18 0x00040000
89 #define BIT19 0x00080000
90 #define BIT20 0x00100000
91 #define BIT21 0x00200000
92 #define BIT22 0x00400000
93 #define BIT23 0x00800000
94 #define BIT24 0x01000000
95 #define BIT25 0x02000000
96 #define BIT26 0x04000000
97 #define BIT27 0x08000000
98 #define BIT28 0x10000000
99 #define BIT29 0x20000000
100 #define BIT30 0x40000000
101 #define BIT31 0x80000000
106 // Common Memory mapped Io access macros ------------------------------------------
108 #define QNCMmioAddress( BaseAddr, Register ) \
109 ( (UINTN)BaseAddr + \
116 #define QNCMmio64Ptr( BaseAddr, Register ) \
117 ( (volatile UINT64 *)QNCMmioAddress( BaseAddr, Register ) )
119 #define QNCMmio64( BaseAddr, Register ) \
120 *QNCMmio64Ptr( BaseAddr, Register )
122 #define QNCMmio64Or( BaseAddr, Register, OrData ) \
123 QNCMmio64( BaseAddr, Register ) = \
125 QNCMmio64( BaseAddr, Register ) | \
129 #define QNCMmio64And( BaseAddr, Register, AndData ) \
130 QNCMmio64( BaseAddr, Register ) = \
132 QNCMmio64( BaseAddr, Register ) & \
136 #define QNCMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \
137 QNCMmio64( BaseAddr, Register ) = \
139 ( QNCMmio64( BaseAddr, Register ) & \
148 #define QNCMmio32Ptr( BaseAddr, Register ) \
149 ( (volatile UINT32 *)QNCMmioAddress( BaseAddr, Register ) )
151 #define QNCMmio32( BaseAddr, Register ) \
152 *QNCMmio32Ptr( BaseAddr, Register )
154 #define QNCMmio32Or( BaseAddr, Register, OrData ) \
155 QNCMmio32( BaseAddr, Register ) = \
157 QNCMmio32( BaseAddr, Register ) | \
161 #define QNCMmio32And( BaseAddr, Register, AndData ) \
162 QNCMmio32( BaseAddr, Register ) = \
164 QNCMmio32( BaseAddr, Register ) & \
168 #define QNCMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
169 QNCMmio32( BaseAddr, Register ) = \
171 ( QNCMmio32( BaseAddr, Register ) & \
180 #define QNCMmio16Ptr( BaseAddr, Register ) \
181 ( (volatile UINT16 *)QNCMmioAddress( BaseAddr, Register ) )
183 #define QNCMmio16( BaseAddr, Register ) \
184 *QNCMmio16Ptr( BaseAddr, Register )
186 #define QNCMmio16Or( BaseAddr, Register, OrData ) \
187 QNCMmio16( BaseAddr, Register ) = \
189 QNCMmio16( BaseAddr, Register ) | \
193 #define QNCMmio16And( BaseAddr, Register, AndData ) \
194 QNCMmio16( BaseAddr, Register ) = \
196 QNCMmio16( BaseAddr, Register ) & \
200 #define QNCMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
201 QNCMmio16( BaseAddr, Register ) = \
203 ( QNCMmio16( BaseAddr, Register ) & \
211 #define QNCMmio8Ptr( BaseAddr, Register ) \
212 ( (volatile UINT8 *)QNCMmioAddress( BaseAddr, Register ) )
214 #define QNCMmio8( BaseAddr, Register ) \
215 *QNCMmio8Ptr( BaseAddr, Register )
217 #define QNCMmio8Or( BaseAddr, Register, OrData ) \
218 QNCMmio8( BaseAddr, Register ) = \
220 QNCMmio8( BaseAddr, Register ) | \
224 #define QNCMmio8And( BaseAddr, Register, AndData ) \
225 QNCMmio8( BaseAddr, Register ) = \
227 QNCMmio8( BaseAddr, Register ) & \
231 #define QNCMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
232 QNCMmio8( BaseAddr, Register ) = \
234 ( QNCMmio8( BaseAddr, Register ) & \
241 // Common Memory mapped Pci access macros ------------------------------------------
244 #define QNCMmPciAddress( Segment, Bus, Device, Function, Register ) \
245 ( (UINTN) QncGetPciExpressBaseAddress() + \
246 (UINTN)(Bus << 20) + \
247 (UINTN)(Device << 15) + \
248 (UINTN)(Function << 12) + \
253 // Macro to calculate the Pci device's base memory mapped address
255 #define PciDeviceMmBase( Bus, Device, Function) \
256 ( (UINTN) QncGetPciExpressBaseAddress () + \
257 (UINTN)(Bus << 20) + \
258 (UINTN)(Device << 15) + \
259 (UINTN)(Function << 12) \
265 #define QNCMmPci32Ptr( Segment, Bus, Device, Function, Register ) \
266 ( (volatile UINT32 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )
268 #define QNCMmPci32( Segment, Bus, Device, Function, Register ) \
269 *QNCMmPci32Ptr( Segment, Bus, Device, Function, Register )
271 #define QNCMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
272 QNCMmPci32( Segment, Bus, Device, Function, Register ) = \
274 QNCMmPci32( Segment, Bus, Device, Function, Register ) | \
278 #define QNCMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
279 QNCMmPci32( Segment, Bus, Device, Function, Register ) = \
281 QNCMmPci32( Segment, Bus, Device, Function, Register ) & \
285 #define QNCMmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
286 QNCMmPci32( Segment, Bus, Device, Function, Register ) = \
288 ( QNCMmPci32( Segment, Bus, Device, Function, Register ) & \
296 #define QNCMmPci16Ptr( Segment, Bus, Device, Function, Register ) \
297 ( (volatile UINT16 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )
299 #define QNCMmPci16( Segment, Bus, Device, Function, Register ) \
300 *QNCMmPci16Ptr( Segment, Bus, Device, Function, Register )
302 #define QNCMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
303 QNCMmPci16( Segment, Bus, Device, Function, Register ) = \
305 QNCMmPci16( Segment, Bus, Device, Function, Register ) | \
309 #define QNCMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
310 QNCMmPci16( Segment, Bus, Device, Function, Register ) = \
312 QNCMmPci16( Segment, Bus, Device, Function, Register ) & \
316 #define QNCMmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
317 QNCMmPci16( Segment, Bus, Device, Function, Register ) = \
319 ( QNCMmPci16( Segment, Bus, Device, Function, Register ) & \
327 #define QNCMmPci8Ptr( Segment, Bus, Device, Function, Register ) \
328 ( (volatile UINT8 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )
330 #define QNCMmPci8( Segment, Bus, Device, Function, Register ) \
331 *QNCMmPci8Ptr( Segment, Bus, Device, Function, Register )
333 #define QNCMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
334 QNCMmPci8( Segment, Bus, Device, Function, Register ) = \
336 QNCMmPci8( Segment, Bus, Device, Function, Register ) | \
340 #define QNCMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
341 QNCMmPci8( Segment, Bus, Device, Function, Register ) = \
343 QNCMmPci8( Segment, Bus, Device, Function, Register ) & \
347 #define QNCMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
348 QNCMmPci8( Segment, Bus, Device, Function, Register ) = \
350 ( QNCMmPci8( Segment, Bus, Device, Function, Register ) & \