QuarkSocPkg/QuarkSouthCluster/Include/MMC.h

   1 /** @file
   2
   3 Header file for Industry MMC 4.2 spec.
   4
   5 Copyright (c) 2013-2015 Intel Corporation.
   6
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef _MMC_H
  12 #define _MMC_H
  13
  14 #pragma pack(1)
  15 //
  16 //Command definition
  17 //
  18
  19 #define  CMD0              0
  20 #define  CMD1              1
  21 #define  CMD2              2
  22 #define  CMD3              3
  23 #define  CMD4              4
  24 #define  CMD6              6
  25 #define  CMD7              7
  26 #define  CMD8              8
  27 #define  CMD9              9
  28 #define  CMD10             10
  29 #define  CMD11             11
  30 #define  CMD12             12
  31 #define  CMD13             13
  32 #define  CMD14             14
  33 #define  CMD15             15
  34 #define  CMD16             16
  35 #define  CMD17             17
  36 #define  CMD18             18
  37 #define  CMD19             19
  38 #define  CMD20             20
  39 #define  CMD23             23
  40 #define  CMD24             24
  41 #define  CMD25             25
  42 #define  CMD26             26
  43 #define  CMD27             27
  44 #define  CMD28             28
  45 #define  CMD29             29
  46 #define  CMD30             30
  47 #define  CMD35             35
  48 #define  CMD36             36
  49 #define  CMD38             38
  50 #define  CMD39             39
  51 #define  CMD40             40
  52 #define  CMD42             42
  53 #define  CMD55             55
  54 #define  CMD56             56
  55
  56
  57
  58 #define  GO_IDLE_STATE           CMD0
  59 #define  SEND_OP_COND            CMD1
  60 #define  ALL_SEND_CID            CMD2
  61 #define  SET_RELATIVE_ADDR       CMD3
  62 #define  SET_DSR                 CMD4
  63 #define  SWITCH                  CMD6
  64 #define  SELECT_DESELECT_CARD    CMD7
  65 #define  SEND_EXT_CSD            CMD8
  66 #define  SEND_CSD                CMD9
  67 #define  SEND_CID                CMD10
  68 #define  READ_DAT_UNTIL_STOP     CMD11
  69 #define  STOP_TRANSMISSION       CMD12
  70 #define  SEND_STATUS             CMD13
  71 #define  BUSTEST_R               CMD14
  72 #define  GO_INACTIVE_STATE       CMD15
  73 #define  SET_BLOCKLEN            CMD16
  74 #define  READ_SINGLE_BLOCK       CMD17
  75 #define  READ_MULTIPLE_BLOCK     CMD18
  76 #define  BUSTEST_W               CMD19
  77 #define  WRITE_DAT_UNTIL_STOP    CMD20
  78 #define  SET_BLOCK_COUNT         CMD23
  79 #define  WRITE_BLOCK             CMD24
  80 #define  WRITE_MULTIPLE_BLOCK    CMD25
  81 #define  PROGRAM_CID             CMD26
  82 #define  PROGRAM_CSD             CMD27
  83 #define  SET_WRITE_PROT          CMD28
  84 #define  CLR_WRITE_PROT          CMD29
  85 #define  SEND_WRITE_PROT         CMD30
  86 #define  ERASE_GROUP_START       CMD35
  87 #define  ERASE_GROUP_END         CMD36
  88 #define  ERASE                   CMD38
  89 #define  FAST_IO                 CMD39
  90 #define  GO_IRQ_STATE            CMD40
  91 #define  LOCK_UNLOCK             CMD42
  92 #define  APP_CMD                 CMD55
  93 #define  GEN_CMD                 CMD56
  94
  95
  96 #define CMD_INDEX_MASK           0x3F
  97 #define AUTO_CMD12_ENABLE        BIT6
  98 #define AUTO_CMD23_ENABLE        BIT7
  99
 100 #define FREQUENCY_OD            (400 * 1000)
 101 #define FREQUENCY_MMC_PP        (26 * 1000 * 1000)
 102 #define FREQUENCY_MMC_PP_HIGH   (52 * 1000 * 1000)
 103
 104 #define DEFAULT_DSR_VALUE        0x404
 105
 106 //
 107 //Registers definition
 108 //
 109
 110 typedef struct {
 111   UINT32  Reserved0:   7;  // 0
 112   UINT32  V170_V195:   1;  // 1.70V - 1.95V
 113   UINT32  V200_V260:   7;  // 2.00V - 2.60V
 114   UINT32  V270_V360:   9;  // 2.70V - 3.60V
 115   UINT32  Reserved1:   5;  // 0
 116   UINT32  AccessMode:  2;  // 00b (byte mode), 10b (sector mode)
 117   UINT32  Busy:        1;  // This bit is set to LOW if the card has not finished the power up routine
 118 }OCR;
 119
 120
 121 typedef struct {
 122   UINT8   NotUsed:     1; //  1
 123   UINT8   CRC:         7; //  CRC7 checksum
 124   UINT8   MDT;            //  Manufacturing date
 125   UINT32  PSN;            //  Product serial number
 126   UINT8   PRV;            //  Product revision
 127   UINT8   PNM[6];         //  Product name
 128   UINT16  OID;            //  OEM/Application ID
 129   UINT8   MID;            //  Manufacturer ID
 130 }CID;
 131
 132
 133 typedef struct {
 134   UINT8   NotUsed:            1; //  1 [0:0]
 135   UINT8   CRC:                7; //  CRC [7:1]
 136   UINT8   ECC:                2; //  ECC code [9:8]
 137   UINT8   FILE_FORMAT:        2; //  File format [11:10]
 138   UINT8   TMP_WRITE_PROTECT:  1; //  Temporary write protection [12:12]
 139   UINT8   PERM_WRITE_PROTECT: 1; //  Permanent write protection [13:13]
 140   UINT8   COPY:               1; //  Copy flag (OTP) [14:14]
 141   UINT8   FILE_FORMAT_GRP:    1; //  File format group [15:15]
 142   UINT16  CONTENT_PROT_APP:   1; //  Content protection application [16:16]
 143   UINT16  Reserved0:          4; //  0 [20:17]
 144   UINT16  WRITE_BL_PARTIAL:   1; //  Partial blocks for write allowed [21:21]
 145   UINT16  WRITE_BL_LEN:       4; //  Max. write data block length [25:22]
 146   UINT16  R2W_FACTOR:         3; //  Write speed factor [28:26]
 147   UINT16  DEFAULT_ECC:        2; //  Manufacturer default ECC [30:29]
 148   UINT16  WP_GRP_ENABLE:      1; //  Write protect group enable [31:31]
 149   UINT32  WP_GRP_SIZE:        5; //  Write protect group size [36:32]
 150   UINT32  ERASE_GRP_MULT:     5; //  Erase group size multiplier [41:37]
 151   UINT32  ERASE_GRP_SIZE:     5; //  Erase group size [46:42]
 152   UINT32  C_SIZE_MULT:        3; //  Device size multiplier [49:47]
 153   UINT32  VDD_W_CURR_MAX:     3; //  Max. write current @ VDD max [52:50]
 154   UINT32  VDD_W_CURR_MIN:     3; //  Max. write current @ VDD min [55:53]
 155   UINT32  VDD_R_CURR_MAX:     3; //  Max. read current @ VDD max [58:56]
 156   UINT32  VDD_R_CURR_MIN:     3; //  Max. read current @ VDD min [61:59]
 157   UINT32  C_SIZELow2:         2;//  Device size [73:62]
 158   UINT32  C_SIZEHigh10:       10;//  Device size [73:62]
 159   UINT32  Reserved1:          2; //  0 [75:74]
 160   UINT32  DSR_IMP:            1; //  DSR implemented [76:76]
 161   UINT32  READ_BLK_MISALIGN:  1; //  Read block misalignment [77:77]
 162   UINT32  WRITE_BLK_MISALIGN: 1; //  Write block misalignment [78:78]
 163   UINT32  READ_BL_PARTIAL:    1; //  Partial blocks for read allowed [79:79]
 164   UINT32  READ_BL_LEN:        4; //  Max. read data block length [83:80]
 165   UINT32  CCC:                12;//  Card command classes [95:84]
 166   UINT8   TRAN_SPEED          ; //  Max. bus clock frequency [103:96]
 167   UINT8   NSAC                ; //  Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
 168   UINT8   TAAC                ; //  Data read access-time 1 [119:112]
 169   UINT8   Reserved2:          2; //  0 [121:120]
 170   UINT8   SPEC_VERS:          4; //  System specification version [125:122]
 171   UINT8   CSD_STRUCTURE:      2; //  CSD structure [127:126]
 172 }CSD;
 173
 174 typedef struct {
 175   UINT8  Reserved0[181];         //  0 [0:180]
 176   UINT8  ERASED_MEM_CONT;        //  Erased Memory Content [181]
 177   UINT8  Reserved2;              //  Erased Memory Content [182]
 178   UINT8  BUS_WIDTH;              //  Bus Width Mode [183]
 179   UINT8  Reserved3;              //  0 [184]
 180   UINT8  HS_TIMING;              //  High Speed Interface Timing [185]
 181   UINT8  Reserved4;              //  0 [186]
 182   UINT8  POWER_CLASS;            //  Power Class [187]
 183   UINT8  Reserved5;              //  0 [188]
 184   UINT8  CMD_SET_REV;            //  Command Set Revision [189]
 185   UINT8  Reserved6;              //  0 [190]
 186   UINT8  CMD_SET;                //  Command Set [191]
 187   UINT8  EXT_CSD_REV;            //  Extended CSD Revision [192]
 188   UINT8  Reserved7;              //  0 [193]
 189   UINT8  CSD_STRUCTURE;          //  CSD Structure Version [194]
 190   UINT8  Reserved8;              //  0 [195]
 191   UINT8  CARD_TYPE;              //  Card Type [196]
 192   UINT8  Reserved9[3];           //  0 [199:197]
 193   UINT8  PWR_CL_52_195;          //  Power Class for 52MHz @ 1.95V [200]
 194   UINT8  PWR_CL_26_195;          //  Power Class for 26MHz @ 1.95V [201]
 195   UINT8  PWR_CL_52_360;          //  Power Class for 52MHz @ 3.6V [202]
 196   UINT8  PWR_CL_26_360;          //  Power Class for 26MHz @ 3.6V [203]
 197   UINT8  Reserved10;             //  0 [204]
 198   UINT8  MIN_PERF_R_4_26;        //  Minimum Read Performance for 4bit @26MHz [205]
 199   UINT8  MIN_PERF_W_4_26;        //  Minimum Write Performance for 4bit @26MHz [206]
 200   UINT8  MIN_PERF_R_8_26_4_52;   //  Minimum Read Performance for 8bit @26MHz/4bit @52MHz [207]
 201   UINT8  MIN_PERF_W_8_26_4_52;   //  Minimum Write Performance for 8bit @26MHz/4bit @52MHz [208]
 202   UINT8  MIN_PERF_R_8_52;        //  Minimum Read Performance for 8bit @52MHz [209]
 203   UINT8  MIN_PERF_W_8_52;        //  Minimum Write Performance for 8bit @52MHz [210]
 204   UINT8  Reserved11;             //  0 [211]
 205   UINT8  SEC_COUNT[4];           //  Sector Count [215:212]
 206   UINT8  Reserved12[288];        //  0 [503:216]
 207   UINT8  S_CMD_SET;              //  Sector Count [504]
 208   UINT8  Reserved13[7];          //  Sector Count [511:505]
 209 }EXT_CSD;
 210
 211
 212 //
 213 //Card Status definition
 214 //
 215 typedef struct {
 216   UINT32  Reserved0:           2; //Reserved for Manufacturer Test Mode
 217   UINT32  Reserved1:           2; //Reserved for Application Specific commands
 218   UINT32  Reserved2:           1; //
 219   UINT32  SAPP_CMD:            1; //
 220   UINT32  Reserved3:           1; //Reserved
 221   UINT32  SWITCH_ERROR:        1; //
 222   UINT32  READY_FOR_DATA:      1; //
 223   UINT32  CURRENT_STATE:       4; //
 224   UINT32  ERASE_RESET:         1; //
 225   UINT32  Reserved4:           1; //Reserved
 226   UINT32  WP_ERASE_SKIP:       1; //
 227   UINT32  CID_CSD_OVERWRITE:   1; //
 228   UINT32  OVERRUN:             1; //
 229   UINT32  UNDERRUN:            1; //
 230   UINT32  ERROR:               1; //
 231   UINT32  CC_ERROR:            1; //
 232   UINT32  CARD_ECC_FAILED:     1; //
 233   UINT32  ILLEGAL_COMMAND:     1; //
 234   UINT32  COM_CRC_ERROR:       1; //
 235   UINT32  LOCK_UNLOCK_FAILED:  1; //
 236   UINT32  CARD_IS_LOCKED:      1; //
 237   UINT32  WP_VIOLATION:        1; //
 238   UINT32  ERASE_PARAM:         1; //
 239   UINT32  ERASE_SEQ_ERROR:     1; //
 240   UINT32  BLOCK_LEN_ERROR:     1; //
 241   UINT32  ADDRESS_MISALIGN:    1; //
 242   UINT32  ADDRESS_OUT_OF_RANGE:1; //
 243 }CARD_STATUS;
 244
 245 typedef struct {
 246   UINT32  CmdSet:              3;
 247   UINT32  Reserved0:           5;
 248   UINT32  Value:               8;
 249   UINT32  Index:               8;
 250   UINT32  Access:              2;
 251   UINT32  Reserved1:           6;
 252 }SWITCH_ARGUMENT;
 253
 254 #define CommandSet_Mode          0
 255 #define SetBits_Mode             1
 256 #define ClearBits_Mode           2
 257 #define WriteByte_Mode           3
 258
 259
 260 #define  Idle_STATE              0
 261 #define  Ready_STATE             1
 262 #define  Ident_STATE             2
 263 #define  Stby_STATE              3
 264 #define  Tran_STATE              4
 265 #define  Data_STATE              5
 266 #define  Rcv_STATE               6
 267 #define  Prg_STATE               7
 268 #define  Dis_STATE               8
 269 #define  Btst_STATE              9
 270
 271
 272
 273 #pragma pack()
 274 #endif