QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciReg.h

   1 /** @file
   2 This file contains the definination for host controller
   3 register operation routines.
   4
   5 Copyright (c) 2013-2015 Intel Corporation.
   6
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11
  12
  13 #ifndef   _OHCI_REGS_H
  14 #define   _OHCI_REGS_H
  15
  16 #define   HC_STATE_RESET         0x0
  17 #define   HC_STATE_RESUME        0x1
  18 #define   HC_STATE_OPERATIONAL   0x2
  19 #define   HC_STATE_SUSPEND       0x3
  20
  21 #define   PERIODIC_ENABLE               0x01
  22 #define   ISOCHRONOUS_ENABLE            0x02
  23 #define   CONTROL_ENABLE                0x04
  24 #define   BULK_ENABLE                   0x08
  25 #define   CONTROL_BULK_RATIO            0x10
  26
  27 #define   HC_FUNCTIONAL_STATE    0x20
  28 #define   INTERRUPT_ROUTING      0x40
  29
  30 #define   HC_RESET               0x01
  31 #define   CONTROL_LIST_FILLED    0x02
  32 #define   BULK_LIST_FILLED       0x04
  33 #define   CHANGE_OWNER_REQUEST   0x08
  34
  35 #define   SCHEDULE_OVERRUN_COUNT 0x10
  36
  37 #define   SCHEDULE_OVERRUN       0x00001
  38 #define   WRITEBACK_DONE_HEAD    0x00002
  39 #define   START_OF_FRAME         0x00004
  40 #define   RESUME_DETECT          0x00008
  41 #define   UNRECOVERABLE_ERROR    0x00010
  42 #define   FRAME_NUMBER_OVERFLOW  0x00020
  43 #define   ROOTHUB_STATUS_CHANGE  0x00040
  44 #define   OWNERSHIP_CHANGE       0x00080
  45
  46 #define   MASTER_INTERRUPT       0x00400
  47
  48 #define   CONTROL_HEAD           0x001
  49 #define   BULK_HEAD              0x002
  50 #define   DONE_HEAD              0x004
  51
  52 #define   Hc_HCCA                0x001
  53 #define   Hc_PERIODIC_CURRENT    0x002
  54 #define   Hc_CONTOL_HEAD         0x004
  55 #define   Hc_CONTROL_CURRENT_PTR 0x008
  56 #define   Hc_BULK_HEAD           0x010
  57 #define   Hc_BULK_CURRENT_PTR    0x020
  58 #define   Hc_DONE_HEAD           0x040
  59
  60 #define   FRAME_INTERVAL         0x008
  61 #define   FS_LARGEST_DATA_PACKET 0x010
  62 #define   FRMINT_TOGGLE          0x020
  63 #define   FRAME_REMAINING        0x040
  64 #define   FRAME_REMAIN_TOGGLE    0x080
  65
  66 #define   RH_DESC_A              0x00001
  67 #define   RH_DESC_B              0x00002
  68 #define   RH_NUM_DS_PORTS        0x00004
  69 #define   RH_NO_PSWITCH          0x00008
  70 #define   RH_PSWITCH_MODE        0x00010
  71 #define   RH_DEVICE_TYPE         0x00020
  72 #define   RH_OC_PROT_MODE        0x00040
  73 #define   RH_NOC_PROT            0x00080
  74 #define   RH_POTPGT              0x00100
  75 #define   RH_NO_POTPGT           0x00200
  76 #define   RH_DEV_REMOVABLE       0x00400
  77 #define   RH_PORT_PWR_CTRL_MASK  0x00800
  78
  79 #define   RH_LOCAL_PSTAT         0x00001
  80 #define   RH_OC_ID               0x00002
  81 #define   RH_REMOTE_WK_ENABLE    0x00004
  82 #define   RH_LOCAL_PSTAT_CHANGE  0x00008
  83 #define   RH_OC_ID_CHANGE        0x00010
  84 #define   RH_CLR_RMT_WK_ENABLE   0x00020
  85
  86 #define   RH_CLEAR_PORT_ENABLE        0x0001
  87 #define   RH_SET_PORT_ENABLE          0x0002
  88 #define   RH_SET_PORT_SUSPEND         0x0004
  89 #define   RH_CLEAR_SUSPEND_STATUS     0x0008
  90 #define   RH_SET_PORT_RESET           0x0010
  91 #define   RH_SET_PORT_POWER           0x0020
  92 #define   RH_CLEAR_PORT_POWER         0x0040
  93 #define   RH_CONNECT_STATUS_CHANGE    0x10000
  94 #define   RH_PORT_ENABLE_STAT_CHANGE  0x20000
  95 #define   RH_PORT_SUSPEND_STAT_CHANGE 0x40000
  96 #define   RH_OC_INDICATOR_CHANGE      0x80000
  97 #define   RH_PORT_RESET_STAT_CHANGE   0x100000
  98
  99 #define   RH_CURR_CONNECT_STAT        0x0001
 100 #define   RH_PORT_ENABLE_STAT         0x0002
 101 #define   RH_PORT_SUSPEND_STAT        0x0004
 102 #define   RH_PORT_OC_INDICATOR        0x0008
 103 #define   RH_PORT_RESET_STAT          0x0010
 104 #define   RH_PORT_POWER_STAT          0x0020
 105 #define   RH_LSDEVICE_ATTACHED        0x0040
 106
 107 #define   RESET_SYSTEM_BUS            (1 << 0)
 108 #define   RESET_HOST_CONTROLLER       (1 << 1)
 109 #define   RESET_CLOCK_GENERATION      (1 << 2)
 110 #define   RESET_SSE_GLOBAL            (1 << 5)
 111 #define   RESET_PSPL                  (1 << 6)
 112 #define   RESET_PCPL                  (1 << 7)
 113 #define   RESET_SSEP1                 (1 << 9)
 114 #define   RESET_SSEP2                 (1 << 10)
 115 #define   RESET_SSEP3                 (1 << 11)
 116
 117 #define ONE_SECOND                      1000000
 118 #define ONE_MILLI_SEC                   1000
 119 #define MAX_BYTES_PER_TD                0x1000
 120 #define MAX_RETRY_TIMES                 100
 121 #define PORT_NUMBER_ON_MAINSTONE2       1
 122
 123
 124 //
 125 // Operational Register Offsets
 126 //
 127
 128 //
 129 // Command & Status Registers Offsets
 130 //
 131 #define HC_REVISION             0x00
 132 #define HC_CONTROL              0x04
 133 #define HC_COMMAND_STATUS       0x08
 134 #define HC_INTERRUPT_STATUS     0x0C
 135 #define HC_INTERRUPT_ENABLE     0x10
 136 #define HC_INTERRUPT_DISABLE    0x14
 137
 138 //
 139 // Memory Pointer Offsets
 140 //
 141 #define HC_HCCA                 0x18
 142 #define HC_PERIODIC_CURRENT     0x1C
 143 #define HC_CONTROL_HEAD         0x20
 144 #define HC_CONTROL_CURRENT_PTR  0x24
 145 #define HC_BULK_HEAD            0x28
 146 #define HC_BULK_CURRENT_PTR     0x2C
 147 #define HC_DONE_HEAD            0x30
 148
 149 //
 150 // Frame Register Offsets
 151 //
 152 #define HC_FRM_INTERVAL         0x34
 153 #define HC_FRM_REMAINING        0x38
 154 #define HC_FRM_NUMBER           0x3C
 155 #define HC_PERIODIC_START       0x40
 156 #define HC_LS_THREASHOLD        0x44
 157
 158 //
 159 // Root Hub Register Offsets
 160 //
 161 #define HC_RH_DESC_A            0x48
 162 #define HC_RH_DESC_B            0x4C
 163 #define HC_RH_STATUS            0x50
 164 #define HC_RH_PORT_STATUS       0x54
 165
 166 #define USBHOST_OFFSET_UHCHR         0x64         // Usb Host reset register
 167
 168 #define OHC_BAR_INDEX               0
 169
 170 //
 171 // Usb Host controller register offset
 172 //
 173 #define USBHOST_OFFSET_UHCREV        0x0          // Usb Host revision register
 174 #define USBHOST_OFFSET_UHCHCON       0x4          // Usb Host control register
 175 #define USBHOST_OFFSET_UHCCOMS       0x8          // Usb Host Command Status register
 176 #define USBHOST_OFFSET_UHCINTS       0xC          // Usb Host Interrupt Status register
 177 #define USBHOST_OFFSET_UHCINTE       0x10         // Usb Host Interrupt Enable register
 178 #define USBHOST_OFFSET_UHCINTD       0x14         // Usb Host Interrupt Disable register
 179 #define USBHOST_OFFSET_UHCHCCA       0x18         // Usb Host Controller Communication Area
 180 #define USBHOST_OFFSET_UHCPCED       0x1C         // Usb Host Period Current Endpoint Descriptor
 181 #define USBHOST_OFFSET_UHCCHED       0x20         // Usb Host Control Head Endpoint Descriptor
 182 #define USBHOST_OFFSET_UHCCCED       0x24         // Usb Host Control Current Endpoint Descriptor
 183 #define USBHOST_OFFSET_UHCBHED       0x28         // Usb Host Bulk Head Endpoint Descriptor
 184 #define USBHOST_OFFSET_UHCBCED       0x2C         // Usb Host Bulk Current Endpoint Descriptor
 185 #define USBHOST_OFFSET_UHCDHEAD      0x30         // Usb Host Done Head register
 186 #define USBHOST_OFFSET_UHCFMI        0x34         // Usb Host Frame Interval register
 187 #define USBHOST_OFFSET_UHCFMR        0x38         // Usb Host Frame Remaining register
 188 #define USBHOST_OFFSET_UHCFMN        0x3C         // Usb Host Frame Number register
 189 #define USBHOST_OFFSET_UHCPERS       0x40         // Usb Host Periodic Start register
 190 #define USBHOST_OFFSET_UHCLST        0x44         // Usb Host Low-Speed Threshold register
 191 #define USBHOST_OFFSET_UHCRHDA       0x48         // Usb Host Root Hub Descriptor A register
 192 #define USBHOST_OFFSET_UHCRHDB       0x4C         // Usb Host Root Hub Descriptor B register
 193 #define USBHOST_OFFSET_UHCRHS        0x50         // Usb Host Root Hub Status register
 194 #define USBHOST_OFFSET_UHCRHPS1      0x54         // Usb Host Root Hub Port Status 1 register
 195
 196 //
 197 // Usb Host controller register bit fields
 198 //
 199 #pragma pack(1)
 200
 201 typedef struct {
 202   UINT8                   ProgInterface;
 203   UINT8                   SubClassCode;
 204   UINT8                   BaseCode;
 205 } USB_CLASSC;
 206
 207 typedef struct {
 208     UINT32 Revision:8;
 209     UINT32 Rsvd:24;
 210 } HcREVISION;
 211
 212 typedef struct {
 213     UINT32 ControlBulkRatio:2;
 214     UINT32 PeriodicEnable:1;
 215     UINT32 IsochronousEnable:1;
 216     UINT32 ControlEnable:1;
 217     UINT32 BulkEnable:1;
 218     UINT32 FunctionalState:2;
 219     UINT32 InterruptRouting:1;
 220     UINT32 RemoteWakeup:1;
 221     UINT32 RemoteWakeupEnable:1;
 222     UINT32 Reserved:21;
 223 } HcCONTROL;
 224
 225 typedef struct {
 226     UINT32 HcReset:1;
 227     UINT32 ControlListFilled:1;
 228     UINT32 BulkListFilled:1;
 229     UINT32 ChangeOwnerRequest:1;
 230     UINT32 Reserved1:12;
 231     UINT32 ScheduleOverrunCount:2;
 232     UINT32 Reserved:14;
 233 } HcCOMMAND_STATUS;
 234
 235 typedef struct {
 236     UINT32 SchedulingOverrun:1;
 237     UINT32 WriteBackDone:1;
 238     UINT32 Sof:1;
 239     UINT32 ResumeDetected:1;
 240     UINT32 UnrecoverableError:1;
 241     UINT32 FrameNumOverflow:1;
 242     UINT32 RHStatusChange:1;
 243     UINT32 Reserved1:23;
 244     UINT32 OwnerChange:1;
 245     UINT32 Reserved2:1;
 246 } HcINTERRUPT_STATUS;
 247
 248 typedef struct {
 249     UINT32 SchedulingOverrunInt:1;
 250     UINT32 WriteBackDoneInt:1;
 251     UINT32 SofInt:1;
 252     UINT32 ResumeDetectedInt:1;
 253     UINT32 UnrecoverableErrorInt:1;
 254     UINT32 FrameNumOverflowInt:1;
 255     UINT32 RHStatusChangeInt:1;
 256     UINT32 Reserved:23;
 257     UINT32 OwnerChangedInt:1;
 258     UINT32 MasterInterruptEnable:1;
 259 } HcINTERRUPT_CONTROL;
 260
 261 typedef struct {
 262     UINT32 Rerserved:8;
 263     UINT32 Hcca:24;
 264 } HcHCCA;
 265
 266 typedef struct {
 267     UINT32 Reserved:4;
 268     UINT32 MemoryPtr:28;
 269 } HcMEMORY_PTR;
 270
 271 typedef struct {
 272     UINT32 FrameInterval:14;
 273     UINT32 Reserved:2;
 274     UINT32 FSMaxDataPacket:15;
 275     UINT32 FrmIntervalToggle:1;
 276 } HcFRM_INTERVAL;
 277
 278 typedef struct {
 279     UINT32 FrameRemaining:14;
 280     UINT32 Reserved:17;
 281     UINT32 FrameRemainingToggle:1;
 282 } HcFRAME_REMAINING;
 283
 284 typedef struct {
 285     UINT32 FrameNumber:16;
 286     UINT32 Reserved:16;
 287 } HcFRAME_NUMBER;
 288
 289 typedef struct {
 290     UINT32 PeriodicStart:14;
 291     UINT32 Reserved:18;
 292 } HcPERIODIC_START;
 293
 294 typedef struct {
 295     UINT32 LsThreshold:12;
 296     UINT32 Reserved:20;
 297 } HcLS_THRESHOLD;
 298
 299 typedef struct {
 300     UINT32 NumDownStrmPorts:8;
 301     UINT32 PowerSwitchMode:1;
 302     UINT32 NoPowerSwitch:1;
 303     UINT32 DeviceType:1;
 304     UINT32 OverCurrentProtMode:1;
 305     UINT32 NoOverCurrentProtMode:1;
 306     UINT32 Reserved:11;
 307     UINT32 PowerOnToPowerGoodTime:8;
 308 } HcRH_DESC_A;
 309
 310 typedef struct {
 311     UINT32 DeviceRemovable:16;
 312     UINT32 PortPowerControlMask:16;
 313 } HcRH_DESC_B;
 314
 315 typedef struct {
 316     UINT32 LocalPowerStat:1;
 317     UINT32 OverCurrentIndicator:1;
 318     UINT32 Reserved1:13;
 319     UINT32 DevRemoteWakeupEnable:1;
 320     UINT32 LocalPowerStatChange:1;
 321     UINT32 OverCurrentIndicatorChange:1;
 322     UINT32 Reserved2:13;
 323     UINT32 ClearRemoteWakeupEnable:1;
 324 } HcRH_STATUS;
 325
 326 typedef struct {
 327     UINT32 CurrentConnectStat:1;
 328     UINT32 EnableStat:1;
 329     UINT32 SuspendStat:1;
 330     UINT32 OCIndicator:1;
 331     UINT32 ResetStat:1;
 332     UINT32 Reserved1:3;
 333     UINT32 PowerStat:1;
 334     UINT32 LsDeviceAttached:1;
 335     UINT32 Reserved2:6;
 336     UINT32 ConnectStatChange:1;
 337     UINT32 EnableStatChange:1;
 338     UINT32 SuspendStatChange:1;
 339     UINT32 OCIndicatorChange:1;
 340     UINT32 ResetStatChange:1;
 341     UINT32 Reserved3:11;
 342 } HcRHPORT_STATUS;
 343
 344 typedef struct {
 345     UINT32 FSBIR:1;
 346     UINT32 FHR:1;
 347     UINT32 CGR:1;
 348     UINT32 SSDC:1;
 349     UINT32 UIT:1;
 350     UINT32 SSE:1;
 351     UINT32 PSPL:1;
 352     UINT32 PCPL:1;
 353     UINT32 Reserved0:1;
 354     UINT32 SSEP1:1;
 355     UINT32 SSEP2:1;
 356     UINT32 SSEP3:1;
 357     UINT32 Reserved1:20;
 358 } HcRESET;
 359
 360 #pragma pack()
 361
 362 //
 363 // Func List
 364 //
 365 /**
 366
 367   Get OHCI operational reg value
 368
 369   @param  Ohc                   UHC private data
 370   @param  Offset                Offset of the operational reg
 371
 372   @retval                       Value of the register
 373
 374 **/
 375 UINT32
 376 OhciGetOperationalReg (
 377   IN USB_OHCI_HC_DEV         *Ohc,
 378   IN UINT32                  Offset
 379   );
 380 /**
 381
 382   Set OHCI operational reg value
 383
 384   @param  Ohc                   UHC private data
 385   @param  Offset                 Offset of the operational reg
 386   @param  Value                  Value to set
 387
 388   @retval EFI_SUCCESS            Value set to the reg
 389
 390 **/
 391 EFI_STATUS
 392 OhciSetOperationalReg (
 393   USB_OHCI_HC_DEV         *Ohc,
 394   IN UINT32               Offset,
 395   IN UINT32               *Value
 396   );
 397 /**
 398
 399   Get HcRevision reg value
 400
 401   @param  Ohc                   UHC private data
 402
 403   @retval                       Value of the register
 404
 405 **/
 406
 407
 408 UINT32
 409 OhciGetHcRevision (
 410   USB_OHCI_HC_DEV         *Ohc
 411   );
 412
 413 /**
 414
 415   Set HcReset reg value
 416
 417   @param  Ohc                   UHC private data
 418   @param  Field                 Field to set
 419   @param  Value                 Value to set
 420
 421   @retval EFI_SUCCESS           Value set
 422
 423 **/
 424
 425 EFI_STATUS
 426 OhciSetHcReset (
 427   IN USB_OHCI_HC_DEV            *Ohc,
 428   IN UINT32                     Field,
 429   IN UINT32                     Value
 430   );
 431 /**
 432
 433   Get specific field of HcReset reg value
 434
 435   @param  Ohc                   UHC private data
 436   @param  Field                 Field to get
 437
 438   @retval                       Value of the field
 439
 440 **/
 441
 442 UINT32
 443 OhciGetHcReset (
 444   IN USB_OHCI_HC_DEV      *Ohc,
 445   IN UINT32               Field
 446   );
 447 /**
 448
 449   Set HcControl reg value
 450
 451   @param  Ohc                   UHC private data
 452   @param  Field                 Field to set
 453   @param  Value                 Value to set
 454
 455   @retval  EFI_SUCCESS          Value set
 456
 457 **/
 458
 459 EFI_STATUS
 460 OhciSetHcControl (
 461   IN USB_OHCI_HC_DEV      *Ohc,
 462   IN UINTN                Field,
 463   IN UINT32               Value
 464   );
 465 /**
 466
 467   Get specific field of HcControl reg value
 468
 469   @param  Ohc                   UHC private data
 470   @param  Field                 Field to get
 471
 472   @retval                       Value of the field
 473
 474 **/
 475
 476
 477 UINT32
 478 OhciGetHcControl (
 479   IN USB_OHCI_HC_DEV   *Ohc,
 480   IN UINTN             Field
 481   );
 482 /**
 483
 484   Set HcCommand reg value
 485
 486   @param  Ohc                   UHC private data
 487   @param  Field                 Field to set
 488   @param  Value                 Value to set
 489
 490   @retval EFI_SUCCESS           Value set
 491
 492 **/
 493
 494 EFI_STATUS
 495 OhciSetHcCommandStatus (
 496   IN USB_OHCI_HC_DEV      *Ohc,
 497   IN UINTN                Field,
 498   IN UINT32               Value
 499   );
 500 /**
 501
 502   Get specific field of HcCommand reg value
 503
 504   @param  Ohc                   UHC private data
 505   @param  Field                 Field to get
 506
 507   @retval                       Value of the field
 508
 509 **/
 510
 511 UINT32
 512 OhciGetHcCommandStatus (
 513   IN USB_OHCI_HC_DEV      *Ohc,
 514   IN UINTN                Field
 515   );
 516 /**
 517
 518   Clear specific fields of Interrupt Status
 519
 520   @param  Ohc                   UHC private data
 521   @param  Field                 Field to clear
 522
 523   @retval EFI_SUCCESS           Fields cleared
 524
 525 **/
 526
 527 EFI_STATUS
 528 OhciClearInterruptStatus (
 529   IN USB_OHCI_HC_DEV      *Ohc,
 530   IN UINTN                Field
 531   );
 532 /**
 533
 534   Get fields of HcInterrupt reg value
 535
 536   @param  Ohc                   UHC private data
 537   @param  Field                 Field to get
 538
 539   @retval                       Value of the field
 540
 541 **/
 542
 543 UINT32
 544 OhciGetHcInterruptStatus (
 545   IN USB_OHCI_HC_DEV      *Ohc,
 546   IN UINTN                Field
 547   );
 548 /**
 549
 550   Set Interrupt Control reg value
 551
 552   @param  Ohc                   UHC private data
 553   @param  StatEnable            Enable or Disable
 554   @param  Field                 Field to set
 555   @param  Value                 Value to set
 556
 557   @retval EFI_SUCCESS           Value set
 558
 559 **/
 560
 561 EFI_STATUS
 562 OhciSetInterruptControl (
 563   IN USB_OHCI_HC_DEV      *Ohc,
 564   IN BOOLEAN              StatEnable,
 565   IN UINTN                Field,
 566   IN UINT32               Value
 567   );
 568 /**
 569
 570   Get field of HcInterruptControl reg value
 571
 572   @param  Ohc                   UHC private data
 573   @param  Field                 Field to get
 574
 575   @retval                       Value of the field
 576
 577 **/
 578
 579 UINT32
 580 OhciGetHcInterruptControl (
 581   IN USB_OHCI_HC_DEV      *Ohc,
 582   IN UINTN                Field
 583   );
 584 /**
 585
 586   Set memory pointer of specific type
 587
 588   @param  Ohc                   UHC private data
 589   @param  PointerType           Type of the pointer to set
 590   @param  Value                 Value to set
 591
 592   @retval EFI_SUCCESS           Memory pointer set
 593
 594 **/
 595
 596 EFI_STATUS
 597 OhciSetMemoryPointer(
 598   IN USB_OHCI_HC_DEV      *Ohc,
 599   IN UINTN                PointerType,
 600   IN VOID                 *Value
 601   );
 602 /**
 603
 604   Get memory pointer of specific type
 605
 606   @param  Ohc                   UHC private data
 607   @param  PointerType           Type of pointer
 608
 609   @retval                       Memory pointer of the specific type
 610
 611 **/
 612
 613 VOID *
 614 OhciGetMemoryPointer (
 615   IN USB_OHCI_HC_DEV      *Ohc,
 616   IN UINTN                PointerType
 617   );
 618 /**
 619
 620   Set Frame Interval value
 621
 622   @param  Ohc                   UHC private data
 623   @param  Field                 Field to set
 624   @param  Value                 Value to set
 625
 626   @retval  EFI_SUCCESS          Value set
 627
 628 **/
 629
 630 EFI_STATUS
 631 OhciSetFrameInterval (
 632   IN USB_OHCI_HC_DEV      *Ohc,
 633   IN UINTN                Field,
 634   IN UINT32               Value
 635   );
 636 /**
 637
 638   Get field of frame interval reg value
 639
 640   @param  Ohc                   UHC private data
 641   @param  Field                 Field to get
 642
 643   @retval                       Value of the field
 644
 645 **/
 646
 647 UINT32
 648 OhciGetFrameInterval (
 649   IN USB_OHCI_HC_DEV      *Ohc,
 650   IN UINTN                Field
 651   );
 652 /**
 653
 654   Set Frame Remaining reg value
 655
 656   @param  Ohc                   UHC private data
 657   @param  Value                 Value to set
 658
 659   @retval  EFI_SUCCESS          Value set
 660
 661 **/
 662
 663 EFI_STATUS
 664 OhciSetFrameRemaining (
 665   IN USB_OHCI_HC_DEV      *Ohc,
 666   IN UINT32               Value
 667   );
 668 /**
 669
 670   Get value of frame remaining reg
 671
 672   @param  Ohc                   UHC private data
 673   @param  Field                 Field to get
 674
 675   @retval                       Value of frame remaining reg
 676
 677 **/
 678 UINT32
 679 OhciGetFrameRemaining (
 680   IN USB_OHCI_HC_DEV      *Ohc,
 681   IN UINTN                Field
 682   );
 683 /**
 684
 685   Set frame number reg value
 686
 687   @param  Ohc                   UHC private data
 688   @param  Value                 Value to set
 689
 690   @retval  EFI_SUCCESS          Value set
 691
 692 **/
 693
 694 EFI_STATUS
 695 OhciSetFrameNumber(
 696   IN USB_OHCI_HC_DEV      *Ohc,
 697   IN UINT32               Value
 698   );
 699 /**
 700
 701   Get frame number reg value
 702
 703   @param  Ohc                   UHC private data
 704
 705   @retval                       Value of frame number reg
 706
 707 **/
 708
 709 UINT32
 710 OhciGetFrameNumber (
 711   IN USB_OHCI_HC_DEV      *Ohc
 712   );
 713 /**
 714
 715   Set period start reg value
 716
 717   @param  Ohc                   UHC private data
 718   @param  Value                 Value to set
 719
 720   @retval EFI_SUCCESS           Value set
 721
 722 **/
 723
 724 EFI_STATUS
 725 OhciSetPeriodicStart (
 726   IN USB_OHCI_HC_DEV      *Ohc,
 727   IN UINT32               Value
 728   );
 729 /**
 730
 731   Get periodic start reg value
 732
 733   @param  Ohc                   UHC private data
 734
 735   @param                        Value of periodic start reg
 736
 737 **/
 738
 739 UINT32
 740 OhciGetPeriodicStart (
 741   IN USB_OHCI_HC_DEV      *Ohc
 742   );
 743 /**
 744
 745   Set Ls Threshold reg value
 746
 747   @param  Ohc                   UHC private data
 748   @param  Value                 Value to set
 749
 750   @retval  EFI_SUCCESS          Value set
 751
 752 **/
 753
 754 EFI_STATUS
 755 OhciSetLsThreshold (
 756   IN USB_OHCI_HC_DEV      *Ohc,
 757   IN UINT32               Value
 758   );
 759 /**
 760
 761   Get Ls Threshold reg value
 762
 763   @param  Ohc                   UHC private data
 764
 765   @retval                       Value of Ls Threshold reg
 766
 767 **/
 768
 769 UINT32
 770 OhciGetLsThreshold (
 771   IN USB_OHCI_HC_DEV      *Ohc
 772   );
 773 /**
 774
 775   Set Root Hub Descriptor reg value
 776
 777   @param  Ohc                   UHC private data
 778   @param  Field                 Field to set
 779   @param  Value                 Value to set
 780
 781   @retval  EFI_SUCCESS          Value set
 782
 783 **/
 784 EFI_STATUS
 785 OhciSetRootHubDescriptor (
 786   IN USB_OHCI_HC_DEV      *Ohc,
 787   IN UINTN                Field,
 788   IN UINT32               Value
 789   );
 790 /**
 791
 792   Get Root Hub Descriptor reg value
 793
 794   @param  Ohc                   UHC private data
 795   @param  Field                 Field to get
 796
 797   @retval                       Value of the field
 798
 799 **/
 800
 801 UINT32
 802 OhciGetRootHubDescriptor (
 803   IN USB_OHCI_HC_DEV     *Ohc,
 804   IN UINTN               Field
 805   );
 806 /**
 807
 808   Set Root Hub Status reg value
 809
 810   @param  Ohc                   UHC private data
 811   @param  Field                 Field to set
 812
 813   @retval  EFI_SUCCESS          Value set
 814
 815 **/
 816
 817 EFI_STATUS
 818 OhciSetRootHubStatus (
 819   IN USB_OHCI_HC_DEV      *Ohc,
 820   IN UINTN                Field
 821   );
 822 /**
 823
 824   Get Root Hub Status reg value
 825
 826   @param  Ohc                   UHC private data
 827   @param  Field                 Field to get
 828
 829   @retval                       Value of the field
 830
 831 **/
 832
 833 UINT32
 834 OhciGetRootHubStatus (
 835   IN USB_OHCI_HC_DEV      *Ohc,
 836   IN UINTN                Field
 837   );
 838 /**
 839
 840   Set Root Hub Port Status reg value
 841
 842   @param  Ohc                   UHC private data
 843   @param  Index                 Index of the port
 844   @param  Field                 Field to set
 845
 846   @retval  EFI_SUCCESS          Value set
 847
 848 **/
 849
 850 EFI_STATUS
 851 OhciSetRootHubPortStatus (
 852   IN USB_OHCI_HC_DEV      *Ohc,
 853   IN UINT32               Index,
 854   IN UINTN                Field
 855   );
 856 /**
 857
 858   Get Root Hub Port Status reg value
 859
 860   @param  Ohc                   UHC private data
 861   @param  Index                 Index of the port
 862   @param  Field                 Field to get
 863
 864   @retval                       Value of the field and index
 865
 866 **/
 867
 868 UINT32
 869 OhciReadRootHubPortStatus (
 870   IN USB_OHCI_HC_DEV      *Ohc,
 871   IN UINT32               Index,
 872   IN UINTN                Field
 873   );
 874
 875 #endif