2 This library is only intended to be used by TPM modules.
3 It provides basic TPM Interface Specification (TIS) and Command functions.
5 Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _TPM_COMM_LIB_H_
17 #define _TPM_COMM_LIB_H_
19 #include <IndustryStandard/Tpm12.h>
21 typedef EFI_HANDLE TIS_TPM_HANDLE
;
24 /// TPM register base address.
26 #define TPM_BASE_ADDRESS 0xfed40000
29 // Set structure alignment to 1-byte
34 // Register set map as specified in TIS specification Chapter 10
38 /// Used to gain ownership for this particular port.
41 UINT8 Reserved1
[7]; // 1
43 /// Controls interrupts.
45 UINT32 IntEnable
; // 8
47 /// SIRQ vector to be used by the TPM.
49 UINT8 IntVector
; // 0ch
50 UINT8 Reserved2
[3]; // 0dh
52 /// What caused interrupt.
56 /// Shows which interrupts are supported by that particular TPM.
58 UINT32 IntfCapability
; // 14h
60 /// Status Register. Provides status of the TPM.
64 /// Number of consecutive writes that can be done to the TPM.
66 UINT16 BurstCount
; // 19h
69 /// Read or write FIFO, depending on transaction.
71 UINT32 DataFifo
; // 24
72 UINT8 Reserved4
[0xed8]; // 28h
86 /// TCG defined configuration registers.
88 UINT8 TcgDefined
[0x7b]; // 0f05h
90 /// Alias to I/O legacy space.
92 UINT32 LegacyAddress1
; // 0f80h
94 /// Additional 8 bits for I/O legacy space extension.
96 UINT32 LegacyAddress1Ex
; // 0f84h
98 /// Alias to second I/O legacy space.
100 UINT32 LegacyAddress2
; // 0f88h
102 /// Additional 8 bits for second I/O legacy space extension.
104 UINT32 LegacyAddress2Ex
; // 0f8ch
106 /// Vendor-defined configuration registers.
108 UINT8 VendorDefined
[0x70];// 0f90h
112 // Restore original structure alignment
117 // Define pointer types used to access TIS registers on PC
119 typedef TIS_PC_REGISTERS
*TIS_PC_REGISTERS_PTR
;
122 // TCG Platform Type based on TCG ACPI Specification Version 1.00
124 #define TCG_PLATFORM_TYPE_CLIENT 0
125 #define TCG_PLATFORM_TYPE_SERVER 1
128 // Define bits of ACCESS and STATUS registers
132 /// This bit is a 1 to indicate that the other bits in this register are valid.
134 #define TIS_PC_VALID BIT7
136 /// Indicate that this locality is active.
138 #define TIS_PC_ACC_ACTIVE BIT5
140 /// Set to 1 to indicate that this locality had the TPM taken away while
141 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
143 #define TIS_PC_ACC_SEIZED BIT4
145 /// Set to 1 to indicate that TPM MUST reset the
146 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
147 /// locality that is writing this bit.
149 #define TIS_PC_ACC_SEIZE BIT3
151 /// When this bit is 1, another locality is requesting usage of the TPM.
153 #define TIS_PC_ACC_PENDIND BIT2
155 /// Set to 1 to indicate that this locality is requesting to use TPM.
157 #define TIS_PC_ACC_RQUUSE BIT1
159 /// A value of 1 indicates that a T/OS has not been established on the platform
161 #define TIS_PC_ACC_ESTABLISH BIT0
164 /// When this bit is 1, TPM is in the Ready state,
165 /// indicating it is ready to receive a new command.
167 #define TIS_PC_STS_READY BIT6
169 /// Write a 1 to this bit to cause the TPM to execute that command.
171 #define TIS_PC_STS_GO BIT5
173 /// This bit indicates that the TPM has data available as a response.
175 #define TIS_PC_STS_DATA BIT4
177 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
179 #define TIS_PC_STS_EXPECT BIT3
181 /// Writes a 1 to this bit to force the TPM to re-send the response.
183 #define TIS_PC_STS_RETRY BIT1
186 // Default TimeOut value
188 #define TIS_TIMEOUT_A 750 * 1000 // 750ms
189 #define TIS_TIMEOUT_B 2000 * 1000 // 2s
190 #define TIS_TIMEOUT_C 750 * 1000 // 750ms
191 #define TIS_TIMEOUT_D 750 * 1000 // 750ms
194 // Max TPM command/reponse length
196 #define TPMCMDBUFLENGTH 1024
199 Check whether the value of a TPM chip register satisfies the input BIT setting.
201 @param[in] Register Address port of register to be checked.
202 @param[in] BitSet Check these data bits are set.
203 @param[in] BitClear Check these data bits are clear.
204 @param[in] TimeOut The max wait time (unit MicroSecond) when checking register.
206 @retval EFI_SUCCESS The register satisfies the check bit.
207 @retval EFI_TIMEOUT The register can't run into the expected status in time.
211 TisPcWaitRegisterBits (
219 Get BurstCount by reading the burstCount field of a TIS regiger
220 in the time of default TIS_TIMEOUT_D.
222 @param[in] TisReg Pointer to TIS register.
223 @param[out] BurstCount Pointer to a buffer to store the got BurstConut.
225 @retval EFI_SUCCESS Get BurstCount.
226 @retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.
227 @retval EFI_TIMEOUT BurstCount can't be got in time.
231 TisPcReadBurstCount (
232 IN TIS_PC_REGISTERS_PTR TisReg
,
233 OUT UINT16
*BurstCount
237 Set TPM chip to ready state by sending ready command TIS_PC_STS_READY
238 to Status Register in time.
240 @param[in] TisReg Pointer to TIS register.
242 @retval EFI_SUCCESS TPM chip enters into ready state.
243 @retval EFI_INVALID_PARAMETER TisReg is NULL.
244 @retval EFI_TIMEOUT TPM chip can't be set to ready state in time.
248 TisPcPrepareCommand (
249 IN TIS_PC_REGISTERS_PTR TisReg
253 Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
254 to ACCESS Register in the time of default TIS_TIMEOUT_D.
256 @param[in] TisReg Pointer to TIS register.
258 @retval EFI_SUCCESS Get the control of TPM chip.
259 @retval EFI_INVALID_PARAMETER TisReg is NULL.
260 @retval EFI_NOT_FOUND TPM chip doesn't exit.
261 @retval EFI_TIMEOUT Can't get the TPM control in time.
266 IN TIS_PC_REGISTERS_PTR TisReg
270 Single function calculates SHA1 digest value for all raw data. It
271 combines Sha1Init(), Sha1Update() and Sha1Final().
273 @param[in] Data Raw data to be digested.
274 @param[in] DataLen Size of the raw data.
275 @param[out] Digest Pointer to a buffer that stores the final digest.
277 @retval EFI_SUCCESS Always successfully calculate the final digest.
282 IN CONST UINT8
*Data
,
284 OUT TPM_DIGEST
*Digest