SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c

   1 /** @file
   2   PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by dTPM2.0 library.
   3
   4 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
   5 Copyright (c), Microsoft Corporation.
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include <IndustryStandard/Tpm20.h>
  11
  12 #include <Library/BaseLib.h>
  13 #include <Library/BaseMemoryLib.h>
  14 #include <Library/IoLib.h>
  15 #include <Library/TimerLib.h>
  16 #include <Library/DebugLib.h>
  17 #include <Library/Tpm2DeviceLib.h>
  18 #include <Library/PcdLib.h>
  19
  20 #include <IndustryStandard/TpmPtp.h>
  21 #include <IndustryStandard/TpmTis.h>
  22
  23 #include "Tpm2DeviceLibDTpm.h"
  24
  25 //
  26 // Execution of the command may take from several seconds to minutes for certain
  27 // commands, such as key generation.
  28 //
  29 #define PTP_TIMEOUT_MAX             (90000 * 1000)  // 90s
  30
  31 //
  32 // Max TPM command/response length
  33 //
  34 #define TPMCMDBUFLENGTH             0x500
  35
  36 /**
  37   Check whether TPM PTP register exist.
  38
  39   @param[in] Reg  Pointer to PTP register.
  40
  41   @retval    TRUE    TPM PTP exists.
  42   @retval    FALSE   TPM PTP is not found.
  43 **/
  44 BOOLEAN
  45 Tpm2IsPtpPresence (
  46   IN VOID *Reg
  47   )
  48 {
  49   UINT8                             RegRead;
  50
  51   RegRead = MmioRead8 ((UINTN)Reg);
  52   if (RegRead == 0xFF) {
  53     //
  54     // No TPM chip
  55     //
  56     return FALSE;
  57   }
  58   return TRUE;
  59 }
  60
  61 /**
  62   Check whether the value of a TPM chip register satisfies the input BIT setting.
  63
  64   @param[in]  Register     Address port of register to be checked.
  65   @param[in]  BitSet       Check these data bits are set.
  66   @param[in]  BitClear     Check these data bits are clear.
  67   @param[in]  TimeOut      The max wait time (unit MicroSecond) when checking register.
  68
  69   @retval     EFI_SUCCESS  The register satisfies the check bit.
  70   @retval     EFI_TIMEOUT  The register can't run into the expected status in time.
  71 **/
  72 EFI_STATUS
  73 PtpCrbWaitRegisterBits (
  74   IN      UINT32                    *Register,
  75   IN      UINT32                    BitSet,
  76   IN      UINT32                    BitClear,
  77   IN      UINT32                    TimeOut
  78   )
  79 {
  80   UINT32                            RegRead;
  81   UINT32                            WaitTime;
  82
  83   for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){
  84     RegRead = MmioRead32 ((UINTN)Register);
  85     if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {
  86       return EFI_SUCCESS;
  87     }
  88     MicroSecondDelay (30);
  89   }
  90   return EFI_TIMEOUT;
  91 }
  92
  93 /**
  94   Get the control of TPM chip.
  95
  96   @param[in] CrbReg                Pointer to CRB register.
  97
  98   @retval    EFI_SUCCESS           Get the control of TPM chip.
  99   @retval    EFI_INVALID_PARAMETER CrbReg is NULL.
 100   @retval    EFI_NOT_FOUND         TPM chip doesn't exit.
 101   @retval    EFI_TIMEOUT           Can't get the TPM control in time.
 102 **/
 103 EFI_STATUS
 104 PtpCrbRequestUseTpm (
 105   IN      PTP_CRB_REGISTERS_PTR      CrbReg
 106   )
 107 {
 108   EFI_STATUS                        Status;
 109
 110   if (!Tpm2IsPtpPresence (CrbReg)) {
 111     return EFI_NOT_FOUND;
 112   }
 113
 114   MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);
 115   Status = PtpCrbWaitRegisterBits (
 116              &CrbReg->LocalityStatus,
 117              PTP_CRB_LOCALITY_STATUS_GRANTED,
 118              0,
 119              PTP_TIMEOUT_A
 120              );
 121   return Status;
 122 }
 123
 124 /**
 125   Send a command to TPM for execution and return response data.
 126
 127   @param[in]      CrbReg        TPM register space base address.
 128   @param[in]      BufferIn      Buffer for command data.
 129   @param[in]      SizeIn        Size of command data.
 130   @param[in, out] BufferOut     Buffer for response data.
 131   @param[in, out] SizeOut       Size of response data.
 132
 133   @retval EFI_SUCCESS           Operation completed successfully.
 134   @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.
 135   @retval EFI_DEVICE_ERROR      Unexpected device behavior.
 136   @retval EFI_UNSUPPORTED       Unsupported TPM version
 137
 138 **/
 139 EFI_STATUS
 140 PtpCrbTpmCommand (
 141   IN     PTP_CRB_REGISTERS_PTR      CrbReg,
 142   IN     UINT8                      *BufferIn,
 143   IN     UINT32                     SizeIn,
 144   IN OUT UINT8                      *BufferOut,
 145   IN OUT UINT32                     *SizeOut
 146   )
 147 {
 148   EFI_STATUS                        Status;
 149   UINT32                            Index;
 150   UINT32                            TpmOutSize;
 151   UINT16                            Data16;
 152   UINT32                            Data32;
 153
 154   DEBUG_CODE_BEGIN ();
 155     UINTN  DebugSize;
 156
 157     DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Send - "));
 158     if (SizeIn > 0x100) {
 159       DebugSize = 0x40;
 160     } else {
 161       DebugSize = SizeIn;
 162     }
 163     for (Index = 0; Index < DebugSize; Index++) {
 164       DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
 165     }
 166     if (DebugSize != SizeIn) {
 167       DEBUG ((DEBUG_VERBOSE, "...... "));
 168       for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {
 169         DEBUG ((DEBUG_VERBOSE, "%02x ", BufferIn[Index]));
 170       }
 171     }
 172     DEBUG ((DEBUG_VERBOSE, "\n"));
 173   DEBUG_CODE_END ();
 174   TpmOutSize         = 0;
 175
 176   //
 177   // STEP 0:
 178   // if CapCRbIdelByPass == 0, enforce Idle state before sending command
 179   //
 180   if (GetCachedIdleByPass () == 0 && (MmioRead32((UINTN)&CrbReg->CrbControlStatus) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0){
 181     Status = PtpCrbWaitRegisterBits (
 182               &CrbReg->CrbControlStatus,
 183               PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 184               0,
 185               PTP_TIMEOUT_C
 186               );
 187     if (EFI_ERROR (Status)) {
 188       //
 189       // Try to goIdle to recover TPM
 190       //
 191       Status = EFI_DEVICE_ERROR;
 192       goto GoIdle_Exit;
 193     }
 194   }
 195
 196   //
 197   // STEP 1:
 198   // Ready is any time the TPM is ready to receive a command, following a write
 199   // of 1 by software to Request.cmdReady, as indicated by the Status field
 200   // being cleared to 0.
 201   //
 202   MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
 203   Status = PtpCrbWaitRegisterBits (
 204              &CrbReg->CrbControlRequest,
 205              0,
 206              PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY,
 207              PTP_TIMEOUT_C
 208              );
 209   if (EFI_ERROR (Status)) {
 210     Status = EFI_DEVICE_ERROR;
 211     goto GoIdle_Exit;
 212   }
 213   Status = PtpCrbWaitRegisterBits (
 214              &CrbReg->CrbControlStatus,
 215              0,
 216              PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 217              PTP_TIMEOUT_C
 218              );
 219   if (EFI_ERROR (Status)) {
 220     Status = EFI_DEVICE_ERROR;
 221     goto GoIdle_Exit;
 222   }
 223
 224   //
 225   // STEP 2:
 226   // Command Reception occurs following a Ready state between the write of the
 227   // first byte of a command to the Command Buffer and the receipt of a write
 228   // of 1 to Start.
 229   //
 230   for (Index = 0; Index < SizeIn; Index++) {
 231     MmioWrite8 ((UINTN)&CrbReg->CrbDataBuffer[Index], BufferIn[Index]);
 232   }
 233   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressHigh, (UINT32)RShiftU64 ((UINTN)CrbReg->CrbDataBuffer, 32));
 234   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandAddressLow, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
 235   MmioWrite32 ((UINTN)&CrbReg->CrbControlCommandSize, sizeof(CrbReg->CrbDataBuffer));
 236
 237   MmioWrite64 ((UINTN)&CrbReg->CrbControlResponseAddrss, (UINT32)(UINTN)CrbReg->CrbDataBuffer);
 238   MmioWrite32 ((UINTN)&CrbReg->CrbControlResponseSize, sizeof(CrbReg->CrbDataBuffer));
 239
 240   //
 241   // STEP 3:
 242   // Command Execution occurs after receipt of a 1 to Start and the TPM
 243   // clearing Start to 0.
 244   //
 245   MmioWrite32((UINTN)&CrbReg->CrbControlStart, PTP_CRB_CONTROL_START);
 246   Status = PtpCrbWaitRegisterBits (
 247              &CrbReg->CrbControlStart,
 248              0,
 249              PTP_CRB_CONTROL_START,
 250              PTP_TIMEOUT_MAX
 251              );
 252   if (EFI_ERROR (Status)) {
 253     //
 254     // Command Completion check timeout. Cancel the currently executing command by writing TPM_CRB_CTRL_CANCEL,
 255     // Expect TPM_RC_CANCELLED or successfully completed response.
 256     //
 257     MmioWrite32((UINTN)&CrbReg->CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
 258     Status = PtpCrbWaitRegisterBits (
 259                &CrbReg->CrbControlStart,
 260                0,
 261                PTP_CRB_CONTROL_START,
 262                PTP_TIMEOUT_B
 263                );
 264     MmioWrite32((UINTN)&CrbReg->CrbControlCancel, 0);
 265
 266     if (EFI_ERROR(Status)) {
 267       //
 268       // Still in Command Execution state. Try to goIdle, the behavior is agnostic.
 269       //
 270       Status = EFI_DEVICE_ERROR;
 271       goto GoIdle_Exit;
 272     }
 273   }
 274
 275   //
 276   // STEP 4:
 277   // Command Completion occurs after completion of a command (indicated by the
 278   // TPM clearing TPM_CRB_CTRL_Start_x to 0) and before a write of a 1 by the
 279   // software to Request.goIdle.
 280   //
 281
 282   //
 283   // Get response data header
 284   //
 285   for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
 286     BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
 287   }
 288   DEBUG_CODE_BEGIN ();
 289     DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand ReceiveHeader - "));
 290     for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {
 291       DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
 292     }
 293     DEBUG ((DEBUG_VERBOSE, "\n"));
 294   DEBUG_CODE_END ();
 295   //
 296   // Check the response data header (tag, parasize and returncode)
 297   //
 298   CopyMem (&Data16, BufferOut, sizeof (UINT16));
 299   // TPM2 should not use this RSP_COMMAND
 300   if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {
 301     DEBUG ((DEBUG_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));
 302     Status = EFI_UNSUPPORTED;
 303     goto GoIdle_Exit;
 304   }
 305
 306   CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));
 307   TpmOutSize  = SwapBytes32 (Data32);
 308   if (*SizeOut < TpmOutSize) {
 309     //
 310     // Command completed, but buffer is not enough
 311     //
 312     Status = EFI_BUFFER_TOO_SMALL;
 313     goto GoReady_Exit;
 314   }
 315   *SizeOut = TpmOutSize;
 316   //
 317   // Continue reading the remaining data
 318   //
 319   for (Index = sizeof (TPM2_RESPONSE_HEADER); Index < TpmOutSize; Index++) {
 320     BufferOut[Index] = MmioRead8 ((UINTN)&CrbReg->CrbDataBuffer[Index]);
 321   }
 322
 323   DEBUG_CODE_BEGIN ();
 324     DEBUG ((DEBUG_VERBOSE, "PtpCrbTpmCommand Receive - "));
 325     for (Index = 0; Index < TpmOutSize; Index++) {
 326       DEBUG ((DEBUG_VERBOSE, "%02x ", BufferOut[Index]));
 327     }
 328     DEBUG ((DEBUG_VERBOSE, "\n"));
 329   DEBUG_CODE_END ();
 330
 331 GoReady_Exit:
 332   //
 333   // Goto Ready State if command is completed successfully and TPM support IdleBypass
 334   // If not supported. flow down to GoIdle
 335   //
 336   if (GetCachedIdleByPass () == 1) {
 337     MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY);
 338     return Status;
 339   }
 340
 341   //
 342   // Do not wait for state transition for TIMEOUT_C
 343   // This function will try to wait 2 TIMEOUT_C at the beginning in next call.
 344   //
 345 GoIdle_Exit:
 346
 347   //
 348   //  Return to Idle state by setting TPM_CRB_CTRL_STS_x.Status.goIdle to 1.
 349   //
 350   MmioWrite32((UINTN)&CrbReg->CrbControlRequest, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
 351
 352   //
 353   // Only enforce Idle state transition if execution fails when CRBIdleBypass==1
 354   // Leave regular Idle delay at the beginning of next command execution
 355   //
 356   if (GetCachedIdleByPass () == 1){
 357     Status = PtpCrbWaitRegisterBits (
 358                &CrbReg->CrbControlStatus,
 359                PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE,
 360                0,
 361                PTP_TIMEOUT_C
 362                );
 363   }
 364
 365   return Status;
 366 }
 367
 368 /**
 369   Send a command to TPM for execution and return response data.
 370
 371   @param[in]      TisReg        TPM register space base address.
 372   @param[in]      BufferIn      Buffer for command data.
 373   @param[in]      SizeIn        Size of command data.
 374   @param[in, out] BufferOut     Buffer for response data.
 375   @param[in, out] SizeOut       Size of response data.
 376
 377   @retval EFI_SUCCESS           Operation completed successfully.
 378   @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.
 379   @retval EFI_DEVICE_ERROR      Unexpected device behavior.
 380   @retval EFI_UNSUPPORTED       Unsupported TPM version
 381
 382 **/
 383 EFI_STATUS
 384 Tpm2TisTpmCommand (
 385   IN     TIS_PC_REGISTERS_PTR       TisReg,
 386   IN     UINT8                      *BufferIn,
 387   IN     UINT32                     SizeIn,
 388   IN OUT UINT8                      *BufferOut,
 389   IN OUT UINT32                     *SizeOut
 390   );
 391
 392 /**
 393   Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE
 394   to ACCESS Register in the time of default TIS_TIMEOUT_A.
 395
 396   @param[in] TisReg                Pointer to TIS register.
 397
 398   @retval    EFI_SUCCESS           Get the control of TPM chip.
 399   @retval    EFI_INVALID_PARAMETER TisReg is NULL.
 400   @retval    EFI_NOT_FOUND         TPM chip doesn't exit.
 401   @retval    EFI_TIMEOUT           Can't get the TPM control in time.
 402 **/
 403 EFI_STATUS
 404 TisPcRequestUseTpm (
 405   IN     TIS_PC_REGISTERS_PTR       TisReg
 406   );
 407
 408 /**
 409   Return PTP interface type.
 410
 411   @param[in] Register                Pointer to PTP register.
 412
 413   @return PTP interface type.
 414 **/
 415 TPM2_PTP_INTERFACE_TYPE
 416 Tpm2GetPtpInterface (
 417   IN VOID *Register
 418   )
 419 {
 420   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 421   PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
 422
 423   if (!Tpm2IsPtpPresence (Register)) {
 424     return Tpm2PtpInterfaceMax;
 425   }
 426   //
 427   // Check interface id
 428   //
 429   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 430   InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
 431
 432   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&
 433       (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&
 434       (InterfaceId.Bits.CapCRB != 0)) {
 435     return Tpm2PtpInterfaceCrb;
 436   }
 437   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&
 438       (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&
 439       (InterfaceId.Bits.CapFIFO != 0) &&
 440       (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {
 441     return Tpm2PtpInterfaceFifo;
 442   }
 443   return Tpm2PtpInterfaceTis;
 444 }
 445
 446 /**
 447   Return PTP CRB interface IdleByPass state.
 448
 449   @param[in] Register                Pointer to PTP register.
 450
 451   @return PTP CRB interface IdleByPass state.
 452 **/
 453 UINT8
 454 Tpm2GetIdleByPass (
 455   IN VOID *Register
 456   )
 457 {
 458   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 459
 460   //
 461   // Check interface id
 462   //
 463   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 464
 465   return (UINT8)(InterfaceId.Bits.CapCRBIdleBypass);
 466 }
 467
 468 /**
 469   Dump PTP register information.
 470
 471   @param[in] Register                Pointer to PTP register.
 472 **/
 473 VOID
 474 DumpPtpInfo (
 475   IN VOID *Register
 476   )
 477 {
 478   PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;
 479   PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;
 480   UINT8                         StatusEx;
 481   UINT16                        Vid;
 482   UINT16                        Did;
 483   UINT8                         Rid;
 484   TPM2_PTP_INTERFACE_TYPE       PtpInterface;
 485
 486   if (!Tpm2IsPtpPresence (Register)) {
 487     return ;
 488   }
 489
 490   InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);
 491   InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);
 492   StatusEx = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->StatusEx);
 493
 494   //
 495   // Dump InterfaceId Register for PTP
 496   //
 497   DEBUG ((DEBUG_INFO, "InterfaceId - 0x%08x\n", InterfaceId.Uint32));
 498   DEBUG ((DEBUG_INFO, "  InterfaceType    - 0x%02x\n", InterfaceId.Bits.InterfaceType));
 499   if (InterfaceId.Bits.InterfaceType != PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) {
 500     DEBUG ((DEBUG_INFO, "  InterfaceVersion - 0x%02x\n", InterfaceId.Bits.InterfaceVersion));
 501     DEBUG ((DEBUG_INFO, "  CapFIFO          - 0x%x\n", InterfaceId.Bits.CapFIFO));
 502     DEBUG ((DEBUG_INFO, "  CapCRB           - 0x%x\n", InterfaceId.Bits.CapCRB));
 503   }
 504
 505   //
 506   // Dump Capability Register for TIS and FIFO
 507   //
 508   DEBUG ((DEBUG_INFO, "InterfaceCapability - 0x%08x\n", InterfaceCapability.Uint32));
 509   if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS) ||
 510       (InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO)) {
 511     DEBUG ((DEBUG_INFO, "  InterfaceVersion - 0x%x\n", InterfaceCapability.Bits.InterfaceVersion));
 512   }
 513
 514   //
 515   // Dump StatusEx Register for PTP FIFO
 516   //
 517   DEBUG ((DEBUG_INFO, "StatusEx - 0x%02x\n", StatusEx));
 518   if (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP) {
 519     DEBUG ((DEBUG_INFO, "  TpmFamily - 0x%x\n", (StatusEx & PTP_FIFO_STS_EX_TPM_FAMILY) >> PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET));
 520   }
 521
 522   Vid = 0xFFFF;
 523   Did = 0xFFFF;
 524   Rid = 0xFF;
 525   PtpInterface = GetCachedPtpInterface ();
 526   DEBUG ((DEBUG_INFO, "PtpInterface - %x\n", PtpInterface));
 527   switch (PtpInterface) {
 528   case Tpm2PtpInterfaceCrb:
 529     Vid = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Vid);
 530     Did = MmioRead16 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->Did);
 531     Rid = (UINT8)InterfaceId.Bits.Rid;
 532     break;
 533   case Tpm2PtpInterfaceFifo:
 534   case Tpm2PtpInterfaceTis:
 535     Vid = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Vid);
 536     Did = MmioRead16 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Did);
 537     Rid = MmioRead8 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->Rid);
 538     break;
 539   default:
 540     break;
 541   }
 542   DEBUG ((DEBUG_INFO, "VID - 0x%04x\n", Vid));
 543   DEBUG ((DEBUG_INFO, "DID - 0x%04x\n", Did));
 544   DEBUG ((DEBUG_INFO, "RID - 0x%02x\n", Rid));
 545 }
 546
 547 /**
 548   This service enables the sending of commands to the TPM2.
 549
 550   @param[in]      InputParameterBlockSize  Size of the TPM2 input parameter block.
 551   @param[in]      InputParameterBlock      Pointer to the TPM2 input parameter block.
 552   @param[in,out]  OutputParameterBlockSize Size of the TPM2 output parameter block.
 553   @param[in]      OutputParameterBlock     Pointer to the TPM2 output parameter block.
 554
 555   @retval EFI_SUCCESS            The command byte stream was successfully sent to the device and a response was successfully received.
 556   @retval EFI_DEVICE_ERROR       The command was not successfully sent to the device or a response was not successfully received from the device.
 557   @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small.
 558 **/
 559 EFI_STATUS
 560 EFIAPI
 561 DTpm2SubmitCommand (
 562   IN UINT32            InputParameterBlockSize,
 563   IN UINT8             *InputParameterBlock,
 564   IN OUT UINT32        *OutputParameterBlockSize,
 565   IN UINT8             *OutputParameterBlock
 566   )
 567 {
 568   TPM2_PTP_INTERFACE_TYPE  PtpInterface;
 569
 570   PtpInterface = GetCachedPtpInterface ();
 571   switch (PtpInterface) {
 572   case Tpm2PtpInterfaceCrb:
 573     return PtpCrbTpmCommand (
 574            (PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
 575            InputParameterBlock,
 576            InputParameterBlockSize,
 577            OutputParameterBlock,
 578            OutputParameterBlockSize
 579            );
 580   case Tpm2PtpInterfaceFifo:
 581   case Tpm2PtpInterfaceTis:
 582     return Tpm2TisTpmCommand (
 583            (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),
 584            InputParameterBlock,
 585            InputParameterBlockSize,
 586            OutputParameterBlock,
 587            OutputParameterBlockSize
 588            );
 589   default:
 590     return EFI_NOT_FOUND;
 591   }
 592 }
 593
 594 /**
 595   This service requests use TPM2.
 596
 597   @retval EFI_SUCCESS      Get the control of TPM2 chip.
 598   @retval EFI_NOT_FOUND    TPM2 not found.
 599   @retval EFI_DEVICE_ERROR Unexpected device behavior.
 600 **/
 601 EFI_STATUS
 602 EFIAPI
 603 DTpm2RequestUseTpm (
 604   VOID
 605   )
 606 {
 607   TPM2_PTP_INTERFACE_TYPE  PtpInterface;
 608
 609   PtpInterface = GetCachedPtpInterface ();
 610   switch (PtpInterface) {
 611   case Tpm2PtpInterfaceCrb:
 612     return PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
 613   case Tpm2PtpInterfaceFifo:
 614   case Tpm2PtpInterfaceTis:
 615     return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));
 616   default:
 617     return EFI_NOT_FOUND;
 618   }
 619 }