1 ;------------------------------------------------------------------------------
3 ; Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
4 ; This program and the accompanying materials
5 ; are licensed and made available under the terms and conditions of the BSD License
6 ; which accompanies this distribution. The full text of the license may be found at
7 ; http://opensource.org/licenses/bsd-license.php.
9 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 ; Debug interrupt handle functions.
20 ;------------------------------------------------------------------------------
22 #include "DebugException.h"
25 externdef InterruptProcess:near
29 public Exception0Handle, TimerInterruptHandle, ExceptionStubHeaderSize
31 ExceptionStubHeaderSize dw Exception1Handle - Exception0Handle ;
32 CommonEntryAddr dq CommonEntry ;
40 jmp qword ptr [CommonEntryAddr]
45 jmp qword ptr [CommonEntryAddr]
50 jmp qword ptr [CommonEntryAddr]
55 jmp qword ptr [CommonEntryAddr]
60 jmp qword ptr [CommonEntryAddr]
65 jmp qword ptr [CommonEntryAddr]
70 jmp qword ptr [CommonEntryAddr]
75 jmp qword ptr [CommonEntryAddr]
80 jmp qword ptr [CommonEntryAddr]
85 jmp qword ptr [CommonEntryAddr]
90 jmp qword ptr [CommonEntryAddr]
95 jmp qword ptr [CommonEntryAddr]
100 jmp qword ptr [CommonEntryAddr]
105 jmp qword ptr [CommonEntryAddr]
110 jmp qword ptr [CommonEntryAddr]
115 jmp qword ptr [CommonEntryAddr]
120 jmp qword ptr [CommonEntryAddr]
125 jmp qword ptr [CommonEntryAddr]
130 jmp qword ptr [CommonEntryAddr]
135 jmp qword ptr [CommonEntryAddr]
137 TimerInterruptHandle:
141 jmp qword ptr [CommonEntryAddr]
144 ; We need to determine if any extra data was pushed by the exception
145 cmp rcx, DEBUG_EXCEPT_DOUBLE_FAULT
147 cmp rcx, DEBUG_EXCEPT_INVALID_TSS
149 cmp rcx, DEBUG_EXCEPT_SEG_NOT_PRESENT
151 cmp rcx, DEBUG_EXCEPT_STACK_FAULT
153 cmp rcx, DEBUG_EXCEPT_GP_FAULT
155 cmp rcx, DEBUG_EXCEPT_PAGE_FAULT
157 cmp rcx, DEBUG_EXCEPT_ALIGNMENT_CHECK
161 mov qword ptr [rsp + 8], 0
167 ; store UINT64 r8, r9, r10, r11, r12, r13, r14, r15;
180 ; store UINT64 Rdi, Rsi, Rbp, Rsp, Rdx, Rcx, Rbx, Rax;
183 push qword ptr [rbp + 8] ; original rcx
185 push qword ptr [rbp + 6 * 8] ; original rsp
186 push qword ptr [rbp] ; original rbp
190 ;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
191 ;; insure FXSAVE/FXRSTOR is enabled in CR4...
192 ;; ... while we're at it, make sure DE is also enabled...
201 push 0 ; cr0 will not saved???
220 mov rax, [rbp + 8 * 3] ; EIP
223 ;; UINT64 Gdtr[2], Idtr[2];
237 mov rax, [rbp + 8 * 5]
240 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
244 ;; clear Dr7 while executing debugger itself
252 ;; insure all status bits in dr6 are clear...
267 db 0fh, 0aeh, 00000111y ;fxsave [rdi]
269 ;; save the exception data
270 push qword ptr [rbp + 16]
272 ;; Clear Direction Flag
275 ; call the C interrupt process function
276 mov rdx, rsp ; Structure
277 mov r15, rcx ; save vector in r15
280 ; Per X64 calling convention, allocate maximum parameter stack space
281 ; and make sure RSP is 16-byte aligned
284 call InterruptProcess
287 ;; skip the exception data
291 db 0fh, 0aeh, 00001110y ; fxrstor [rsi]
294 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
303 ;; skip restore of dr6. We cleared dr6 during the context save.
309 pop qword ptr [rbp + 8 * 5]
312 ;; UINT64 Gdtr[2], Idtr[2];
313 ;; Best not let anyone mess with these particular registers...
317 pop qword ptr [rbp + 8 * 3] ; set EIP in stack
319 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
320 ;; NOTE - modified segment registers could hang the debugger... We
321 ;; could attempt to insulate ourselves against this possibility,
322 ;; but that poses risks as well.
330 pop qword ptr [rbp + 8 * 4] ; Set CS in stack
334 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4;
337 add rsp, 8 ; skip for Cr1
345 ;; restore general register
348 add rsp, 8 ; skip rbp
349 add rsp, 8 ; skip rsp
358 ; store UINT64 r8, r9, r10, r11, r12, r13, r14, r15;
370 add rsp, 16 ; skip rcx and error code