2 Debug Port Library implementation based on usb3 debug port.
4 Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__
16 #define __USB3_DEBUG_PORT_LIB_INTERNAL__
20 #include <IndustryStandard/Usb.h>
21 #include <Library/IoLib.h>
22 #include <IndustryStandard/Pci.h>
23 #include <Library/PcdLib.h>
24 #include <Library/UefiLib.h>
25 #include <Library/UefiBootServicesTableLib.h>
26 #include <Library/MemoryAllocationLib.h>
27 #include <Library/DebugLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/BaseLib.h>
30 #include <Library/TimerLib.h>
31 #include <Library/DebugCommunicationLib.h>
32 #include <Library/PciLib.h>
33 #include <Library/SerialPortLib.h> // Todo: remove in future
36 // Internal serial debug - remove finally
38 #include <Library/SerialPortLib.h>
39 #include <Library/PrintLib.h>
42 // USB Debug GUID value
44 #define USB3_DBG_GUID \
46 0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \
50 // The state machine of usb debug port
52 #define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
53 #define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
54 #define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
55 #define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
57 #define USB3_DEBUG_PORT_MAX_PACKET_SIZE 0x08
59 #define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525
60 #define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A
61 #define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF
62 #define XHCI_DEBUG_DEVICE_REVISION 0x00
64 #define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
65 #define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
67 #define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
68 #define XHC_HCCPARAMS_OFFSET 0x10
69 #define XHC_CAPABILITY_ID_MASK 0xFF
70 #define XHC_NEXT_CAPABILITY_MASK 0xFF00
72 #define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
73 #define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
74 #define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
75 #define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
77 #define XHC_USBCMD_RUN BIT0 // Run/Stop
78 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
80 #define XHC_USBSTS_HALT BIT0
83 // Transfer the data of 8 bytes each time
85 #define XHC_DEBUG_PORT_DATA_LENGTH 8
88 // Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.
90 #define DATA_TRANSFER_WRITE_TIMEOUT 0
91 #define DATA_TRANSFER_READ_TIMEOUT 50000
92 #define DATA_TRANSFER_POLL_TIMEOUT 1000
95 // XHCI port power off/on delay
97 #define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
100 // USB debug device string descritpor (header size + unicode string length)
102 #define STRING0_DESC_LEN 4
103 #define MANU_DESC_LEN 12
104 #define PRODUCT_DESC_LEN 40
105 #define SERIAL_DESC_LEN 4
108 // Debug Capability Register Offset
110 #define XHC_DC_DCID 0x0
111 #define XHC_DC_DCDB 0x4
112 #define XHC_DC_DCERSTSZ 0x8
113 #define XHC_DC_DCERSTBA 0x10
114 #define XHC_DC_DCERDP 0x18
115 #define XHC_DC_DCCTRL 0x20
116 #define XHC_DC_DCST 0x24
117 #define XHC_DC_DCPORTSC 0x28
118 #define XHC_DC_DCCP 0x30
119 #define XHC_DC_DCDDI1 0x38
120 #define XHC_DC_DCDDI2 0x3C
122 #define TRB_TYPE_LINK 6
124 #define ERST_NUMBER 0x01
125 #define TR_RING_TRB_NUMBER 0x100
126 #define EVENT_RING_TRB_NUMBER 0x200
128 #define ED_BULK_OUT 2
131 #define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
132 #define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
133 #define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
136 // Endpoint Type (EP Type).
138 #define ED_NOT_VALID 0
139 #define ED_ISOCH_OUT 1
140 #define ED_BULK_OUT 2
141 #define ED_INTERRUPT_OUT 3
142 #define ED_CONTROL_BIDIR 4
143 #define ED_ISOCH_IN 5
145 #define ED_INTERRUPT_IN 7
148 // 6.4.5 TRB Completion Codes
150 #define TRB_COMPLETION_INVALID 0
151 #define TRB_COMPLETION_SUCCESS 1
152 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
153 #define TRB_COMPLETION_BABBLE_ERROR 3
154 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
155 #define TRB_COMPLETION_TRB_ERROR 5
156 #define TRB_COMPLETION_STALL_ERROR 6
157 #define TRB_COMPLETION_SHORT_PACKET 13
162 #define TRB_TYPE_NORMAL 1
163 #define TRB_TYPE_SETUP_STAGE 2
164 #define TRB_TYPE_DATA_STAGE 3
165 #define TRB_TYPE_STATUS_STAGE 4
166 #define TRB_TYPE_ISOCH 5
167 #define TRB_TYPE_LINK 6
168 #define TRB_TYPE_EVENT_DATA 7
169 #define TRB_TYPE_NO_OP 8
170 #define TRB_TYPE_EN_SLOT 9
171 #define TRB_TYPE_DIS_SLOT 10
172 #define TRB_TYPE_ADDRESS_DEV 11
173 #define TRB_TYPE_CON_ENDPOINT 12
174 #define TRB_TYPE_EVALU_CONTXT 13
175 #define TRB_TYPE_RESET_ENDPOINT 14
176 #define TRB_TYPE_STOP_ENDPOINT 15
177 #define TRB_TYPE_SET_TR_DEQUE 16
178 #define TRB_TYPE_RESET_DEV 17
179 #define TRB_TYPE_GET_PORT_BANW 21
180 #define TRB_TYPE_FORCE_HEADER 22
181 #define TRB_TYPE_NO_OP_COMMAND 23
182 #define TRB_TYPE_TRANS_EVENT 32
183 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
184 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
185 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
186 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
187 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
190 // Convert millisecond to microsecond.
192 #define XHC_1_MILLISECOND (1000)
193 #define XHC_POLL_DELAY (1000)
194 #define XHC_GENERIC_TIMEOUT (10 * 1000)
196 #define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
197 #define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
198 #define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
199 #define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
202 // Transfer types, used in URB to identify the transfer type
204 #define XHC_CTRL_TRANSFER 0x01
205 #define XHC_BULK_TRANSFER 0x02
206 #define XHC_INT_TRANSFER_SYNC 0x04
207 #define XHC_INT_TRANSFER_ASYNC 0x08
208 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
211 // USB Transfer Results
213 #define EFI_USB_NOERROR 0x00
214 #define EFI_USB_ERR_NOTEXECUTE 0x01
215 #define EFI_USB_ERR_STALL 0x02
216 #define EFI_USB_ERR_BUFFER 0x04
217 #define EFI_USB_ERR_BABBLE 0x08
218 #define EFI_USB_ERR_NAK 0x10
219 #define EFI_USB_ERR_CRC 0x20
220 #define EFI_USB_ERR_TIMEOUT 0x40
221 #define EFI_USB_ERR_BITSTUFF 0x80
222 #define EFI_USB_ERR_SYSTEM 0x100
227 // 7.6.9 OUT/IN EP Context: 64 bytes
228 // 7.6.9.2 When used by the DbC it is always a 64 byte data structure
230 typedef struct _ENDPOINT_CONTEXT_64
{
233 UINT32 Mult
:2; // set to 0
234 UINT32 MaxPStreams
:5; // set to 0
235 UINT32 LSA
:1; // set to 0
236 UINT32 Interval
:8; // set to 0
243 UINT32 HID
:1; // set to 0
244 UINT32 MaxBurstSize
:8;
245 UINT32 MaxPacketSize
:16;
251 UINT32 AverageTRBLength
:16;
252 UINT32 MaxESITPayload
:16; // set to 0
254 UINT32 RsvdZ5
; // Reserved
267 } ENDPOINT_CONTEXT_64
;
270 // 6.4.1.1 Normal TRB: 16 bytes
271 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
272 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
273 // Rings, and to define the Data stage information for Control Transfer Rings.
275 typedef struct _TRANSFER_TRB_NORMAL
{
295 } TRANSFER_TRB_NORMAL
;
298 // 6.4.2.1 Transfer Event TRB: 16 bytes
299 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
300 // for more information on the use and operation of Transfer Events.
302 typedef struct _EVT_TRB_TRANSFER
{
308 UINT32 Completecode
:8;
321 // 6.4.4.1 Link TRB: 16 bytes
322 // A Link TRB provides support for non-contiguous TRB Rings.
324 typedef struct _LINK_TRB
{
330 UINT32 InterTarget
:10;
343 // TRB Template: 16 bytes
345 typedef struct _TRB_TEMPLATE
{
359 // Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes
361 typedef struct _EVENT_RING_SEG_TABLE_ENTRY
{
364 UINT32 RingTrbSize
:16;
367 } EVENT_RING_SEG_TABLE_ENTRY
;
372 typedef struct _EVENT_RING
{
373 EFI_PHYSICAL_ADDRESS ERSTBase
;
374 EFI_PHYSICAL_ADDRESS EventRingSeg0
;
376 EFI_PHYSICAL_ADDRESS EventRingEnqueue
;
377 EFI_PHYSICAL_ADDRESS EventRingDequeue
;
382 typedef struct _TRANSFER_RING
{
383 EFI_PHYSICAL_ADDRESS RingSeg0
;
385 EFI_PHYSICAL_ADDRESS RingEnqueue
;
386 EFI_PHYSICAL_ADDRESS RingDequeue
;
393 typedef struct _DBC_INFO_CONTEXT
{
394 UINT64 String0DescAddress
;
395 UINT64 ManufacturerStrDescAddress
;
396 UINT64 ProductStrDescAddress
;
397 UINT64 SerialNumberStrDescAddress
;
398 UINT64 String0Length
:8;
399 UINT64 ManufacturerStrLength
:8;
400 UINT64 ProductStrLength
:8;
401 UINT64 SerialNumberStrLength
:8;
409 // Debug Capability Context Data Structure: 192 bytes
411 typedef struct _XHC_DC_CONTEXT
{
412 DBC_INFO_CONTEXT DbcInfoContext
;
413 ENDPOINT_CONTEXT_64 EpOutContext
;
414 ENDPOINT_CONTEXT_64 EpInContext
;
421 TRB_TEMPLATE TrbTemplate
;
422 TRANSFER_TRB_NORMAL TrbNormal
;
426 /// USB data transfer direction
432 } EFI_USB_DATA_DIRECTION
;
435 // URB (Usb Request Block) contains information for all kinds of
438 typedef struct _URB
{
440 // Transfer data buffer
442 EFI_PHYSICAL_ADDRESS Data
;
450 // Completed data length
456 EFI_PHYSICAL_ADDRESS Ring
;
457 EFI_PHYSICAL_ADDRESS Trb
;
459 EFI_USB_DATA_DIRECTION Direction
;
462 typedef struct _USB3_DEBUG_PORT_INSTANCE
{
466 // The flag indicates debug device is ready
468 BOOLEAN DebugSupport
;
471 // The flag indicates debug device is ready
476 // The flag indicates if USB 3.0 ports has been turn off/on power
478 BOOLEAN ChangePortPower
;
481 // XHCI MMIO Base address
483 EFI_PHYSICAL_ADDRESS XhciMmioBase
;
486 // XHCI OP RegisterBase address
488 EFI_PHYSICAL_ADDRESS XhciOpRegister
;
491 // XHCI Debug Register Base Address
493 EFI_PHYSICAL_ADDRESS DebugCapabilityBase
;
496 // XHCI Debug Capability offset
498 UINT64 DebugCapabilityOffset
;
501 // XHCI Debug Context Address
503 EFI_PHYSICAL_ADDRESS DebugCapabilityContext
;
508 TRANSFER_RING TransferRingOut
;
509 TRANSFER_RING TransferRingIn
;
514 EVENT_RING EventRing
;
527 // The available data length in the following data buffer.
531 // The data buffer. Maximum length is 8 bytes.
537 UINT64 TimerFrequency
;
539 BOOLEAN TimerCountDown
;
541 } USB3_DEBUG_PORT_HANDLE
;
546 Read XHCI debug register.
548 @param Handle Debug port handle.
549 @param Offset The offset of the debug register.
551 @return The register content read
556 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
561 Set one bit of the debug register while keeping other bits.
563 @param Handle Debug port handle.
564 @param Offset The offset of the debug register.
565 @param Bit The bit mask of the register to set.
570 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
576 Write the data to the debug register.
578 @param Handle Debug port handle.
579 @param Offset The offset of the debug register.
580 @param Data The data to write.
585 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
591 Discover the USB3 debug device.
593 @param Handle Debug port handle.
595 @retval RETURN_SUCCESS The serial device was initialized.
596 @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
600 DiscoverUsb3DebugPort(
601 USB3_DEBUG_PORT_HANDLE
*Handle
605 Initialize the Serial Device hardware.
607 @param Handle Debug port handle.
609 @retval RETURN_SUCCESS The serial device was initialized successfully.
610 @retval !RETURN_SUCCESS Error.
614 InitializeUsb3DebugPort (
615 USB3_DEBUG_PORT_HANDLE
*Handle
619 Return XHCI MMIO base address.
628 Verifies if the bit positions specified by a mask are set in a register.
630 @param[in, out] Register UNITN register
631 @param[in] BitMask 32-bit mask
633 @return BOOLEAN - TRUE if all bits specified by the mask are enabled.
634 - FALSE even if one of the bits specified by the mask
644 Sets bits as per the enabled bit positions in the mask.
646 @param[in, out] Register UINTN register
647 @param[in] BitMask 32-bit mask
656 Clears bits as per the enabled bit positions in the mask.
658 @param[in, out] Register UINTN register
659 @param[in] BitMask 32-bit mask
663 IN OUT UINTN Register
,
668 Initialize USB3 debug port.
670 This method invokes various internal functions to facilitate
671 detection and initialization of USB3 debug port.
673 @retval RETURN_SUCCESS The serial device was initialized.
682 Return command register value in XHCI controller.
691 Allocate aligned memory for XHC's usage.
693 @param BufferSize The size, in bytes, of the Buffer.
695 @return A pointer to the allocated buffer or NULL if allocation fails.
699 AllocateAlignBuffer (
704 The real function to initialize USB3 debug port.
706 This method invokes various internal functions to facilitate
707 detection and initialization of USB3 debug port.
709 @retval RETURN_SUCCESS The serial device was initialized.
718 Submits bulk transfer to a bulk endpoint of a USB device.
720 @param Handle The instance of debug device.
721 @param Direction The direction of data transfer.
722 @param Data Array of pointers to the buffers of data to transmit
723 from or receive into.
724 @param DataLength The lenght of the data buffer.
725 @param Timeout Indicates the maximum time, in millisecond, which
726 the transfer is allowed to complete.
728 @retval EFI_SUCCESS The transfer was completed successfully.
729 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
730 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
731 @retval EFI_TIMEOUT The transfer failed due to timeout.
732 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
738 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
739 IN EFI_USB_DATA_DIRECTION Direction
,
741 IN OUT UINTN
*DataLength
,
746 Check if the timer is timeout.
748 @param[in] UsbDebugPortHandle Pointer to USB Debug port handle
749 @param[in] Timer The start timer from the begin.
750 @param[in] TimeoutTicker Ticker number need time out.
752 @return TRUE Timer time out occurs.
753 @retval FALSE Timer does not time out.
758 IN USB3_DEBUG_PORT_HANDLE
*UsbDebugPortHandle
,
760 IN UINT64 TimeoutTicker
763 #endif //__SERIAL_PORT_LIB_USB__