2 Debug Port Library implementation based on usb3 debug port.
4 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
9 #ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__
10 #define __USB3_DEBUG_PORT_LIB_INTERNAL__
14 #include <IndustryStandard/Usb.h>
15 #include <Library/IoLib.h>
16 #include <IndustryStandard/Pci.h>
17 #include <Library/PcdLib.h>
18 #include <Library/UefiLib.h>
19 #include <Library/UefiBootServicesTableLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/BaseMemoryLib.h>
23 #include <Library/BaseLib.h>
24 #include <Library/TimerLib.h>
25 #include <Library/DebugCommunicationLib.h>
26 #include <Library/PciLib.h>
29 // USB Debug GUID value
31 #define USB3_DBG_GUID \
33 0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \
37 // The state machine of usb debug port
39 #define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability
40 #define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability
41 #define USB3DBG_ENABLED 2 // The XHCI debug device is enabled
42 #define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled
43 #define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized
45 #define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08
48 // MaxPacketSize for DbC Endpoint Descriptor IN and OUT
50 #define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400
52 #define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525
53 #define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A
54 #define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF
55 #define XHCI_DEBUG_DEVICE_REVISION 0x00
57 #define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL
58 #define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000
60 #define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A
61 #define XHC_HCCPARAMS_OFFSET 0x10
62 #define XHC_CAPABILITY_ID_MASK 0xFF
63 #define XHC_NEXT_CAPABILITY_MASK 0xFF00
65 #define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1
66 #define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset
67 #define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset
68 #define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset
70 #define XHC_USBCMD_RUN BIT0 // Run/Stop
71 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
73 #define XHC_USBSTS_HALT BIT0
76 // Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.
78 #define DATA_TRANSFER_WRITE_TIMEOUT 0
79 #define DATA_TRANSFER_READ_TIMEOUT 50000
80 #define DATA_TRANSFER_POLL_TIMEOUT 1000
81 #define XHC_DEBUG_PORT_1_MILLISECOND 1000
83 // XHCI port power off/on delay
85 #define XHC_DEBUG_PORT_ON_OFF_DELAY 100000
88 // USB debug device string descritpor (header size + unicode string length)
90 #define STRING0_DESC_LEN 4
91 #define MANU_DESC_LEN 12
92 #define PRODUCT_DESC_LEN 40
93 #define SERIAL_DESC_LEN 4
96 // Debug Capability Register Offset
98 #define XHC_DC_DCID 0x0
99 #define XHC_DC_DCDB 0x4
100 #define XHC_DC_DCERSTSZ 0x8
101 #define XHC_DC_DCERSTBA 0x10
102 #define XHC_DC_DCERDP 0x18
103 #define XHC_DC_DCCTRL 0x20
104 #define XHC_DC_DCST 0x24
105 #define XHC_DC_DCPORTSC 0x28
106 #define XHC_DC_DCCP 0x30
107 #define XHC_DC_DCDDI1 0x38
108 #define XHC_DC_DCDDI2 0x3C
110 #define TRB_TYPE_LINK 6
112 #define ERST_NUMBER 0x01
113 #define TR_RING_TRB_NUMBER 0x100
114 #define EVENT_RING_TRB_NUMBER 0x200
116 #define ED_BULK_OUT 2
119 #define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))
120 #define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))
121 #define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
124 // Endpoint Type (EP Type).
126 #define ED_NOT_VALID 0
127 #define ED_ISOCH_OUT 1
128 #define ED_BULK_OUT 2
129 #define ED_INTERRUPT_OUT 3
130 #define ED_CONTROL_BIDIR 4
131 #define ED_ISOCH_IN 5
133 #define ED_INTERRUPT_IN 7
136 // 6.4.5 TRB Completion Codes
138 #define TRB_COMPLETION_INVALID 0
139 #define TRB_COMPLETION_SUCCESS 1
140 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
141 #define TRB_COMPLETION_BABBLE_ERROR 3
142 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
143 #define TRB_COMPLETION_TRB_ERROR 5
144 #define TRB_COMPLETION_STALL_ERROR 6
145 #define TRB_COMPLETION_SHORT_PACKET 13
150 #define TRB_TYPE_NORMAL 1
151 #define TRB_TYPE_SETUP_STAGE 2
152 #define TRB_TYPE_DATA_STAGE 3
153 #define TRB_TYPE_STATUS_STAGE 4
154 #define TRB_TYPE_ISOCH 5
155 #define TRB_TYPE_LINK 6
156 #define TRB_TYPE_EVENT_DATA 7
157 #define TRB_TYPE_NO_OP 8
158 #define TRB_TYPE_EN_SLOT 9
159 #define TRB_TYPE_DIS_SLOT 10
160 #define TRB_TYPE_ADDRESS_DEV 11
161 #define TRB_TYPE_CON_ENDPOINT 12
162 #define TRB_TYPE_EVALU_CONTXT 13
163 #define TRB_TYPE_RESET_ENDPOINT 14
164 #define TRB_TYPE_STOP_ENDPOINT 15
165 #define TRB_TYPE_SET_TR_DEQUE 16
166 #define TRB_TYPE_RESET_DEV 17
167 #define TRB_TYPE_GET_PORT_BANW 21
168 #define TRB_TYPE_FORCE_HEADER 22
169 #define TRB_TYPE_NO_OP_COMMAND 23
170 #define TRB_TYPE_TRANS_EVENT 32
171 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
172 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
173 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
174 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
175 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
178 // Convert millisecond to microsecond.
180 #define XHC_1_MILLISECOND (1000)
181 #define XHC_POLL_DELAY (1000)
182 #define XHC_GENERIC_TIMEOUT (10 * 1000)
184 #define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.
185 #define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.
186 #define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.
187 #define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.
190 // Transfer types, used in URB to identify the transfer type
192 #define XHC_CTRL_TRANSFER 0x01
193 #define XHC_BULK_TRANSFER 0x02
194 #define XHC_INT_TRANSFER_SYNC 0x04
195 #define XHC_INT_TRANSFER_ASYNC 0x08
196 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
199 // USB Transfer Results
201 #define EFI_USB_NOERROR 0x00
202 #define EFI_USB_ERR_NOTEXECUTE 0x01
203 #define EFI_USB_ERR_STALL 0x02
204 #define EFI_USB_ERR_BUFFER 0x04
205 #define EFI_USB_ERR_BABBLE 0x08
206 #define EFI_USB_ERR_NAK 0x10
207 #define EFI_USB_ERR_CRC 0x20
208 #define EFI_USB_ERR_TIMEOUT 0x40
209 #define EFI_USB_ERR_BITSTUFF 0x80
210 #define EFI_USB_ERR_SYSTEM 0x100
215 // 7.6.9 OUT/IN EP Context: 64 bytes
216 // 7.6.9.2 When used by the DbC it is always a 64 byte data structure
218 typedef struct _ENDPOINT_CONTEXT_64
{
221 UINT32 Mult
:2; // set to 0
222 UINT32 MaxPStreams
:5; // set to 0
223 UINT32 LSA
:1; // set to 0
224 UINT32 Interval
:8; // set to 0
231 UINT32 HID
:1; // set to 0
232 UINT32 MaxBurstSize
:8;
233 UINT32 MaxPacketSize
:16;
239 UINT32 AverageTRBLength
:16;
240 UINT32 MaxESITPayload
:16; // set to 0
242 UINT32 RsvdZ5
; // Reserved
255 } ENDPOINT_CONTEXT_64
;
258 // 6.4.1.1 Normal TRB: 16 bytes
259 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
260 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
261 // Rings, and to define the Data stage information for Control Transfer Rings.
263 typedef struct _TRANSFER_TRB_NORMAL
{
283 } TRANSFER_TRB_NORMAL
;
286 // 6.4.2.1 Transfer Event TRB: 16 bytes
287 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
288 // for more information on the use and operation of Transfer Events.
290 typedef struct _EVT_TRB_TRANSFER
{
296 UINT32 Completecode
:8;
309 // 6.4.4.1 Link TRB: 16 bytes
310 // A Link TRB provides support for non-contiguous TRB Rings.
312 typedef struct _LINK_TRB
{
318 UINT32 InterTarget
:10;
331 // TRB Template: 16 bytes
333 typedef struct _TRB_TEMPLATE
{
347 // Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes
349 typedef struct _EVENT_RING_SEG_TABLE_ENTRY
{
352 UINT32 RingTrbSize
:16;
355 } EVENT_RING_SEG_TABLE_ENTRY
;
360 typedef struct _EVENT_RING
{
361 EFI_PHYSICAL_ADDRESS ERSTBase
;
362 EFI_PHYSICAL_ADDRESS EventRingSeg0
;
364 EFI_PHYSICAL_ADDRESS EventRingEnqueue
;
365 EFI_PHYSICAL_ADDRESS EventRingDequeue
;
370 typedef struct _TRANSFER_RING
{
371 EFI_PHYSICAL_ADDRESS RingSeg0
;
373 EFI_PHYSICAL_ADDRESS RingEnqueue
;
374 EFI_PHYSICAL_ADDRESS RingDequeue
;
381 typedef struct _DBC_INFO_CONTEXT
{
382 UINT64 String0DescAddress
;
383 UINT64 ManufacturerStrDescAddress
;
384 UINT64 ProductStrDescAddress
;
385 UINT64 SerialNumberStrDescAddress
;
386 UINT64 String0Length
:8;
387 UINT64 ManufacturerStrLength
:8;
388 UINT64 ProductStrLength
:8;
389 UINT64 SerialNumberStrLength
:8;
397 // Debug Capability Context Data Structure: 192 bytes
399 typedef struct _XHC_DC_CONTEXT
{
400 DBC_INFO_CONTEXT DbcInfoContext
;
401 ENDPOINT_CONTEXT_64 EpOutContext
;
402 ENDPOINT_CONTEXT_64 EpInContext
;
409 TRB_TEMPLATE TrbTemplate
;
410 TRANSFER_TRB_NORMAL TrbNormal
;
414 /// USB data transfer direction
420 } EFI_USB_DATA_DIRECTION
;
423 // URB (Usb Request Block) contains information for all kinds of
426 typedef struct _URB
{
428 // Transfer data buffer
430 EFI_PHYSICAL_ADDRESS Data
;
438 // Completed data length
444 EFI_PHYSICAL_ADDRESS Ring
;
445 EFI_PHYSICAL_ADDRESS Trb
;
447 EFI_USB_DATA_DIRECTION Direction
;
450 typedef struct _USB3_DEBUG_PORT_INSTANCE
{
454 // The flag indicates debug capability is supported
456 BOOLEAN DebugSupport
;
459 // The flag indicates debug device is ready
464 // The flag indicates the instance is from HOB
469 // Prevent notification being interrupted by debug timer
474 // PciIo protocol event
476 EFI_PHYSICAL_ADDRESS PciIoEvent
;
479 // The flag indicates if USB 3.0 ports has been turn off/on power
481 BOOLEAN ChangePortPower
;
484 // XHCI MMIO Base address
486 EFI_PHYSICAL_ADDRESS XhciMmioBase
;
489 // XHCI OP RegisterBase address
491 EFI_PHYSICAL_ADDRESS XhciOpRegister
;
494 // XHCI Debug Register Base Address
496 EFI_PHYSICAL_ADDRESS DebugCapabilityBase
;
499 // XHCI Debug Capability offset
501 UINT64 DebugCapabilityOffset
;
504 // XHCI Debug Context Address
506 EFI_PHYSICAL_ADDRESS DebugCapabilityContext
;
511 TRANSFER_RING TransferRingOut
;
512 TRANSFER_RING TransferRingIn
;
517 EVENT_RING EventRing
;
530 // The available data length in the following data buffer.
534 // The data buffer address for data read and poll.
536 EFI_PHYSICAL_ADDRESS Data
;
537 } USB3_DEBUG_PORT_HANDLE
;
542 Read XHCI debug register.
544 @param Handle Debug port handle.
545 @param Offset The offset of the debug register.
547 @return The register content read
552 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
557 Set one bit of the debug register while keeping other bits.
559 @param Handle Debug port handle.
560 @param Offset The offset of the debug register.
561 @param Bit The bit mask of the register to set.
566 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
572 Write the data to the debug register.
574 @param Handle Debug port handle.
575 @param Offset The offset of the debug register.
576 @param Data The data to write.
581 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
587 Verifies if the bit positions specified by a mask are set in a register.
589 @param[in, out] Register UNITN register
590 @param[in] BitMask 32-bit mask
592 @return BOOLEAN - TRUE if all bits specified by the mask are enabled.
593 - FALSE even if one of the bits specified by the mask
603 Sets bits as per the enabled bit positions in the mask.
605 @param[in, out] Register UINTN register
606 @param[in] BitMask 32-bit mask
615 Clears bits as per the enabled bit positions in the mask.
617 @param[in, out] Register UINTN register
618 @param[in] BitMask 32-bit mask
622 IN OUT UINTN Register
,
627 Initialize USB3 debug port.
629 This method invokes various internal functions to facilitate
630 detection and initialization of USB3 debug port.
632 @retval RETURN_SUCCESS The serial device was initialized.
641 Return command register value in XHCI controller.
650 Allocate aligned memory for XHC's usage.
652 @param BufferSize The size, in bytes, of the Buffer.
654 @return A pointer to the allocated buffer or NULL if allocation fails.
658 AllocateAlignBuffer (
663 The real function to initialize USB3 debug port.
665 This method invokes various internal functions to facilitate
666 detection and initialization of USB3 debug port.
668 @retval RETURN_SUCCESS The serial device was initialized.
677 Submits bulk transfer to a bulk endpoint of a USB device.
679 @param Handle The instance of debug device.
680 @param Direction The direction of data transfer.
681 @param Data Array of pointers to the buffers of data to transmit
682 from or receive into.
683 @param DataLength The lenght of the data buffer.
684 @param Timeout Indicates the maximum time, in millisecond, which
685 the transfer is allowed to complete.
687 @retval EFI_SUCCESS The transfer was completed successfully.
688 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
689 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
690 @retval EFI_TIMEOUT The transfer failed due to timeout.
691 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
697 IN USB3_DEBUG_PORT_HANDLE
*Handle
,
698 IN EFI_USB_DATA_DIRECTION Direction
,
700 IN OUT UINTN
*DataLength
,
705 Initialize usb debug port hardware.
707 @param Handle Debug port handle.
709 @retval TRUE The usb debug port hardware configuration is changed.
710 @retval FALSE The usb debug port hardware configuration is not changed.
715 InitializeUsbDebugHardware (
716 IN USB3_DEBUG_PORT_HANDLE
*Handle
720 Return USB3 debug instance address pointer.
723 EFI_PHYSICAL_ADDRESS
*
724 GetUsb3DebugPortInstanceAddrPtr (
729 Return USB3 debug instance address.
732 USB3_DEBUG_PORT_HANDLE
*
733 GetUsb3DebugPortInstance (
737 #endif //__SERIAL_PORT_LIB_USB__