UefiCpuPkg/CpuDxe/CpuDxe.h

   1 /** @file
   2   CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.
   3
   4   Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_DXE_H_
  16 #define _CPU_DXE_H_
  17
  18 #include <PiDxe.h>
  19
  20 #include <Protocol/Cpu.h>
  21 #include <Protocol/MpService.h>
  22 #include <Register/Msr.h>
  23
  24 #include <Ppi/SecPlatformInformation.h>
  25 #include <Ppi/SecPlatformInformation2.h>
  26
  27 #include <Library/UefiDriverEntryPoint.h>
  28 #include <Library/UefiBootServicesTableLib.h>
  29 #include <Library/DxeServicesTableLib.h>
  30 #include <Library/BaseLib.h>
  31 #include <Library/CpuLib.h>
  32 #include <Library/BaseMemoryLib.h>
  33 #include <Library/MemoryAllocationLib.h>
  34 #include <Library/DebugLib.h>
  35 #include <Library/MtrrLib.h>
  36 #include <Library/LocalApicLib.h>
  37 #include <Library/UefiCpuLib.h>
  38 #include <Library/UefiLib.h>
  39 #include <Library/CpuExceptionHandlerLib.h>
  40 #include <Library/HobLib.h>
  41 #include <Library/ReportStatusCodeLib.h>
  42 #include <Library/MpInitLib.h>
  43 #include <Library/TimerLib.h>
  44
  45 #include <Guid/IdleLoopEvent.h>
  46 #include <Guid/VectorHandoffTable.h>
  47
  48 #define EFI_MEMORY_CACHETYPE_MASK     (EFI_MEMORY_UC  | \
  49                                        EFI_MEMORY_WC  | \
  50                                        EFI_MEMORY_WT  | \
  51                                        EFI_MEMORY_WB  | \
  52                                        EFI_MEMORY_UCE   \
  53                                        )
  54
  55 #define EFI_MEMORY_PAGETYPE_MASK      (EFI_MEMORY_RP  | \
  56                                        EFI_MEMORY_XP  | \
  57                                        EFI_MEMORY_RO    \
  58                                        )
  59
  60 /**
  61   Flush CPU data cache. If the instruction cache is fully coherent
  62   with all DMA operations then function can just return EFI_SUCCESS.
  63
  64   @param  This              Protocol instance structure
  65   @param  Start             Physical address to start flushing from.
  66   @param  Length            Number of bytes to flush. Round up to chipset
  67                             granularity.
  68   @param  FlushType         Specifies the type of flush operation to perform.
  69
  70   @retval EFI_SUCCESS       If cache was flushed
  71   @retval EFI_UNSUPPORTED   If flush type is not supported.
  72   @retval EFI_DEVICE_ERROR  If requested range could not be flushed.
  73
  74 **/
  75 EFI_STATUS
  76 EFIAPI
  77 CpuFlushCpuDataCache (
  78   IN EFI_CPU_ARCH_PROTOCOL     *This,
  79   IN EFI_PHYSICAL_ADDRESS      Start,
  80   IN UINT64                    Length,
  81   IN EFI_CPU_FLUSH_TYPE        FlushType
  82   );
  83
  84 /**
  85   Enables CPU interrupts.
  86
  87   @param  This              Protocol instance structure
  88
  89   @retval EFI_SUCCESS       If interrupts were enabled in the CPU
  90   @retval EFI_DEVICE_ERROR  If interrupts could not be enabled on the CPU.
  91
  92 **/
  93 EFI_STATUS
  94 EFIAPI
  95 CpuEnableInterrupt (
  96   IN EFI_CPU_ARCH_PROTOCOL     *This
  97   );
  98
  99 /**
 100   Disables CPU interrupts.
 101
 102   @param  This              Protocol instance structure
 103
 104   @retval EFI_SUCCESS       If interrupts were disabled in the CPU.
 105   @retval EFI_DEVICE_ERROR  If interrupts could not be disabled on the CPU.
 106
 107 **/
 108 EFI_STATUS
 109 EFIAPI
 110 CpuDisableInterrupt (
 111   IN EFI_CPU_ARCH_PROTOCOL     *This
 112   );
 113
 114 /**
 115   Return the state of interrupts.
 116
 117   @param  This                   Protocol instance structure
 118   @param  State                  Pointer to the CPU's current interrupt state
 119
 120   @retval EFI_SUCCESS            If interrupts were disabled in the CPU.
 121   @retval EFI_INVALID_PARAMETER  State is NULL.
 122
 123 **/
 124 EFI_STATUS
 125 EFIAPI
 126 CpuGetInterruptState (
 127   IN  EFI_CPU_ARCH_PROTOCOL     *This,
 128   OUT BOOLEAN                   *State
 129   );
 130
 131 /**
 132   Generates an INIT to the CPU.
 133
 134   @param  This              Protocol instance structure
 135   @param  InitType          Type of CPU INIT to perform
 136
 137   @retval EFI_SUCCESS       If CPU INIT occurred. This value should never be
 138                             seen.
 139   @retval EFI_DEVICE_ERROR  If CPU INIT failed.
 140   @retval EFI_UNSUPPORTED   Requested type of CPU INIT not supported.
 141
 142 **/
 143 EFI_STATUS
 144 EFIAPI
 145 CpuInit (
 146   IN EFI_CPU_ARCH_PROTOCOL     *This,
 147   IN EFI_CPU_INIT_TYPE         InitType
 148   );
 149
 150 /**
 151   Registers a function to be called from the CPU interrupt handler.
 152
 153   @param  This                   Protocol instance structure
 154   @param  InterruptType          Defines which interrupt to hook. IA-32
 155                                  valid range is 0x00 through 0xFF
 156   @param  InterruptHandler       A pointer to a function of type
 157                                  EFI_CPU_INTERRUPT_HANDLER that is called
 158                                  when a processor interrupt occurs.  A null
 159                                  pointer is an error condition.
 160
 161   @retval EFI_SUCCESS            If handler installed or uninstalled.
 162   @retval EFI_ALREADY_STARTED    InterruptHandler is not NULL, and a handler
 163                                  for InterruptType was previously installed.
 164   @retval EFI_INVALID_PARAMETER  InterruptHandler is NULL, and a handler for
 165                                  InterruptType was not previously installed.
 166   @retval EFI_UNSUPPORTED        The interrupt specified by InterruptType
 167                                  is not supported.
 168
 169 **/
 170 EFI_STATUS
 171 EFIAPI
 172 CpuRegisterInterruptHandler (
 173   IN EFI_CPU_ARCH_PROTOCOL         *This,
 174   IN EFI_EXCEPTION_TYPE            InterruptType,
 175   IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
 176   );
 177
 178 /**
 179   Returns a timer value from one of the CPU's internal timers. There is no
 180   inherent time interval between ticks but is a function of the CPU frequency.
 181
 182   @param  This                - Protocol instance structure.
 183   @param  TimerIndex          - Specifies which CPU timer is requested.
 184   @param  TimerValue          - Pointer to the returned timer value.
 185   @param  TimerPeriod         - A pointer to the amount of time that passes
 186                                 in femtoseconds (10-15) for each increment
 187                                 of TimerValue. If TimerValue does not
 188                                 increment at a predictable rate, then 0 is
 189                                 returned.  The amount of time that has
 190                                 passed between two calls to GetTimerValue()
 191                                 can be calculated with the formula
 192                                 (TimerValue2 - TimerValue1) * TimerPeriod.
 193                                 This parameter is optional and may be NULL.
 194
 195   @retval EFI_SUCCESS           - If the CPU timer count was returned.
 196   @retval EFI_UNSUPPORTED       - If the CPU does not have any readable timers.
 197   @retval EFI_DEVICE_ERROR      - If an error occurred while reading the timer.
 198   @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
 199
 200 **/
 201 EFI_STATUS
 202 EFIAPI
 203 CpuGetTimerValue (
 204   IN  EFI_CPU_ARCH_PROTOCOL       *This,
 205   IN  UINT32                      TimerIndex,
 206   OUT UINT64                      *TimerValue,
 207   OUT UINT64                      *TimerPeriod OPTIONAL
 208   );
 209
 210 /**
 211   Set memory cacheability attributes for given range of memeory.
 212
 213   @param  This                   Protocol instance structure
 214   @param  BaseAddress            Specifies the start address of the
 215                                  memory range
 216   @param  Length                 Specifies the length of the memory range
 217   @param  Attributes             The memory cacheability for the memory range
 218
 219   @retval EFI_SUCCESS            If the cacheability of that memory range is
 220                                  set successfully
 221   @retval EFI_UNSUPPORTED        If the desired operation cannot be done
 222   @retval EFI_INVALID_PARAMETER  The input parameter is not correct,
 223                                  such as Length = 0
 224
 225 **/
 226 EFI_STATUS
 227 EFIAPI
 228 CpuSetMemoryAttributes (
 229   IN EFI_CPU_ARCH_PROTOCOL      *This,
 230   IN EFI_PHYSICAL_ADDRESS       BaseAddress,
 231   IN UINT64                     Length,
 232   IN UINT64                     Attributes
 233   );
 234
 235 /**
 236   Initialize Global Descriptor Table.
 237
 238 **/
 239 VOID
 240 InitGlobalDescriptorTable (
 241   VOID
 242   );
 243
 244 /**
 245   Sets the code selector (CS).
 246
 247   @param  Selector  Value of code selector.
 248
 249 **/
 250 VOID
 251 EFIAPI
 252 SetCodeSelector (
 253   UINT16 Selector
 254   );
 255
 256 /**
 257   Sets the data selector (DS).
 258
 259   @param  Selector  Value of data selector.
 260
 261 **/
 262 VOID
 263 EFIAPI
 264 SetDataSelectors (
 265   UINT16 Selector
 266   );
 267
 268 /**
 269   Update GCD memory space attributes according to current page table setup.
 270 **/
 271 VOID
 272 RefreshGcdMemoryAttributesFromPaging (
 273   VOID
 274   );
 275
 276 #endif
 277