2 ;------------------------------------------------------------------------------
4 ;* Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
5 ;* This program and the accompanying materials
6 ;* are licensed and made available under the terms and conditions of the BSD License
7 ;* which accompanies this distribution. The full text of the license may be found at
8 ;* http://opensource.org/licenses/bsd-license.php
10 ;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 ;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ;------------------------------------------------------------------------------
21 EXTRN mErrorCodeFlag:DWORD ; Error code flags for exceptions
24 ; point to the external interrupt vector table
26 ExternalVectorTablePtr QWORD 0
28 InitializeExternalVectorTablePtr PROC PUBLIC
29 mov ExternalVectorTablePtr, rcx
31 InitializeExternalVectorTablePtr ENDP
33 ;------------------------------------------------------------------------------
38 ;------------------------------------------------------------------------------
39 SetCodeSelector PROC PUBLIC
41 lea rax, setCodeSelectorLongJump
45 setCodeSelectorLongJump:
50 ;------------------------------------------------------------------------------
55 ;------------------------------------------------------------------------------
56 SetDataSelectors PROC PUBLIC
65 ;---------------------------------------;
66 ; CommonInterruptEntry ;
67 ;---------------------------------------;
68 ; The follow algorithm is used for the common interrupt routine.
70 CommonInterruptEntry PROC PUBLIC
73 ; All interrupt handlers are invoked through interrupt gates, so
74 ; IF flag automatically cleared at the entry point
77 ; Calculate vector number
79 xchg rcx, [rsp] ; get the return address of call, actually, it is the address of vector number.
80 movzx ecx, word ptr [rcx]
81 cmp ecx, 32 ; Intel reserved vector for exceptions?
83 bt mErrorCodeFlag, ecx
89 ; Push a dummy error code on the stack
90 ; to maintain coherent stack map
93 mov qword ptr [rsp + 8], 0
100 ; +---------------------+ <-- 16-byte aligned ensured by processor
102 ; +---------------------+
104 ; +---------------------+
106 ; +---------------------+
108 ; +---------------------+
110 ; +---------------------+
112 ; +---------------------+
113 ; + RCX / Vector Number +
114 ; +---------------------+
116 ; +---------------------+ <-- RBP, 16-byte aligned
121 ; Since here the stack pointer is 16-byte aligned, so
122 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
126 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
127 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
137 push qword ptr [rbp + 8] ; RCX
140 push qword ptr [rbp + 48] ; RSP
141 push qword ptr [rbp] ; RBP
145 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
146 movzx rax, word ptr [rbp + 56]
148 movzx rax, word ptr [rbp + 32]
159 mov [rbp + 8], rcx ; save vector number
162 push qword ptr [rbp + 24]
164 ;; UINT64 Gdtr[2], Idtr[2];
189 push qword ptr [rbp + 40]
191 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
207 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
221 ;; FX_SAVE_STATE_X64 FxSaveState;
224 db 0fh, 0aeh, 07h ;fxsave [rdi]
226 ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
229 ;; UINT32 ExceptionData;
230 push qword ptr [rbp + 16]
232 ;; call into exception handler
234 mov rax, ExternalVectorTablePtr ; get the interrupt vectors base
235 mov rax, [rax + rcx * 8]
240 ;; Prepare parameter and call
244 ; Per X64 calling convention, allocate maximum parameter stack space
245 ; and make sure RSP is 16-byte aligned
253 ;; UINT64 ExceptionData;
256 ;; FX_SAVE_STATE_X64 FxSaveState;
259 db 0fh, 0aeh, 0Eh ; fxrstor [rsi]
262 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
263 ;; Skip restoration of DRx registers to support in-circuit emualators
264 ;; or debuggers set breakpoint in interrupt/exception context
267 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
270 add rsp, 8 ; not for Cr1
281 pop qword ptr [rbp + 40]
284 ;; UINT64 Gdtr[2], Idtr[2];
285 ;; Best not let anyone mess with these particular registers...
289 pop qword ptr [rbp + 24]
291 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
293 ; mov gs, rax ; not for gs
295 ; mov fs, rax ; not for fs
296 ; (X64 will not use fs and gs, so we do not restore it)
301 pop qword ptr [rbp + 32] ; for cs
302 pop qword ptr [rbp + 56] ; for ss
304 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
305 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
308 add rsp, 8 ; not for rbp
309 pop qword ptr [rbp + 48] ; for rsp
328 CommonInterruptEntry ENDP