UefiCpuPkg/Include/Guid/SmmBaseHob.h

   1 /** @file
   2   The Smm Base HOB is used to store the information of:
   3   * The relocated SmBase address in array for each processor.
   4
   5   The default Smbase for the x86 processor is 0x30000. When SMI happens, processor
   6   runs the SMI handler at Smbase+0x8000. Also, the SMM save state area is within
   7   Smbase+0x10000. Since it's the start address to store the processor save state
   8   and code for the SMI entry point, those info are tiled within an SMRAM allocated
   9   or reserved buffer. This tile size shall be enough to cover 3 parts:
  10   1. Processor SMRAM Save State Map starts at Smbase + 0xfc00
  11   2. Extra processor specific context start starts at Smbase + 0xfb00
  12   3. SMI entry point starts at Smbase + 0x8000.
  13   Besides, This size should be rounded up to nearest power of 2. The Smm Base HOB
  14   producer should be responsible for reserving enough size.
  15
  16   One of the SMM initialization from processor perspective is to relocate and program
  17   the new Smbase (in TSEG range) for each processor thread. When the Smbase relocation
  18   happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database
  19   which tells the PiSmmCpuDxeSmm driver (which runs at a later phase) about the new
  20   Smbase for each processor. PiSmmCpuDxeSmm driver installs the SMI handler at the
  21   SMM_BASE_HOB.Smbase[Index]+0x8000 for processor index. When the HOB doesn't exist,
  22   PiSmmCpuDxeSmm driver shall relocate and program the new Smbase itself.
  23
  24   Note:
  25   1. Smbase relocation process needs to program the vender specific hardware
  26   interface to set Smbase, it might be in the thread scope. It's doable to
  27   program the hardware interface using DXE MP service protocol in PiSmmCpuDxeSmm
  28   entry point. But, considering the standalone MM environment where the CpuMm
  29   driver runs in a isolated environment and it cannot invoke any DXE or PEI MP
  30   service, we recommend to put the hardware interface programming in a separate
  31   PEI module instead of in the PiSmmCpuDxeSmm driver.
  32
  33   2. There is the hard requirement that SMI Entry Size <= 0x1000, data Size <=
  34   0x1000 in PiSmmCpuDxeSmm. So, this require the allocated or reserved buffer in
  35   SMRAM should be >= 0x2000.
  36
  37   Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
  38   SPDX-License-Identifier: BSD-2-Clause-Patent
  39
  40 **/
  41
  42 #ifndef SMM_BASE_HOB_H_
  43 #define SMM_BASE_HOB_H_
  44
  45 #define SMM_BASE_HOB_DATA_GUID \
  46   { \
  47     0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73}  \
  48   }
  49
  50 #pragma pack(1)
  51 typedef struct {
  52   ///
  53   /// ProcessorIndex tells which processor range this specific HOB instance described.
  54   /// If ProcessorIndex is set to 0, it indicats the HOB describes the processor from
  55   /// 0 to NumberOfProcessors - 1. The HOB list may contains multiple this HOB
  56   /// instances. Each HOB instances describe the information for processor from
  57   /// ProcessorIndex to ProcessorIndex + NumberOfProcessors - 1. The instance order in
  58   /// the HOB list is random so consumer can not assume the ProcessorIndex of first
  59   /// instance is 0.
  60   ///
  61   UINT32    ProcessorIndex;
  62   ///
  63   /// Describes the Number of all max supported processors.
  64   ///
  65   UINT32    NumberOfProcessors;
  66   ///
  67   /// Pointer to SmBase address for each processor.
  68   ///
  69   UINT64    SmBase[];
  70 } SMM_BASE_HOB_DATA;
  71 #pragma pack()
  72
  73 extern EFI_GUID  gSmmBaseHobGuid;
  74
  75 #endif