2 Public include file for Local APIC library.
4 Local APIC library assumes local APIC is enabled. It does not
5 handles cases where local APIC is disabled.
7 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
12 #ifndef __LOCAL_APIC_LIB_H__
13 #define __LOCAL_APIC_LIB_H__
15 #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.
16 #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.
19 Retrieve the base address of local APIC.
21 @return The base address of local APIC.
26 GetLocalApicBaseAddress (
31 Set the base address of local APIC.
33 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
35 @param[in] BaseAddress Local APIC base address to be set.
40 SetLocalApicBaseAddress (
45 Get the current local APIC mode.
47 If local APIC is disabled, then ASSERT.
49 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
50 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
59 Set the current local APIC mode.
61 If the specified local APIC mode is not valid, then ASSERT.
62 If the specified local APIC mode can't be set as current, then ASSERT.
64 @param ApicMode APIC mode to be set.
66 @note This API must not be called from an interrupt handler or SMI handler.
67 It may result in unpredictable behavior.
76 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
78 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
79 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
80 the 32-bit local APIC ID is returned as initial APIC ID.
82 @return 32-bit initial local APIC ID of the executing processor.
91 Get the local APIC ID of the executing processor.
93 @return 32-bit local APIC ID of the executing processor.
102 Get the value of the local APIC version register.
104 @return the value of the local APIC version register.
113 Send a Fixed IPI to a specified target processor.
115 This function returns after the IPI has been accepted by the target processor.
117 @param ApicId The local APIC ID of the target processor.
118 @param Vector The vector number of the interrupt being sent.
128 Send a Fixed IPI to all processors excluding self.
130 This function returns after the IPI has been accepted by the target processors.
132 @param Vector The vector number of the interrupt being sent.
136 SendFixedIpiAllExcludingSelf (
141 Send a SMI IPI to a specified target processor.
143 This function returns after the IPI has been accepted by the target processor.
145 @param ApicId Specify the local APIC ID of the target processor.
154 Send a SMI IPI to all processors excluding self.
156 This function returns after the IPI has been accepted by the target processors.
160 SendSmiIpiAllExcludingSelf (
165 Send an INIT IPI to a specified target processor.
167 This function returns after the IPI has been accepted by the target processor.
169 @param ApicId Specify the local APIC ID of the target processor.
178 Send an INIT IPI to all processors excluding self.
180 This function returns after the IPI has been accepted by the target processors.
184 SendInitIpiAllExcludingSelf (
189 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
191 This function returns after the IPI has been accepted by the target processor.
193 if StartupRoutine >= 1M, then ASSERT.
194 if StartupRoutine is not multiple of 4K, then ASSERT.
196 @param ApicId Specify the local APIC ID of the target processor.
197 @param StartupRoutine Points to a start-up routine which is below 1M physical
198 address and 4K aligned.
204 IN UINT32 StartupRoutine
208 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
210 This function returns after the IPI has been accepted by the target processors.
212 if StartupRoutine >= 1M, then ASSERT.
213 if StartupRoutine is not multiple of 4K, then ASSERT.
215 @param StartupRoutine Points to a start-up routine which is below 1M physical
216 address and 4K aligned.
220 SendInitSipiSipiAllExcludingSelf (
221 IN UINT32 StartupRoutine
225 Initialize the state of the SoftwareEnable bit in the Local APIC
226 Spurious Interrupt Vector register.
228 @param Enable If TRUE, then set SoftwareEnable to 1
229 If FALSE, then set SoftwareEnable to 0.
234 InitializeLocalApicSoftwareEnable (
239 Programming Virtual Wire Mode.
241 This function programs the local APIC for virtual wire mode following
242 the example described in chapter A.3 of the MP 1.4 spec.
244 IOxAPIC is not involved in this type of virtual wire mode.
248 ProgramVirtualWireMode (
253 Disable LINT0 & LINT1 interrupts.
255 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
259 DisableLvtInterrupts (
264 Read the initial count value from the init-count register.
266 @return The initial count value read from the init-count register.
270 GetApicTimerInitCount (
275 Read the current count value from the current-count register.
277 @return The current count value read from the current-count register.
281 GetApicTimerCurrentCount (
286 Initialize the local APIC timer.
288 The local APIC timer is initialized and enabled.
290 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
291 If it is 0, then use the current divide value in the DCR.
292 @param InitCount The initial count value.
293 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
294 @param Vector The timer interrupt vector number.
298 InitializeApicTimer (
299 IN UINTN DivideValue
,
301 IN BOOLEAN PeriodicMode
,
306 Get the state of the local APIC timer.
308 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
309 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
310 @param Vector Return the timer interrupt vector number.
315 OUT UINTN
*DivideValue OPTIONAL
,
316 OUT BOOLEAN
*PeriodicMode OPTIONAL
,
317 OUT UINT8
*Vector OPTIONAL
321 Enable the local APIC timer interrupt.
325 EnableApicTimerInterrupt (
330 Disable the local APIC timer interrupt.
334 DisableApicTimerInterrupt (
339 Get the local APIC timer interrupt state.
341 @retval TRUE The local APIC timer interrupt is enabled.
342 @retval FALSE The local APIC timer interrupt is disabled.
346 GetApicTimerInterruptState (
351 Send EOI to the local APIC.
360 Get the 32-bit address that a device should use to send a Message Signaled
361 Interrupt (MSI) to the Local APIC of the currently executing processor.
363 @return 32-bit address used to send an MSI to the Local APIC.
372 Get the 64-bit data value that a device should use to send a Message Signaled
373 Interrupt (MSI) to the Local APIC of the currently executing processor.
375 If Vector is not in range 0x10..0xFE, then ASSERT().
376 If DeliveryMode is not supported, then ASSERT().
378 @param Vector The 8-bit interrupt vector associated with the MSI.
379 Must be in the range 0x10..0xFE
380 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
381 is handled. The only supported values are:
382 0: LOCAL_APIC_DELIVERY_MODE_FIXED
383 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
384 2: LOCAL_APIC_DELIVERY_MODE_SMI
385 4: LOCAL_APIC_DELIVERY_MODE_NMI
386 5: LOCAL_APIC_DELIVERY_MODE_INIT
387 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
389 @param LevelTriggered TRUE specifies a level triggered interrupt.
390 FALSE specifies an edge triggered interrupt.
391 @param AssertionLevel Ignored if LevelTriggered is FALSE.
392 TRUE specifies a level triggered interrupt that active
393 when the interrupt line is asserted.
394 FALSE specifies a level triggered interrupt that active
395 when the interrupt line is deasserted.
397 @return 64-bit data value used to send an MSI to the Local APIC.
403 IN UINTN DeliveryMode
,
404 IN BOOLEAN LevelTriggered
,
405 IN BOOLEAN AssertionLevel
409 Get Package ID/Core ID/Thread ID of a processor.
411 The algorithm assumes the target system has symmetry across physical
412 package boundaries with respect to the number of logical processors
413 per package, number of cores per package.
415 @param[in] InitialApicId Initial APIC ID of the target logical processor.
416 @param[out] Package Returns the processor package ID.
417 @param[out] Core Returns the processor core ID.
418 @param[out] Thread Returns the processor thread ID.
422 GetProcessorLocationByApicId (
423 IN UINT32 InitialApicId
,
424 OUT UINT32
*Package OPTIONAL
,
425 OUT UINT32
*Core OPTIONAL
,
426 OUT UINT32
*Thread OPTIONAL
430 Get Package ID/Module ID/Tile ID/Die ID/Core ID/Thread ID of a processor.
432 The algorithm assumes the target system has symmetry across physical
433 package boundaries with respect to the number of threads per core, number of
434 cores per module, number of modules per tile, number of tiles per die, number
437 @param[in] InitialApicId Initial APIC ID of the target logical processor.
438 @param[out] Package Returns the processor package ID.
439 @param[out] Die Returns the processor die ID.
440 @param[out] Tile Returns the processor tile ID.
441 @param[out] Module Returns the processor module ID.
442 @param[out] Core Returns the processor core ID.
443 @param[out] Thread Returns the processor thread ID.
447 GetProcessorLocation2ByApicId (
448 IN UINT32 InitialApicId
,
449 OUT UINT32
*Package OPTIONAL
,
450 OUT UINT32
*Die OPTIONAL
,
451 OUT UINT32
*Tile OPTIONAL
,
452 OUT UINT32
*Module OPTIONAL
,
453 OUT UINT32
*Core OPTIONAL
,
454 OUT UINT32
*Thread OPTIONAL