2 Public include file for Local APIC library.
4 Local APIC library assumes local APIC is enabled. It does not
5 handles cases where local APIC is disabled.
7 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #ifndef __LOCAL_APIC_LIB_H__
19 #define __LOCAL_APIC_LIB_H__
21 #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.
22 #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.
25 Retrieve the base address of local APIC.
27 @return The base address of local APIC.
32 GetLocalApicBaseAddress (
37 Set the base address of local APIC.
39 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
41 @param[in] BaseAddress Local APIC base address to be set.
46 SetLocalApicBaseAddress (
51 Get the current local APIC mode.
53 If local APIC is disabled, then ASSERT.
55 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
56 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
65 Set the current local APIC mode.
67 If the specified local APIC mode is not valid, then ASSERT.
68 If the specified local APIC mode can't be set as current, then ASSERT.
70 @param ApicMode APIC mode to be set.
72 @note This API must not be called from an interrupt handler or SMI handler.
73 It may result in unpredictable behavior.
82 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
84 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
85 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
86 the 32-bit local APIC ID is returned as initial APIC ID.
88 @return 32-bit initial local APIC ID of the executing processor.
97 Get the local APIC ID of the executing processor.
99 @return 32-bit local APIC ID of the executing processor.
108 Get the value of the local APIC version register.
110 @return the value of the local APIC version register.
119 Send a Fixed IPI to a specified target processor.
121 This function returns after the IPI has been accepted by the target processor.
123 @param ApicId The local APIC ID of the target processor.
124 @param Vector The vector number of the interrupt being sent.
134 Send a Fixed IPI to all processors excluding self.
136 This function returns after the IPI has been accepted by the target processors.
138 @param Vector The vector number of the interrupt being sent.
142 SendFixedIpiAllExcludingSelf (
147 Send a SMI IPI to a specified target processor.
149 This function returns after the IPI has been accepted by the target processor.
151 @param ApicId Specify the local APIC ID of the target processor.
160 Send a SMI IPI to all processors excluding self.
162 This function returns after the IPI has been accepted by the target processors.
166 SendSmiIpiAllExcludingSelf (
171 Send an INIT IPI to a specified target processor.
173 This function returns after the IPI has been accepted by the target processor.
175 @param ApicId Specify the local APIC ID of the target processor.
184 Send an INIT IPI to all processors excluding self.
186 This function returns after the IPI has been accepted by the target processors.
190 SendInitIpiAllExcludingSelf (
195 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
197 This function returns after the IPI has been accepted by the target processor.
199 if StartupRoutine >= 1M, then ASSERT.
200 if StartupRoutine is not multiple of 4K, then ASSERT.
202 @param ApicId Specify the local APIC ID of the target processor.
203 @param StartupRoutine Points to a start-up routine which is below 1M physical
204 address and 4K aligned.
210 IN UINT32 StartupRoutine
214 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
216 This function returns after the IPI has been accepted by the target processors.
218 if StartupRoutine >= 1M, then ASSERT.
219 if StartupRoutine is not multiple of 4K, then ASSERT.
221 @param StartupRoutine Points to a start-up routine which is below 1M physical
222 address and 4K aligned.
226 SendInitSipiSipiAllExcludingSelf (
227 IN UINT32 StartupRoutine
231 Programming Virtual Wire Mode.
233 This function programs the local APIC for virtual wire mode following
234 the example described in chapter A.3 of the MP 1.4 spec.
236 IOxAPIC is not involved in this type of virtual wire mode.
240 ProgramVirtualWireMode (
245 Disable LINT0 & LINT1 interrupts.
247 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
251 DisableLvtInterrupts (
256 Read the initial count value from the init-count register.
258 @return The initial count value read from the init-count register.
262 GetApicTimerInitCount (
267 Read the current count value from the current-count register.
269 @return The current count value read from the current-count register.
273 GetApicTimerCurrentCount (
278 Initialize the local APIC timer.
280 The local APIC timer is initialized and enabled.
282 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
283 If it is 0, then use the current divide value in the DCR.
284 @param InitCount The initial count value.
285 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
286 @param Vector The timer interrupt vector number.
290 InitializeApicTimer (
291 IN UINTN DivideValue
,
293 IN BOOLEAN PeriodicMode
,
298 Get the state of the local APIC timer.
300 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
301 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
302 @param Vector Return the timer interrupt vector number.
307 OUT UINTN
*DivideValue OPTIONAL
,
308 OUT BOOLEAN
*PeriodicMode OPTIONAL
,
309 OUT UINT8
*Vector OPTIONAL
313 Enable the local APIC timer interrupt.
317 EnableApicTimerInterrupt (
322 Disable the local APIC timer interrupt.
326 DisableApicTimerInterrupt (
331 Get the local APIC timer interrupt state.
333 @retval TRUE The local APIC timer interrupt is enabled.
334 @retval FALSE The local APIC timer interrupt is disabled.
338 GetApicTimerInterruptState (
343 Send EOI to the local APIC.
352 Get the 32-bit address that a device should use to send a Message Signaled
353 Interrupt (MSI) to the Local APIC of the currently executing processor.
355 @return 32-bit address used to send an MSI to the Local APIC.
364 Get the 64-bit data value that a device should use to send a Message Signaled
365 Interrupt (MSI) to the Local APIC of the currently executing processor.
367 If Vector is not in range 0x10..0xFE, then ASSERT().
368 If DeliveryMode is not supported, then ASSERT().
370 @param Vector The 8-bit interrupt vector associated with the MSI.
371 Must be in the range 0x10..0xFE
372 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
373 is handled. The only supported values are:
374 0: LOCAL_APIC_DELIVERY_MODE_FIXED
375 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
376 2: LOCAL_APIC_DELIVERY_MODE_SMI
377 4: LOCAL_APIC_DELIVERY_MODE_NMI
378 5: LOCAL_APIC_DELIVERY_MODE_INIT
379 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
381 @param LevelTriggered TRUE specifies a level triggered interrupt.
382 FALSE specifies an edge triggered interrupt.
383 @param AssertionLevel Ignored if LevelTriggered is FALSE.
384 TRUE specifies a level triggered interrupt that active
385 when the interrupt line is asserted.
386 FALSE specifies a level triggered interrupt that active
387 when the interrupt line is deasserted.
389 @return 64-bit data value used to send an MSI to the Local APIC.
395 IN UINTN DeliveryMode
,
396 IN BOOLEAN LevelTriggered
,
397 IN BOOLEAN AssertionLevel