2 CPUID leaf definitions.
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
9 Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
11 This program and the accompanying materials are licensed and made available
12 under the terms and conditions of the BSD License which accompanies this
13 distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 @par Specification Reference:
20 AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
24 #ifndef __AMD_CPUID_H__
25 #define __AMD_CPUID_H__
28 CPUID Signature Information
30 @param EAX CPUID_SIGNATURE (0x00)
32 @retval EAX Returns the highest value the CPUID instruction recognizes for
33 returning basic processor information. The value is returned is
35 @retval EBX First 4 characters of a vendor identification string.
36 @retval ECX Last 4 characters of a vendor identification string.
37 @retval EDX Middle 4 characters of a vendor identification string.
42 /// @{ CPUID signature values returned by AMD processors
44 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')
45 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')
46 #define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')
53 CPUID Extended Processor Signature and Features
55 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
57 @retval EAX Extended Family, Model, Stepping Identifiers
58 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
59 @retval EBX Brand Identifier
60 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
61 @retval ECX Extended Feature Identifiers
62 described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
63 @retval EDX Extended Feature Identifiers
64 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
68 CPUID Extended Processor Signature and Features EAX for CPUID leaf
69 #CPUID_EXTENDED_CPU_SIG.
73 /// Individual bit fields
77 /// [Bits 3:0] Stepping.
81 /// [Bits 7:4] Base Model.
85 /// [Bits 11:8] Base Family.
89 /// [Bit 15:12] Reserved.
93 /// [Bits 19:16] Extended Model.
97 /// [Bits 27:20] Extended Family.
101 /// [Bit 31:28] Reserved.
106 /// All bit fields as a 32-bit value
109 } CPUID_AMD_EXTENDED_CPU_SIG_EAX
;
112 CPUID Extended Processor Signature and Features EBX for CPUID leaf
113 #CPUID_EXTENDED_CPU_SIG.
117 /// Individual bit fields
121 /// [Bits 27:0] Reserved.
125 /// [Bit 31:28] Package Type.
130 /// All bit fields as a 32-bit value
133 } CPUID_AMD_EXTENDED_CPU_SIG_EBX
;
136 CPUID Extended Processor Signature and Features ECX for CPUID leaf
137 #CPUID_EXTENDED_CPU_SIG.
141 /// Individual bit fields
145 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
149 /// [Bit 1] Core multi-processing legacy mode.
153 /// [Bit 2] Secure Virtual Mode feature.
157 /// [Bit 3] Extended APIC register space.
159 UINT32 ExtApicSpace
:1;
161 /// [Bit 4] LOCK MOV CR0 means MOV CR8.
165 /// [Bit 5] LZCNT instruction support.
169 /// [Bit 6] SSE4A instruction support.
173 /// [Bit 7] Misaligned SSE Mode.
175 UINT32 MisAlignSse
:1;
177 /// [Bit 8] ThreeDNow Prefetch instructions.
181 /// [Bit 9] OS Visible Work-around support.
185 /// [Bit 10] Instruction Based Sampling.
189 /// [Bit 11] Extended Operation Support.
193 /// [Bit 12] SKINIT and STGI support.
197 /// [Bit 13] Watchdog Timer support.
201 /// [Bit 14] Reserved.
205 /// [Bit 15] Lightweight Profiling support.
209 /// [Bit 16] 4-Operand FMA instruction support.
213 /// [Bit 17] Translation Cache Extension.
217 /// [Bit 21:18] Reserved.
221 /// [Bit 22] Topology Extensions support.
223 UINT32 TopologyExtensions
:1;
225 /// [Bit 23] Core Performance Counter Extensions.
227 UINT32 PerfCtrExtCore
:1;
229 /// [Bit 25:24] Reserved.
233 /// [Bit 26] Data Breakpoint Extension.
235 UINT32 DataBreakpointExtension
:1;
237 /// [Bit 27] Performance Time-Stamp Counter.
241 /// [Bit 28] L3 Performance Counter Extensions.
243 UINT32 PerfCtrExtL3
:1;
245 /// [Bit 29] MWAITX and MONITORX capability.
247 UINT32 MwaitExtended
:1;
249 /// [Bit 31:30] Reserved.
254 /// All bit fields as a 32-bit value
257 } CPUID_AMD_EXTENDED_CPU_SIG_ECX
;
260 CPUID Extended Processor Signature and Features EDX for CPUID leaf
261 #CPUID_EXTENDED_CPU_SIG.
265 /// Individual bit fields
269 /// [Bit 0] x87 floating point unit on-chip.
273 /// [Bit 1] Virtual-mode enhancements.
277 /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
281 /// [Bit 3] Page-size extensions (4 MB pages).
285 /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
289 /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
293 /// [Bit 6] Physical-address extensions (PAE).
297 /// [Bit 7] Machine check exception, CR4.MCE.
301 /// [Bit 8] CMPXCHG8B instruction.
305 /// [Bit 9] APIC exists and is enabled.
309 /// [Bit 10] Reserved.
313 /// [Bit 11] SYSCALL and SYSRET instructions.
315 UINT32 SYSCALL_SYSRET
:1;
317 /// [Bit 12] Memory-type range registers.
321 /// [Bit 13] Page global extension, CR4.PGE.
325 /// [Bit 14] Machine check architecture, MCG_CAP.
329 /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
333 /// [Bit 16] Page attribute table.
337 /// [Bit 17] Page-size extensions.
341 /// [Bit 19:18] Reserved.
345 /// [Bit 20] No-execute page protection.
349 /// [Bit 21] Reserved.
353 /// [Bit 22] AMD Extensions to MMX instructions.
357 /// [Bit 23] MMX instructions.
361 /// [Bit 24] FXSAVE and FXRSTOR instructions.
365 /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
369 /// [Bit 26] 1-GByte large page support.
373 /// [Bit 27] RDTSCP intructions.
377 /// [Bit 28] Reserved.
381 /// [Bit 29] Long Mode.
385 /// [Bit 30] 3DNow! instructions.
389 /// [Bit 31] AMD Extensions to 3DNow! instructions.
391 UINT32 ThreeDNowExt
:1;
394 /// All bit fields as a 32-bit value
397 } CPUID_AMD_EXTENDED_CPU_SIG_EDX
;
401 CPUID Linear Physical Address Size
403 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
405 @retval EAX Linear/Physical Address Size described by the type
406 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
407 @retval EBX Linear/Physical Address Size described by the type
408 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
409 @retval ECX Linear/Physical Address Size described by the type
410 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
411 @retval EDX Reserved.
415 CPUID Linear Physical Address Size EAX for CPUID leaf
416 #CPUID_VIR_PHY_ADDRESS_SIZE.
420 /// Individual bit fields
424 /// [Bits 7:0] Maximum physical byte address size in bits.
426 UINT32 PhysicalAddressBits
:8;
428 /// [Bits 15:8] Maximum linear byte address size in bits.
430 UINT32 LinearAddressBits
:8;
432 /// [Bits 23:16] Maximum guest physical byte address size in bits.
434 UINT32 GuestPhysAddrSize
:8;
436 /// [Bit 31:24] Reserved.
441 /// All bit fields as a 32-bit value
444 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX
;
447 CPUID Linear Physical Address Size EBX for CPUID leaf
448 #CPUID_VIR_PHY_ADDRESS_SIZE.
452 /// Individual bit fields
456 /// [Bits 0] Clear Zero Instruction.
460 /// [Bits 1] Instructions retired count support.
464 /// [Bits 2] Restore error pointers for XSave instructions.
468 /// [Bit 31:3] Reserved.
473 /// All bit fields as a 32-bit value
476 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
;
479 CPUID Linear Physical Address Size ECX for CPUID leaf
480 #CPUID_VIR_PHY_ADDRESS_SIZE.
484 /// Individual bit fields
488 /// [Bits 7:0] Number of threads - 1.
492 /// [Bit 11:8] Reserved.
496 /// [Bits 15:12] APIC ID size.
498 UINT32 ApicIdCoreIdSize
:4;
500 /// [Bits 17:16] Performance time-stamp counter size.
502 UINT32 PerfTscSize
:2;
504 /// [Bit 31:18] Reserved.
509 /// All bit fields as a 32-bit value
512 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
;
516 CPUID AMD Processor Topology
518 @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
520 @retval EAX Extended APIC ID described by the type
521 CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
522 @retval EBX Core Indentifiers described by the type
523 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
524 @retval ECX Node Indentifiers described by the type
525 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
526 @retval EDX Reserved.
528 #define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E
531 CPUID AMD Processor Topology EAX for CPUID leaf
532 #CPUID_AMD_PROCESSOR_TOPOLOGY.
536 /// Individual bit fields
540 /// [Bit 31:0] Extended APIC Id.
542 UINT32 ExtendedApicId
;
545 /// All bit fields as a 32-bit value
548 } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX
;
551 CPUID AMD Processor Topology EBX for CPUID leaf
552 #CPUID_AMD_PROCESSOR_TOPOLOGY.
556 /// Individual bit fields
560 /// [Bits 7:0] Core Id.
564 /// [Bits 15:8] Threads per core.
566 UINT32 ThreadsPerCore
:8;
568 /// [Bit 31:16] Reserved.
573 /// All bit fields as a 32-bit value
576 } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX
;
579 CPUID AMD Processor Topology ECX for CPUID leaf
580 #CPUID_AMD_PROCESSOR_TOPOLOGY.
584 /// Individual bit fields
588 /// [Bits 7:0] Node Id.
592 /// [Bits 10:8] Nodes per processor.
594 UINT32 NodesPerProcessor
:3;
596 /// [Bit 31:11] Reserved.
601 /// All bit fields as a 32-bit value
604 } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX
;
608 CPUID Memory Encryption Information
610 @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
612 @retval EAX Returns the memory encryption feature support status.
613 @retval EBX If memory encryption feature is present then return
614 the page table bit number used to enable memory encryption support
615 and reducing of physical address space in bits.
616 @retval ECX Returns number of encrypted guest supported simultaneously.
617 @retval EDX Returns minimum SEV enabled and SEV disabled ASID.
626 AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);
630 #define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F
633 CPUID Memory Encryption support information EAX for CPUID leaf
634 #CPUID_MEMORY_ENCRYPTION_INFO.
638 /// Individual bit fields
642 /// [Bit 0] Secure Memory Encryption (Sme) Support
647 /// [Bit 1] Secure Encrypted Virtualization (Sev) Support
652 /// [Bit 2] Page flush MSR support
654 UINT32 PageFlushMsrBit
:1;
657 /// [Bit 3] Encrypted state support
662 /// [Bit 31:4] Reserved
664 UINT32 ReservedBits
:28;
667 /// All bit fields as a 32-bit value
670 } CPUID_MEMORY_ENCRYPTION_INFO_EAX
;
673 CPUID Memory Encryption support information EBX for CPUID leaf
674 #CPUID_MEMORY_ENCRYPTION_INFO.
678 /// Individual bit fields
682 /// [Bit 5:0] Page table bit number used to enable memory encryption
687 /// [Bit 11:6] Reduction of system physical address space bits when
688 /// memory encryption is enabled
690 UINT32 ReducedPhysBits
:5;
693 /// [Bit 31:12] Reserved
695 UINT32 ReservedBits
:21;
698 /// All bit fields as a 32-bit value
701 } CPUID_MEMORY_ENCRYPTION_INFO_EBX
;
704 CPUID Memory Encryption support information ECX for CPUID leaf
705 #CPUID_MEMORY_ENCRYPTION_INFO.
709 /// Individual bit fields
713 /// [Bit 31:0] Number of encrypted guest supported simultaneously
718 /// All bit fields as a 32-bit value
721 } CPUID_MEMORY_ENCRYPTION_INFO_ECX
;
724 CPUID Memory Encryption support information EDX for CPUID leaf
725 #CPUID_MEMORY_ENCRYPTION_INFO.
729 /// Individual bit fields
733 /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
738 /// All bit fields as a 32-bit value
741 } CPUID_MEMORY_ENCRYPTION_INFO_EDX
;