2 MSR Definitions for the Intel(R) Atom(TM) Processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3.
24 #ifndef __ATOM_MSR_H__
25 #define __ATOM_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Shared. Model Specific Platform ID (R).
32 @param ECX MSR_ATOM_PLATFORM_ID (0x00000017)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
40 MSR_ATOM_PLATFORM_ID_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
44 @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
46 #define MSR_ATOM_PLATFORM_ID 0x00000017
49 MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
53 /// Individual bit fields
58 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
60 UINT32 MaximumQualifiedRatio
:5;
65 /// All bit fields as a 32-bit value
69 /// All bit fields as a 64-bit value
72 } MSR_ATOM_PLATFORM_ID_REGISTER
;
76 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
77 processor features; (R) indicates current processor configuration.
79 @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)
80 @param EAX Lower 32-bits of MSR value.
81 Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
82 @param EDX Upper 32-bits of MSR value.
83 Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
87 MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;
89 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
90 AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
92 @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
94 #define MSR_ATOM_EBL_CR_POWERON 0x0000002A
97 MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
101 /// Individual bit fields
106 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
109 UINT32 DataErrorCheckingEnable
:1;
111 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
114 UINT32 ResponseErrorCheckingEnable
:1;
116 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
118 UINT32 AERR_DriveEnable
:1;
120 /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
121 /// Disabled Always 0.
123 UINT32 BERR_Enable
:1;
127 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
129 UINT32 BINIT_DriverEnable
:1;
132 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
134 UINT32 ExecuteBIST
:1;
136 /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
139 UINT32 AERR_ObservationEnabled
:1;
142 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
145 UINT32 BINIT_ObservationEnabled
:1;
148 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
150 UINT32 ResetVector
:1;
153 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
155 UINT32 APICClusterID
:2;
158 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
160 UINT32 SymmetricArbitrationID
:2;
162 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
164 UINT32 IntegerBusFrequencyRatio
:5;
166 UINT32 Reserved10
:32;
169 /// All bit fields as a 32-bit value
173 /// All bit fields as a 64-bit value
176 } MSR_ATOM_EBL_CR_POWERON_REGISTER
;
180 Unique. Last Branch Record 0 From IP (R/W) One of eight pairs of last branch
181 record registers on the last branch record stack. This part of the stack
182 contains pointers to the source instruction for one of the last eight
183 branches, exceptions, or interrupts taken by the processor. See also: -
184 Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
185 Interrupt, and Exception Recording (Pentium M Processors).".
187 @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
188 @param EAX Lower 32-bits of MSR value.
189 @param EDX Upper 32-bits of MSR value.
195 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
196 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
198 @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
199 MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
200 MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
201 MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
202 MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
203 MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
204 MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
205 MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
208 #define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
209 #define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
210 #define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
211 #define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
212 #define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
213 #define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
214 #define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
215 #define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
220 Unique. Last Branch Record 0 To IP (R/W) One of eight pairs of last branch
221 record registers on the last branch record stack. This part of the stack
222 contains pointers to the destination instruction for one of the last eight
223 branches, exceptions, or interrupts taken by the processor.
225 @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
226 @param EAX Lower 32-bits of MSR value.
227 @param EDX Upper 32-bits of MSR value.
233 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
234 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
236 @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
237 MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
238 MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
239 MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
240 MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
241 MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
242 MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
243 MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
246 #define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
247 #define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
248 #define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
249 #define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
250 #define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
251 #define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
252 #define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
253 #define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
258 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
259 bus clock speed for processors based on Intel Atom microarchitecture:.
261 @param ECX MSR_ATOM_FSB_FREQ (0x000000CD)
262 @param EAX Lower 32-bits of MSR value.
263 Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
264 @param EDX Upper 32-bits of MSR value.
265 Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
269 MSR_ATOM_FSB_FREQ_REGISTER Msr;
271 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
273 @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
275 #define MSR_ATOM_FSB_FREQ 0x000000CD
278 MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
282 /// Individual bit fields
286 /// [Bits 2:0] - Scalable Bus Speed
288 /// Atom Processor Family
289 /// ---------------------
290 /// 111B: 083 MHz (FSB 333)
291 /// 101B: 100 MHz (FSB 400)
292 /// 001B: 133 MHz (FSB 533)
293 /// 011B: 167 MHz (FSB 667)
295 /// 133.33 MHz should be utilized if performing calculation with
296 /// System Bus Speed when encoding is 001B.
297 /// 166.67 MHz should be utilized if performing calculation with
298 /// System Bus Speed when
299 /// encoding is 011B.
301 UINT32 ScalableBusSpeed
:3;
306 /// All bit fields as a 32-bit value
310 /// All bit fields as a 64-bit value
313 } MSR_ATOM_FSB_FREQ_REGISTER
;
319 @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
320 @param EAX Lower 32-bits of MSR value.
321 Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
322 @param EDX Upper 32-bits of MSR value.
323 Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
327 MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;
329 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
330 AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
332 @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
334 #define MSR_ATOM_BBL_CR_CTL3 0x0000011E
337 MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
341 /// Individual bit fields
345 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
346 /// Indicates if the L2 is hardware-disabled.
348 UINT32 L2HardwareEnabled
:1;
351 /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
352 /// Disabled (default) Until this bit is set the processor will not
353 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
358 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
360 UINT32 L2NotPresent
:1;
365 /// All bit fields as a 32-bit value
369 /// All bit fields as a 64-bit value
372 } MSR_ATOM_BBL_CR_CTL3_REGISTER
;
378 @param ECX MSR_ATOM_PERF_STATUS (0x00000198)
379 @param EAX Lower 32-bits of MSR value.
380 Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
381 @param EDX Upper 32-bits of MSR value.
382 Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
386 MSR_ATOM_PERF_STATUS_REGISTER Msr;
388 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
389 AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
391 @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
393 #define MSR_ATOM_PERF_STATUS 0x00000198
396 MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
400 /// Individual bit fields
404 /// [Bits 15:0] Current Performance State Value.
406 UINT32 CurrentPerformanceStateValue
:16;
410 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
411 /// configured for the processor.
413 UINT32 MaximumBusRatio
:5;
417 /// All bit fields as a 64-bit value
420 } MSR_ATOM_PERF_STATUS_REGISTER
;
426 @param ECX MSR_ATOM_THERM2_CTL (0x0000019D)
427 @param EAX Lower 32-bits of MSR value.
428 Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
429 @param EDX Upper 32-bits of MSR value.
430 Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
434 MSR_ATOM_THERM2_CTL_REGISTER Msr;
436 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
437 AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
439 @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
441 #define MSR_ATOM_THERM2_CTL 0x0000019D
444 MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
448 /// Individual bit fields
453 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
454 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
455 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
456 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
457 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
464 /// All bit fields as a 32-bit value
468 /// All bit fields as a 64-bit value
471 } MSR_ATOM_THERM2_CTL_REGISTER
;
475 Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor
476 functions to be enabled and disabled.
478 @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
479 @param EAX Lower 32-bits of MSR value.
480 Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
481 @param EDX Upper 32-bits of MSR value.
482 Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
486 MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;
488 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
489 AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
491 @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
493 #define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
496 MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
500 /// Individual bit fields
504 /// [Bit 0] Fast-Strings Enable See Table 35-2.
506 UINT32 FastStrings
:1;
509 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
512 UINT32 AutomaticThermalControlCircuit
:1;
515 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
517 UINT32 PerformanceMonitoring
:1;
521 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
522 /// the processor to indicate a pending break event within the processor 0
523 /// = Indicates compatible FERR# signaling behavior This bit must be set
524 /// to 1 to support XAPIC interrupt model usage.
528 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
532 /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See
537 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
538 /// thermal sensor indicates that the die temperature is at the
539 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
540 /// TM2 will reduce the bus to core ratio and voltage according to the
541 /// value last written to MSR_THERM2_CTL bits 15:0.
542 /// When this bit is clear (0, default), the processor does not change
543 /// the VID signals or the bus to core ratio when the processor enters a
544 /// thermally managed state. The BIOS must enable this feature if the
545 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
546 /// not set, this feature is not supported and BIOS must not alter the
547 /// contents of the TM2 bit location. The processor is operating out of
548 /// specification if both this bit and the TM1 bit are set to 0.
553 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
559 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
564 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
565 /// (R/WO) When set, this bit causes the following bits to become
566 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
567 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
568 /// be set before an Enhanced Intel SpeedStep Technology transition is
569 /// requested. This bit is cleared on reset.
574 /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 35-2.
576 UINT32 LimitCpuidMaxval
:1;
578 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
580 UINT32 xTPR_Message_Disable
:1;
584 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
587 UINT32 Reserved11
:29;
590 /// All bit fields as a 64-bit value
593 } MSR_ATOM_IA32_MISC_ENABLE_REGISTER
;
597 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)
598 that points to the MSR containing the most recent branch record. See
599 MSR_LASTBRANCH_0_FROM_IP (at 40H).
601 @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
602 @param EAX Lower 32-bits of MSR value.
603 @param EDX Upper 32-bits of MSR value.
609 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
610 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
612 @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
614 #define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
618 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
619 last branch instruction that the processor executed prior to the last
620 exception that was generated or the last interrupt that was handled.
622 @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)
623 @param EAX Lower 32-bits of MSR value.
624 @param EDX Upper 32-bits of MSR value.
630 Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
632 @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
634 #define MSR_ATOM_LER_FROM_LIP 0x000001DD
638 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
639 to the target of the last branch instruction that the processor executed
640 prior to the last exception that was generated or the last interrupt that
643 @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)
644 @param EAX Lower 32-bits of MSR value.
645 @param EDX Upper 32-bits of MSR value.
651 Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
653 @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
655 #define MSR_ATOM_LER_TO_LIP 0x000001DE
659 Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control
662 @param ECX MSR_ATOM_IA32_PERF_GLOBAL_STAUS (0x0000038E)
663 @param EAX Lower 32-bits of MSR value.
664 @param EDX Upper 32-bits of MSR value.
670 Msr = AsmReadMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS);
671 AsmWriteMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS, Msr);
673 @note MSR_ATOM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
675 #define MSR_ATOM_IA32_PERF_GLOBAL_STAUS 0x0000038E
679 Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
682 @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
683 @param EAX Lower 32-bits of MSR value.
684 Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
685 @param EDX Upper 32-bits of MSR value.
686 Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
690 MSR_ATOM_PEBS_ENABLE_REGISTER Msr;
692 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
693 AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
695 @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
697 #define MSR_ATOM_PEBS_ENABLE 0x000003F1
700 MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
704 /// Individual bit fields
708 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
715 /// All bit fields as a 32-bit value
719 /// All bit fields as a 64-bit value
722 } MSR_ATOM_PEBS_ENABLE_REGISTER
;
726 Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
728 @param ECX MSR_ATOM_MC3_CTL (0x0000040C)
729 @param EAX Lower 32-bits of MSR value.
730 @param EDX Upper 32-bits of MSR value.
736 Msr = AsmReadMsr64 (MSR_ATOM_MC3_CTL);
737 AsmWriteMsr64 (MSR_ATOM_MC3_CTL, Msr);
739 @note MSR_ATOM_MC3_CTL is defined as MSR_MC3_CTL in SDM.
741 #define MSR_ATOM_MC3_CTL 0x0000040C
745 Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
747 @param ECX MSR_ATOM_MC3_STATUS (0x0000040D)
748 @param EAX Lower 32-bits of MSR value.
749 @param EDX Upper 32-bits of MSR value.
755 Msr = AsmReadMsr64 (MSR_ATOM_MC3_STATUS);
756 AsmWriteMsr64 (MSR_ATOM_MC3_STATUS, Msr);
758 @note MSR_ATOM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
760 #define MSR_ATOM_MC3_STATUS 0x0000040D
764 Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
765 register is either not implemented or contains no address if the ADDRV flag
766 in the MSR_MC3_STATUS register is clear. When not implemented in the
767 processor, all reads and writes to this MSR will cause a general-protection
770 @param ECX MSR_ATOM_MC3_ADDR (0x0000040E)
771 @param EAX Lower 32-bits of MSR value.
772 @param EDX Upper 32-bits of MSR value.
778 Msr = AsmReadMsr64 (MSR_ATOM_MC3_ADDR);
779 AsmWriteMsr64 (MSR_ATOM_MC3_ADDR, Msr);
781 @note MSR_ATOM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
783 #define MSR_ATOM_MC3_ADDR 0x0000040E
787 Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
789 @param ECX MSR_ATOM_MC4_CTL (0x00000410)
790 @param EAX Lower 32-bits of MSR value.
791 @param EDX Upper 32-bits of MSR value.
797 Msr = AsmReadMsr64 (MSR_ATOM_MC4_CTL);
798 AsmWriteMsr64 (MSR_ATOM_MC4_CTL, Msr);
800 @note MSR_ATOM_MC4_CTL is defined as MSR_MC4_CTL in SDM.
802 #define MSR_ATOM_MC4_CTL 0x00000410
806 Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
808 @param ECX MSR_ATOM_MC4_STATUS (0x00000411)
809 @param EAX Lower 32-bits of MSR value.
810 @param EDX Upper 32-bits of MSR value.
816 Msr = AsmReadMsr64 (MSR_ATOM_MC4_STATUS);
817 AsmWriteMsr64 (MSR_ATOM_MC4_STATUS, Msr);
819 @note MSR_ATOM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
821 #define MSR_ATOM_MC4_STATUS 0x00000411
825 Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
826 register is either not implemented or contains no address if the ADDRV flag
827 in the MSR_MC4_STATUS register is clear. When not implemented in the
828 processor, all reads and writes to this MSR will cause a general-protection
831 @param ECX MSR_ATOM_MC4_ADDR (0x00000412)
832 @param EAX Lower 32-bits of MSR value.
833 @param EDX Upper 32-bits of MSR value.
839 Msr = AsmReadMsr64 (MSR_ATOM_MC4_ADDR);
840 AsmWriteMsr64 (MSR_ATOM_MC4_ADDR, Msr);
842 @note MSR_ATOM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
844 #define MSR_ATOM_MC4_ADDR 0x00000412
848 Package. Package C2 Residency Note: C-state values are processor specific
849 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
850 C-States. Package. Package C2 Residency Counter. (R/O) Time that this
851 package is in processor-specific C2 states since last reset. Counts at 1 Mhz
854 @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
855 @param EAX Lower 32-bits of MSR value.
856 @param EDX Upper 32-bits of MSR value.
862 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
863 AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
865 @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
867 #define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
871 Package. Package C4 Residency Note: C-state values are processor specific
872 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
873 C-States. Package. Package C4 Residency Counter. (R/O) Time that this
874 package is in processor-specific C4 states since last reset. Counts at 1 Mhz
877 @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
878 @param EAX Lower 32-bits of MSR value.
879 @param EDX Upper 32-bits of MSR value.
885 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
886 AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
888 @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
890 #define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
894 Package. Package C6 Residency Note: C-state values are processor specific
895 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
896 C-States. Package. Package C6 Residency Counter. (R/O) Time that this
897 package is in processor-specific C6 states since last reset. Counts at 1 Mhz
900 @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
901 @param EAX Lower 32-bits of MSR value.
902 @param EDX Upper 32-bits of MSR value.
908 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
909 AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
911 @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
913 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA