2 MSR Definitions for Intel processors based on the Haswell-E microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __HASWELL_E_MSR_H__
25 #define __HASWELL_E_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Haswell-E microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x3F \
46 Package. Configured State of Enabled Processor Core Count and Logical
47 Processor Count (RO) - After a Power-On RESET, enumerates factory
48 configuration of the number of processor cores and logical processors in the
49 physical package. - Following the sequence of (i) BIOS modified a
50 Configuration Mask which selects a subset of processor cores to be active
51 post RESET and (ii) a RESET event after the modification, enumerates the
52 current configuration of enabled processor core count and logical processor
53 count in the physical package.
55 @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
56 @param EAX Lower 32-bits of MSR value.
57 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
58 @param EDX Upper 32-bits of MSR value.
59 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
63 MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;
65 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);
67 @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.
69 #define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035
72 MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT
76 /// Individual bit fields
80 /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are
81 /// currently enabled (by either factory configuration or BIOS
82 /// configuration) in the physical package.
86 /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that
87 /// are currently enabled (by either factory configuration or BIOS
88 /// configuration) in the physical package.
90 UINT32 Thread_Count
:16;
94 /// All bit fields as a 32-bit value
98 /// All bit fields as a 64-bit value
101 } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
;
105 Thread. A Hardware Assigned ID for the Logical Processor (RO).
107 @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
108 @param EAX Lower 32-bits of MSR value.
109 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
110 @param EDX Upper 32-bits of MSR value.
111 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
115 MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;
117 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);
119 @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.
121 #define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053
124 MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO
128 /// Individual bit fields
132 /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific
133 /// numerical. value physically assigned to each logical processor. This
134 /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within
135 /// a physical package.
137 UINT32 Logical_Processor_ID
:8;
142 /// All bit fields as a 32-bit value
146 /// All bit fields as a 64-bit value
149 } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
;
153 Core. C-State Configuration Control (R/W) Note: C-state values are processor
154 specific C-state code names, unrelated to MWAIT extension C-state parameters
155 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
157 @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
158 @param EAX Lower 32-bits of MSR value.
159 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
160 @param EDX Upper 32-bits of MSR value.
161 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
165 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
167 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
168 AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
170 @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
172 #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2
175 MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
179 /// Individual bit fields
183 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
184 /// processor-specific C-state code name (consuming the least power) for
185 /// the package. The default is set as factory-configured package C-state
186 /// limit. The following C-state code name encodings are supported: 000b:
187 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
188 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
189 /// supported by the processor are available.
194 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
199 /// [Bit 15] CFG Lock (R/WO).
204 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
206 UINT32 C3AutoDemotion
:1;
208 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
210 UINT32 C1AutoDemotion
:1;
212 /// [Bit 27] Enable C3 Undemotion (R/W).
214 UINT32 C3Undemotion
:1;
216 /// [Bit 28] Enable C1 Undemotion (R/W).
218 UINT32 C1Undemotion
:1;
220 /// [Bit 29] Package C State Demotion Enable (R/W).
222 UINT32 CStateDemotion
:1;
224 /// [Bit 30] Package C State UnDemotion Enable (R/W).
226 UINT32 CStateUndemotion
:1;
231 /// All bit fields as a 32-bit value
235 /// All bit fields as a 64-bit value
238 } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER
;
242 Thread. Global Machine Check Capability (R/O).
244 @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
245 @param EAX Lower 32-bits of MSR value.
246 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
247 @param EDX Upper 32-bits of MSR value.
248 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
252 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;
254 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
256 @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
258 #define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179
261 MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
265 /// Individual bit fields
269 /// [Bits 7:0] Count.
273 /// [Bit 8] MCG_CTL_P.
277 /// [Bit 9] MCG_EXT_P.
281 /// [Bit 10] MCP_CMCI_P.
285 /// [Bit 11] MCG_TES_P.
290 /// [Bits 23:16] MCG_EXT_CNT.
292 UINT32 MCG_EXT_CNT
:8;
294 /// [Bit 24] MCG_SER_P.
298 /// [Bit 25] MCG_EM_P.
302 /// [Bit 26] MCG_ELOG_P.
309 /// All bit fields as a 32-bit value
313 /// All bit fields as a 64-bit value
316 } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER
;
320 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
321 Enhancement. Accessible only while in SMM.
323 @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
324 @param EAX Lower 32-bits of MSR value.
325 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
326 @param EDX Upper 32-bits of MSR value.
327 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
331 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;
333 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
334 AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
336 @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
338 #define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D
341 MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
345 /// Individual bit fields
351 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
352 /// SMM code access restriction is supported and a host-space interface
353 /// available to SMM handler.
355 UINT32 SMM_Code_Access_Chk
:1;
357 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
358 /// SMM long flow indicator is supported and a host-space interface
359 /// available to SMM handler.
361 UINT32 Long_Flow_Indication
:1;
365 /// All bit fields as a 64-bit value
368 } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER
;
372 Package. MC Bank Error Configuration (R/W).
374 @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
375 @param EAX Lower 32-bits of MSR value.
376 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
377 @param EDX Upper 32-bits of MSR value.
378 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
382 MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;
384 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
385 AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
387 @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
389 #define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F
392 MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
396 /// Individual bit fields
401 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
402 /// to log additional info in bits 36:32.
404 UINT32 MemErrorLogEnable
:1;
409 /// All bit fields as a 32-bit value
413 /// All bit fields as a 64-bit value
416 } MSR_HASWELL_E_ERROR_CONTROL_REGISTER
;
420 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
421 RW if MSR_PLATFORM_INFO.[28] = 1.
423 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
424 @param EAX Lower 32-bits of MSR value.
425 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
426 @param EDX Upper 32-bits of MSR value.
427 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
431 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;
433 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
435 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
437 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD
440 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
444 /// Individual bit fields
448 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
449 /// limit of 1 core active.
453 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
454 /// limit of 2 core active.
458 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
459 /// limit of 3 core active.
463 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
464 /// limit of 4 core active.
468 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
469 /// limit of 5 core active.
473 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
474 /// limit of 6 core active.
478 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
479 /// limit of 7 core active.
483 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
484 /// limit of 8 core active.
489 /// All bit fields as a 64-bit value
492 } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER
;
496 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
497 RW if MSR_PLATFORM_INFO.[28] = 1.
499 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
500 @param EAX Lower 32-bits of MSR value.
501 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
502 @param EDX Upper 32-bits of MSR value.
503 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
507 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;
509 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
511 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
513 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE
516 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
520 /// Individual bit fields
524 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
525 /// limit of 9 core active.
529 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
530 /// limit of 10 core active.
534 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
535 /// limit of 11 core active.
539 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
540 /// limit of 12 core active.
544 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
545 /// limit of 13 core active.
549 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
550 /// limit of 14 core active.
554 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
555 /// limit of 15 core active.
559 /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
560 /// limit of 16 core active.
565 /// All bit fields as a 64-bit value
568 } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER
;
572 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
573 RW if MSR_PLATFORM_INFO.[28] = 1.
575 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
576 @param EAX Lower 32-bits of MSR value.
577 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
578 @param EDX Upper 32-bits of MSR value.
579 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
583 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;
585 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
587 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
589 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF
592 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
596 /// Individual bit fields
600 /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
601 /// limit of 17 core active.
605 /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
606 /// limit of 18 core active.
612 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
613 /// the processor uses override configuration specified in
614 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
615 /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
616 /// configuration (Default).
618 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
621 /// All bit fields as a 64-bit value
624 } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
;
628 Package. Unit Multipliers used in RAPL Interfaces (R/O).
630 @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
631 @param EAX Lower 32-bits of MSR value.
632 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
633 @param EDX Upper 32-bits of MSR value.
634 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
638 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;
640 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
642 @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
644 #define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606
647 MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
651 /// Individual bit fields
655 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
660 /// [Bits 12:8] Package. Energy Status Units Energy related information
661 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
662 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
665 UINT32 EnergyStatusUnits
:5;
668 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
676 /// All bit fields as a 32-bit value
680 /// All bit fields as a 64-bit value
683 } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER
;
687 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
690 @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
691 @param EAX Lower 32-bits of MSR value.
692 @param EDX Upper 32-bits of MSR value.
698 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
699 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
701 @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
703 #define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618
707 Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.
709 @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
710 @param EAX Lower 32-bits of MSR value.
711 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
712 @param EDX Upper 32-bits of MSR value.
713 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
717 MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;
719 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
721 @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
723 #define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619
726 MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS
730 /// Individual bit fields
734 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
735 /// to enable DRAM RAPL mode 0 (Direct VR).
741 /// All bit fields as a 32-bit value
745 /// All bit fields as a 64-bit value
748 } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER
;
752 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
755 @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
756 @param EAX Lower 32-bits of MSR value.
757 @param EDX Upper 32-bits of MSR value.
763 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
765 @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
767 #define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B
771 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
773 @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
774 @param EAX Lower 32-bits of MSR value.
775 @param EDX Upper 32-bits of MSR value.
781 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
782 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
784 @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
786 #define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C
790 Package. Configuration of PCIE PLL Relative to BCLK(R/W).
792 @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
793 @param EAX Lower 32-bits of MSR value.
794 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
795 @param EDX Upper 32-bits of MSR value.
796 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
800 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;
802 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);
803 AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);
805 @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.
807 #define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E
810 MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO
814 /// Individual bit fields
818 /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz
819 /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use
820 /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz
825 /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of
830 /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out
831 /// before re-locking Gen2/Gen3 PLLs.
838 /// All bit fields as a 32-bit value
842 /// All bit fields as a 64-bit value
845 } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
;
849 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
850 fields represent the widest possible range of uncore frequencies. Writing to
851 these fields allows software to control the minimum and the maximum
852 frequency that hardware will select.
854 @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
855 @param EAX Lower 32-bits of MSR value.
856 Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
857 @param EDX Upper 32-bits of MSR value.
858 Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
862 MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
864 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
865 AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
868 #define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620
871 MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
875 /// Individual bit fields
879 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
885 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
886 /// possible ratio of the LLC/Ring.
893 /// All bit fields as a 32-bit value
897 /// All bit fields as a 64-bit value
900 } MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER
;
903 Package. Reserved (R/O) Reads return 0.
905 @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
906 @param EAX Lower 32-bits of MSR value.
907 @param EDX Upper 32-bits of MSR value.
913 Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);
915 @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
917 #define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639
921 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
922 refers to processor core frequency).
924 @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
925 @param EAX Lower 32-bits of MSR value.
926 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
927 @param EDX Upper 32-bits of MSR value.
928 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
932 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
934 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
935 AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
937 @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
939 #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690
942 MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
946 /// Individual bit fields
950 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
951 /// reduced below the operating system request due to assertion of
952 /// external PROCHOT.
954 UINT32 PROCHOT_Status
:1;
956 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
957 /// operating system request due to a thermal event.
959 UINT32 ThermalStatus
:1;
961 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
962 /// reduced below the operating system request due to PBM limit.
964 UINT32 PowerBudgetManagementStatus
:1;
966 /// [Bit 3] Platform Configuration Services Status (R0) When set,
967 /// frequency is reduced below the operating system request due to PCS
970 UINT32 PlatformConfigurationServicesStatus
:1;
973 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
974 /// When set, frequency is reduced below the operating system request
975 /// because the processor has detected that utilization is low.
977 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
979 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
980 /// below the operating system request due to a thermal alert from the
981 /// Voltage Regulator.
983 UINT32 VRThermAlertStatus
:1;
986 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
987 /// reduced below the operating system request due to electrical design
988 /// point constraints (e.g. maximum electrical current consumption).
990 UINT32 ElectricalDesignPointStatus
:1;
993 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
994 /// below the operating system request due to Multi-Core Turbo limits.
996 UINT32 MultiCoreTurboStatus
:1;
999 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
1000 /// below max non-turbo P1.
1002 UINT32 FrequencyP1Status
:1;
1004 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
1005 /// set, frequency is reduced below max n-core turbo frequency.
1007 UINT32 TurboFrequencyLimitingStatus
:1;
1009 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
1010 /// reduced below the operating system request.
1012 UINT32 FrequencyLimitingStatus
:1;
1014 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1015 /// has asserted since the log bit was last cleared. This log bit will
1016 /// remain set until cleared by software writing 0.
1018 UINT32 PROCHOT_Log
:1;
1020 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1021 /// has asserted since the log bit was last cleared. This log bit will
1022 /// remain set until cleared by software writing 0.
1024 UINT32 ThermalLog
:1;
1026 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
1027 /// Status bit has asserted since the log bit was last cleared. This log
1028 /// bit will remain set until cleared by software writing 0.
1030 UINT32 PowerBudgetManagementLog
:1;
1032 /// [Bit 19] Platform Configuration Services Log When set, indicates that
1033 /// the PCS Status bit has asserted since the log bit was last cleared.
1034 /// This log bit will remain set until cleared by software writing 0.
1036 UINT32 PlatformConfigurationServicesLog
:1;
1039 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1040 /// indicates that the AUBFC Status bit has asserted since the log bit was
1041 /// last cleared. This log bit will remain set until cleared by software
1044 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
1046 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1047 /// Alert Status bit has asserted since the log bit was last cleared. This
1048 /// log bit will remain set until cleared by software writing 0.
1050 UINT32 VRThermAlertLog
:1;
1053 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1054 /// Status bit has asserted since the log bit was last cleared. This log
1055 /// bit will remain set until cleared by software writing 0.
1057 UINT32 ElectricalDesignPointLog
:1;
1060 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
1061 /// Turbo Status bit has asserted since the log bit was last cleared. This
1062 /// log bit will remain set until cleared by software writing 0.
1064 UINT32 MultiCoreTurboLog
:1;
1067 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
1068 /// Frequency P1 Status bit has asserted since the log bit was last
1069 /// cleared. This log bit will remain set until cleared by software
1072 UINT32 CoreFrequencyP1Log
:1;
1074 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
1075 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
1076 /// has asserted since the log bit was last cleared. This log bit will
1077 /// remain set until cleared by software writing 0.
1079 UINT32 TurboFrequencyLimitingLog
:1;
1081 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
1082 /// Frequency Limiting Status bit has asserted since the log bit was last
1083 /// cleared. This log bit will remain set until cleared by software
1086 UINT32 CoreFrequencyLimitingLog
:1;
1087 UINT32 Reserved9
:32;
1090 /// All bit fields as a 32-bit value
1094 /// All bit fields as a 64-bit value
1097 } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER
;
1101 THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
1102 ECX=0):EBX.RDT-M[bit 12] = 1.
1104 @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
1105 @param EAX Lower 32-bits of MSR value.
1106 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1107 @param EDX Upper 32-bits of MSR value.
1108 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1110 <b>Example usage</b>
1112 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;
1114 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
1115 AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
1117 @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
1119 #define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D
1122 MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
1126 /// Individual bit fields
1130 /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
1131 /// occupancy monitoring all other encoding reserved..
1134 UINT32 Reserved1
:24;
1136 /// [Bits 41:32] RMID (RW).
1139 UINT32 Reserved2
:22;
1142 /// All bit fields as a 64-bit value
1145 } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER
;
1149 THREAD. Resource Association Register (R/W)..
1151 @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
1152 @param EAX Lower 32-bits of MSR value.
1153 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1154 @param EDX Upper 32-bits of MSR value.
1155 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1157 <b>Example usage</b>
1159 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;
1161 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
1162 AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
1164 @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
1166 #define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F
1169 MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
1173 /// Individual bit fields
1177 /// [Bits 9:0] RMID.
1180 UINT32 Reserved1
:22;
1181 UINT32 Reserved2
:32;
1184 /// All bit fields as a 32-bit value
1188 /// All bit fields as a 64-bit value
1191 } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER
;
1195 Package. Uncore perfmon per-socket global control.
1197 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
1198 @param EAX Lower 32-bits of MSR value.
1199 @param EDX Upper 32-bits of MSR value.
1201 <b>Example usage</b>
1205 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
1206 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
1208 @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1210 #define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700
1214 Package. Uncore perfmon per-socket global status.
1216 @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
1217 @param EAX Lower 32-bits of MSR value.
1218 @param EDX Upper 32-bits of MSR value.
1220 <b>Example usage</b>
1224 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
1225 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
1227 @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1229 #define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701
1233 Package. Uncore perfmon per-socket global configuration.
1235 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
1236 @param EAX Lower 32-bits of MSR value.
1237 @param EDX Upper 32-bits of MSR value.
1239 <b>Example usage</b>
1243 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
1244 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
1246 @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1248 #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702
1252 Package. Uncore U-box UCLK fixed counter control.
1254 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
1255 @param EAX Lower 32-bits of MSR value.
1256 @param EDX Upper 32-bits of MSR value.
1258 <b>Example usage</b>
1262 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
1263 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
1265 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
1267 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703
1271 Package. Uncore U-box UCLK fixed counter.
1273 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
1274 @param EAX Lower 32-bits of MSR value.
1275 @param EDX Upper 32-bits of MSR value.
1277 <b>Example usage</b>
1281 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
1282 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
1284 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
1286 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704
1290 Package. Uncore U-box perfmon event select for U-box counter 0.
1292 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
1293 @param EAX Lower 32-bits of MSR value.
1294 @param EDX Upper 32-bits of MSR value.
1296 <b>Example usage</b>
1300 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
1301 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
1303 @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
1305 #define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705
1309 Package. Uncore U-box perfmon event select for U-box counter 1.
1311 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
1312 @param EAX Lower 32-bits of MSR value.
1313 @param EDX Upper 32-bits of MSR value.
1315 <b>Example usage</b>
1319 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
1320 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
1322 @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
1324 #define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706
1328 Package. Uncore U-box perfmon U-box wide status.
1330 @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
1331 @param EAX Lower 32-bits of MSR value.
1332 @param EDX Upper 32-bits of MSR value.
1334 <b>Example usage</b>
1338 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
1339 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
1341 @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1343 #define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708
1347 Package. Uncore U-box perfmon counter 0.
1349 @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
1350 @param EAX Lower 32-bits of MSR value.
1351 @param EDX Upper 32-bits of MSR value.
1353 <b>Example usage</b>
1357 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
1358 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
1360 @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
1362 #define MSR_HASWELL_E_U_PMON_CTR0 0x00000709
1366 Package. Uncore U-box perfmon counter 1.
1368 @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
1369 @param EAX Lower 32-bits of MSR value.
1370 @param EDX Upper 32-bits of MSR value.
1372 <b>Example usage</b>
1376 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
1377 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
1379 @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
1381 #define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A
1385 Package. Uncore PCU perfmon for PCU-box-wide control.
1387 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
1388 @param EAX Lower 32-bits of MSR value.
1389 @param EDX Upper 32-bits of MSR value.
1391 <b>Example usage</b>
1395 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
1396 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
1398 @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
1400 #define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710
1404 Package. Uncore PCU perfmon event select for PCU counter 0.
1406 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
1407 @param EAX Lower 32-bits of MSR value.
1408 @param EDX Upper 32-bits of MSR value.
1410 <b>Example usage</b>
1414 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
1415 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
1417 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
1419 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711
1423 Package. Uncore PCU perfmon event select for PCU counter 1.
1425 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
1426 @param EAX Lower 32-bits of MSR value.
1427 @param EDX Upper 32-bits of MSR value.
1429 <b>Example usage</b>
1433 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
1434 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
1436 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
1438 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712
1442 Package. Uncore PCU perfmon event select for PCU counter 2.
1444 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
1445 @param EAX Lower 32-bits of MSR value.
1446 @param EDX Upper 32-bits of MSR value.
1448 <b>Example usage</b>
1452 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
1453 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
1455 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
1457 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713
1461 Package. Uncore PCU perfmon event select for PCU counter 3.
1463 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
1464 @param EAX Lower 32-bits of MSR value.
1465 @param EDX Upper 32-bits of MSR value.
1467 <b>Example usage</b>
1471 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
1472 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
1474 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
1476 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714
1480 Package. Uncore PCU perfmon box-wide filter.
1482 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
1483 @param EAX Lower 32-bits of MSR value.
1484 @param EDX Upper 32-bits of MSR value.
1486 <b>Example usage</b>
1490 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
1491 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
1493 @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
1495 #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715
1499 Package. Uncore PCU perfmon box wide status.
1501 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
1502 @param EAX Lower 32-bits of MSR value.
1503 @param EDX Upper 32-bits of MSR value.
1505 <b>Example usage</b>
1509 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
1510 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
1512 @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1514 #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716
1518 Package. Uncore PCU perfmon counter 0.
1520 @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
1521 @param EAX Lower 32-bits of MSR value.
1522 @param EDX Upper 32-bits of MSR value.
1524 <b>Example usage</b>
1528 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
1529 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
1531 @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
1533 #define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717
1537 Package. Uncore PCU perfmon counter 1.
1539 @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
1540 @param EAX Lower 32-bits of MSR value.
1541 @param EDX Upper 32-bits of MSR value.
1543 <b>Example usage</b>
1547 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
1548 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
1550 @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
1552 #define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718
1556 Package. Uncore PCU perfmon counter 2.
1558 @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
1559 @param EAX Lower 32-bits of MSR value.
1560 @param EDX Upper 32-bits of MSR value.
1562 <b>Example usage</b>
1566 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
1567 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
1569 @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
1571 #define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719
1575 Package. Uncore PCU perfmon counter 3.
1577 @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
1578 @param EAX Lower 32-bits of MSR value.
1579 @param EDX Upper 32-bits of MSR value.
1581 <b>Example usage</b>
1585 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
1586 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
1588 @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
1590 #define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A
1594 Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
1596 @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
1597 @param EAX Lower 32-bits of MSR value.
1598 @param EDX Upper 32-bits of MSR value.
1600 <b>Example usage</b>
1604 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
1605 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
1607 @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
1609 #define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720
1613 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
1615 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
1616 @param EAX Lower 32-bits of MSR value.
1617 @param EDX Upper 32-bits of MSR value.
1619 <b>Example usage</b>
1623 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
1624 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
1626 @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
1628 #define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721
1632 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
1634 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
1635 @param EAX Lower 32-bits of MSR value.
1636 @param EDX Upper 32-bits of MSR value.
1638 <b>Example usage</b>
1642 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
1643 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
1645 @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
1647 #define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722
1651 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
1653 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
1654 @param EAX Lower 32-bits of MSR value.
1655 @param EDX Upper 32-bits of MSR value.
1657 <b>Example usage</b>
1661 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
1662 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
1664 @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
1666 #define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723
1670 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
1672 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
1673 @param EAX Lower 32-bits of MSR value.
1674 @param EDX Upper 32-bits of MSR value.
1676 <b>Example usage</b>
1680 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
1681 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
1683 @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
1685 #define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724
1689 Package. Uncore SBo 0 perfmon box-wide filter.
1691 @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
1692 @param EAX Lower 32-bits of MSR value.
1693 @param EDX Upper 32-bits of MSR value.
1695 <b>Example usage</b>
1699 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
1700 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
1702 @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
1704 #define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725
1708 Package. Uncore SBo 0 perfmon counter 0.
1710 @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
1711 @param EAX Lower 32-bits of MSR value.
1712 @param EDX Upper 32-bits of MSR value.
1714 <b>Example usage</b>
1718 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
1719 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
1721 @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
1723 #define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726
1727 Package. Uncore SBo 0 perfmon counter 1.
1729 @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
1730 @param EAX Lower 32-bits of MSR value.
1731 @param EDX Upper 32-bits of MSR value.
1733 <b>Example usage</b>
1737 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
1738 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
1740 @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
1742 #define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727
1746 Package. Uncore SBo 0 perfmon counter 2.
1748 @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
1749 @param EAX Lower 32-bits of MSR value.
1750 @param EDX Upper 32-bits of MSR value.
1752 <b>Example usage</b>
1756 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
1757 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
1759 @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
1761 #define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728
1765 Package. Uncore SBo 0 perfmon counter 3.
1767 @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
1768 @param EAX Lower 32-bits of MSR value.
1769 @param EDX Upper 32-bits of MSR value.
1771 <b>Example usage</b>
1775 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
1776 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
1778 @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
1780 #define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729
1784 Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
1786 @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
1787 @param EAX Lower 32-bits of MSR value.
1788 @param EDX Upper 32-bits of MSR value.
1790 <b>Example usage</b>
1794 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
1795 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
1797 @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
1799 #define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A
1803 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
1805 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
1806 @param EAX Lower 32-bits of MSR value.
1807 @param EDX Upper 32-bits of MSR value.
1809 <b>Example usage</b>
1813 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
1814 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
1816 @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
1818 #define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B
1822 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
1824 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
1825 @param EAX Lower 32-bits of MSR value.
1826 @param EDX Upper 32-bits of MSR value.
1828 <b>Example usage</b>
1832 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
1833 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
1835 @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
1837 #define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C
1841 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
1843 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
1844 @param EAX Lower 32-bits of MSR value.
1845 @param EDX Upper 32-bits of MSR value.
1847 <b>Example usage</b>
1851 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
1852 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
1854 @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
1856 #define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D
1860 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
1862 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
1863 @param EAX Lower 32-bits of MSR value.
1864 @param EDX Upper 32-bits of MSR value.
1866 <b>Example usage</b>
1870 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
1871 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
1873 @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
1875 #define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E
1879 Package. Uncore SBo 1 perfmon box-wide filter.
1881 @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
1882 @param EAX Lower 32-bits of MSR value.
1883 @param EDX Upper 32-bits of MSR value.
1885 <b>Example usage</b>
1889 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
1890 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
1892 @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
1894 #define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F
1898 Package. Uncore SBo 1 perfmon counter 0.
1900 @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
1901 @param EAX Lower 32-bits of MSR value.
1902 @param EDX Upper 32-bits of MSR value.
1904 <b>Example usage</b>
1908 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
1909 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
1911 @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
1913 #define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730
1917 Package. Uncore SBo 1 perfmon counter 1.
1919 @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
1920 @param EAX Lower 32-bits of MSR value.
1921 @param EDX Upper 32-bits of MSR value.
1923 <b>Example usage</b>
1927 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
1928 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
1930 @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
1932 #define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731
1936 Package. Uncore SBo 1 perfmon counter 2.
1938 @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
1939 @param EAX Lower 32-bits of MSR value.
1940 @param EDX Upper 32-bits of MSR value.
1942 <b>Example usage</b>
1946 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
1947 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
1949 @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
1951 #define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732
1955 Package. Uncore SBo 1 perfmon counter 3.
1957 @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
1958 @param EAX Lower 32-bits of MSR value.
1959 @param EDX Upper 32-bits of MSR value.
1961 <b>Example usage</b>
1965 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
1966 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
1968 @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
1970 #define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733
1974 Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
1976 @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
1977 @param EAX Lower 32-bits of MSR value.
1978 @param EDX Upper 32-bits of MSR value.
1980 <b>Example usage</b>
1984 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
1985 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
1987 @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
1989 #define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734
1993 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
1995 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
1996 @param EAX Lower 32-bits of MSR value.
1997 @param EDX Upper 32-bits of MSR value.
1999 <b>Example usage</b>
2003 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
2004 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
2006 @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
2008 #define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735
2012 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
2014 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
2015 @param EAX Lower 32-bits of MSR value.
2016 @param EDX Upper 32-bits of MSR value.
2018 <b>Example usage</b>
2022 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
2023 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
2025 @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
2027 #define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736
2031 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
2033 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
2034 @param EAX Lower 32-bits of MSR value.
2035 @param EDX Upper 32-bits of MSR value.
2037 <b>Example usage</b>
2041 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
2042 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
2044 @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
2046 #define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737
2050 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
2052 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
2053 @param EAX Lower 32-bits of MSR value.
2054 @param EDX Upper 32-bits of MSR value.
2056 <b>Example usage</b>
2060 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
2061 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
2063 @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
2065 #define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738
2069 Package. Uncore SBo 2 perfmon box-wide filter.
2071 @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
2072 @param EAX Lower 32-bits of MSR value.
2073 @param EDX Upper 32-bits of MSR value.
2075 <b>Example usage</b>
2079 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
2080 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
2082 @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
2084 #define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739
2088 Package. Uncore SBo 2 perfmon counter 0.
2090 @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
2091 @param EAX Lower 32-bits of MSR value.
2092 @param EDX Upper 32-bits of MSR value.
2094 <b>Example usage</b>
2098 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
2099 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
2101 @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
2103 #define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A
2107 Package. Uncore SBo 2 perfmon counter 1.
2109 @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
2110 @param EAX Lower 32-bits of MSR value.
2111 @param EDX Upper 32-bits of MSR value.
2113 <b>Example usage</b>
2117 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
2118 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
2120 @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
2122 #define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B
2126 Package. Uncore SBo 2 perfmon counter 2.
2128 @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
2129 @param EAX Lower 32-bits of MSR value.
2130 @param EDX Upper 32-bits of MSR value.
2132 <b>Example usage</b>
2136 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
2137 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
2139 @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
2141 #define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C
2145 Package. Uncore SBo 2 perfmon counter 3.
2147 @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
2148 @param EAX Lower 32-bits of MSR value.
2149 @param EDX Upper 32-bits of MSR value.
2151 <b>Example usage</b>
2155 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
2156 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
2158 @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
2160 #define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D
2164 Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
2166 @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
2167 @param EAX Lower 32-bits of MSR value.
2168 @param EDX Upper 32-bits of MSR value.
2170 <b>Example usage</b>
2174 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
2175 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
2177 @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
2179 #define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E
2183 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
2185 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
2186 @param EAX Lower 32-bits of MSR value.
2187 @param EDX Upper 32-bits of MSR value.
2189 <b>Example usage</b>
2193 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
2194 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
2196 @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
2198 #define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F
2202 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
2204 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
2205 @param EAX Lower 32-bits of MSR value.
2206 @param EDX Upper 32-bits of MSR value.
2208 <b>Example usage</b>
2212 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
2213 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
2215 @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
2217 #define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740
2221 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
2223 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
2224 @param EAX Lower 32-bits of MSR value.
2225 @param EDX Upper 32-bits of MSR value.
2227 <b>Example usage</b>
2231 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
2232 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
2234 @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
2236 #define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741
2240 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
2242 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
2243 @param EAX Lower 32-bits of MSR value.
2244 @param EDX Upper 32-bits of MSR value.
2246 <b>Example usage</b>
2250 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
2251 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
2253 @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
2255 #define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742
2259 Package. Uncore SBo 3 perfmon box-wide filter.
2261 @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
2262 @param EAX Lower 32-bits of MSR value.
2263 @param EDX Upper 32-bits of MSR value.
2265 <b>Example usage</b>
2269 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
2270 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
2272 @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
2274 #define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743
2278 Package. Uncore SBo 3 perfmon counter 0.
2280 @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
2281 @param EAX Lower 32-bits of MSR value.
2282 @param EDX Upper 32-bits of MSR value.
2284 <b>Example usage</b>
2288 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
2289 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
2291 @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
2293 #define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744
2297 Package. Uncore SBo 3 perfmon counter 1.
2299 @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
2300 @param EAX Lower 32-bits of MSR value.
2301 @param EDX Upper 32-bits of MSR value.
2303 <b>Example usage</b>
2307 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
2308 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
2310 @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
2312 #define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745
2316 Package. Uncore SBo 3 perfmon counter 2.
2318 @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
2319 @param EAX Lower 32-bits of MSR value.
2320 @param EDX Upper 32-bits of MSR value.
2322 <b>Example usage</b>
2326 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
2327 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
2329 @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
2331 #define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746
2335 Package. Uncore SBo 3 perfmon counter 3.
2337 @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
2338 @param EAX Lower 32-bits of MSR value.
2339 @param EDX Upper 32-bits of MSR value.
2341 <b>Example usage</b>
2345 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
2346 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
2348 @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
2350 #define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747
2354 Package. Uncore C-box 0 perfmon for box-wide control.
2356 @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
2357 @param EAX Lower 32-bits of MSR value.
2358 @param EDX Upper 32-bits of MSR value.
2360 <b>Example usage</b>
2364 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
2365 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
2367 @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
2369 #define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00
2373 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
2375 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
2376 @param EAX Lower 32-bits of MSR value.
2377 @param EDX Upper 32-bits of MSR value.
2379 <b>Example usage</b>
2383 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
2384 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
2386 @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
2388 #define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01
2392 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
2394 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
2395 @param EAX Lower 32-bits of MSR value.
2396 @param EDX Upper 32-bits of MSR value.
2398 <b>Example usage</b>
2402 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
2403 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
2405 @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
2407 #define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02
2411 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
2413 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
2414 @param EAX Lower 32-bits of MSR value.
2415 @param EDX Upper 32-bits of MSR value.
2417 <b>Example usage</b>
2421 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
2422 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
2424 @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
2426 #define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03
2430 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
2432 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
2433 @param EAX Lower 32-bits of MSR value.
2434 @param EDX Upper 32-bits of MSR value.
2436 <b>Example usage</b>
2440 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
2441 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
2443 @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
2445 #define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04
2449 Package. Uncore C-box 0 perfmon box wide filter 0.
2451 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
2452 @param EAX Lower 32-bits of MSR value.
2453 @param EDX Upper 32-bits of MSR value.
2455 <b>Example usage</b>
2459 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
2460 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
2462 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
2464 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05
2468 Package. Uncore C-box 0 perfmon box wide filter 1.
2470 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
2471 @param EAX Lower 32-bits of MSR value.
2472 @param EDX Upper 32-bits of MSR value.
2474 <b>Example usage</b>
2478 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
2479 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
2481 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
2483 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06
2487 Package. Uncore C-box 0 perfmon box wide status.
2489 @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
2490 @param EAX Lower 32-bits of MSR value.
2491 @param EDX Upper 32-bits of MSR value.
2493 <b>Example usage</b>
2497 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
2498 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
2500 @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
2502 #define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07
2506 Package. Uncore C-box 0 perfmon counter 0.
2508 @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
2509 @param EAX Lower 32-bits of MSR value.
2510 @param EDX Upper 32-bits of MSR value.
2512 <b>Example usage</b>
2516 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
2517 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
2519 @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
2521 #define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08
2525 Package. Uncore C-box 0 perfmon counter 1.
2527 @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
2528 @param EAX Lower 32-bits of MSR value.
2529 @param EDX Upper 32-bits of MSR value.
2531 <b>Example usage</b>
2535 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
2536 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
2538 @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
2540 #define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09
2544 Package. Uncore C-box 0 perfmon counter 2.
2546 @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
2547 @param EAX Lower 32-bits of MSR value.
2548 @param EDX Upper 32-bits of MSR value.
2550 <b>Example usage</b>
2554 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
2555 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
2557 @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
2559 #define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A
2563 Package. Uncore C-box 0 perfmon counter 3.
2565 @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
2566 @param EAX Lower 32-bits of MSR value.
2567 @param EDX Upper 32-bits of MSR value.
2569 <b>Example usage</b>
2573 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
2574 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
2576 @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
2578 #define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B
2582 Package. Uncore C-box 1 perfmon for box-wide control.
2584 @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
2585 @param EAX Lower 32-bits of MSR value.
2586 @param EDX Upper 32-bits of MSR value.
2588 <b>Example usage</b>
2592 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
2593 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
2595 @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
2597 #define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10
2601 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
2603 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
2604 @param EAX Lower 32-bits of MSR value.
2605 @param EDX Upper 32-bits of MSR value.
2607 <b>Example usage</b>
2611 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
2612 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
2614 @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
2616 #define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11
2620 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
2622 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
2623 @param EAX Lower 32-bits of MSR value.
2624 @param EDX Upper 32-bits of MSR value.
2626 <b>Example usage</b>
2630 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
2631 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
2633 @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
2635 #define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12
2639 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
2641 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
2642 @param EAX Lower 32-bits of MSR value.
2643 @param EDX Upper 32-bits of MSR value.
2645 <b>Example usage</b>
2649 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
2650 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
2652 @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
2654 #define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13
2658 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
2660 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
2661 @param EAX Lower 32-bits of MSR value.
2662 @param EDX Upper 32-bits of MSR value.
2664 <b>Example usage</b>
2668 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
2669 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
2671 @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
2673 #define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14
2677 Package. Uncore C-box 1 perfmon box wide filter 0.
2679 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
2680 @param EAX Lower 32-bits of MSR value.
2681 @param EDX Upper 32-bits of MSR value.
2683 <b>Example usage</b>
2687 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
2688 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
2690 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
2692 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15
2696 Package. Uncore C-box 1 perfmon box wide filter1.
2698 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
2699 @param EAX Lower 32-bits of MSR value.
2700 @param EDX Upper 32-bits of MSR value.
2702 <b>Example usage</b>
2706 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
2707 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
2709 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
2711 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16
2715 Package. Uncore C-box 1 perfmon box wide status.
2717 @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
2718 @param EAX Lower 32-bits of MSR value.
2719 @param EDX Upper 32-bits of MSR value.
2721 <b>Example usage</b>
2725 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
2726 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
2728 @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
2730 #define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17
2734 Package. Uncore C-box 1 perfmon counter 0.
2736 @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
2737 @param EAX Lower 32-bits of MSR value.
2738 @param EDX Upper 32-bits of MSR value.
2740 <b>Example usage</b>
2744 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
2745 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
2747 @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
2749 #define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18
2753 Package. Uncore C-box 1 perfmon counter 1.
2755 @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
2756 @param EAX Lower 32-bits of MSR value.
2757 @param EDX Upper 32-bits of MSR value.
2759 <b>Example usage</b>
2763 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
2764 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
2766 @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
2768 #define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19
2772 Package. Uncore C-box 1 perfmon counter 2.
2774 @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
2775 @param EAX Lower 32-bits of MSR value.
2776 @param EDX Upper 32-bits of MSR value.
2778 <b>Example usage</b>
2782 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
2783 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
2785 @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
2787 #define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A
2791 Package. Uncore C-box 1 perfmon counter 3.
2793 @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
2794 @param EAX Lower 32-bits of MSR value.
2795 @param EDX Upper 32-bits of MSR value.
2797 <b>Example usage</b>
2801 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
2802 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
2804 @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
2806 #define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B
2810 Package. Uncore C-box 2 perfmon for box-wide control.
2812 @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
2813 @param EAX Lower 32-bits of MSR value.
2814 @param EDX Upper 32-bits of MSR value.
2816 <b>Example usage</b>
2820 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
2821 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
2823 @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
2825 #define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20
2829 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
2831 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
2832 @param EAX Lower 32-bits of MSR value.
2833 @param EDX Upper 32-bits of MSR value.
2835 <b>Example usage</b>
2839 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
2840 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
2842 @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
2844 #define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21
2848 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
2850 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
2851 @param EAX Lower 32-bits of MSR value.
2852 @param EDX Upper 32-bits of MSR value.
2854 <b>Example usage</b>
2858 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
2859 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
2861 @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
2863 #define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22
2867 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
2869 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
2870 @param EAX Lower 32-bits of MSR value.
2871 @param EDX Upper 32-bits of MSR value.
2873 <b>Example usage</b>
2877 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
2878 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
2880 @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
2882 #define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23
2886 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
2888 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
2889 @param EAX Lower 32-bits of MSR value.
2890 @param EDX Upper 32-bits of MSR value.
2892 <b>Example usage</b>
2896 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
2897 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
2899 @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
2901 #define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24
2905 Package. Uncore C-box 2 perfmon box wide filter 0.
2907 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
2908 @param EAX Lower 32-bits of MSR value.
2909 @param EDX Upper 32-bits of MSR value.
2911 <b>Example usage</b>
2915 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
2916 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
2918 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
2920 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25
2924 Package. Uncore C-box 2 perfmon box wide filter1.
2926 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
2927 @param EAX Lower 32-bits of MSR value.
2928 @param EDX Upper 32-bits of MSR value.
2930 <b>Example usage</b>
2934 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
2935 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
2937 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
2939 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26
2943 Package. Uncore C-box 2 perfmon box wide status.
2945 @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
2946 @param EAX Lower 32-bits of MSR value.
2947 @param EDX Upper 32-bits of MSR value.
2949 <b>Example usage</b>
2953 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
2954 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
2956 @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
2958 #define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27
2962 Package. Uncore C-box 2 perfmon counter 0.
2964 @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
2965 @param EAX Lower 32-bits of MSR value.
2966 @param EDX Upper 32-bits of MSR value.
2968 <b>Example usage</b>
2972 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
2973 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
2975 @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
2977 #define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28
2981 Package. Uncore C-box 2 perfmon counter 1.
2983 @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
2984 @param EAX Lower 32-bits of MSR value.
2985 @param EDX Upper 32-bits of MSR value.
2987 <b>Example usage</b>
2991 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
2992 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
2994 @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
2996 #define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29
3000 Package. Uncore C-box 2 perfmon counter 2.
3002 @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
3003 @param EAX Lower 32-bits of MSR value.
3004 @param EDX Upper 32-bits of MSR value.
3006 <b>Example usage</b>
3010 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
3011 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
3013 @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
3015 #define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A
3019 Package. Uncore C-box 2 perfmon counter 3.
3021 @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
3022 @param EAX Lower 32-bits of MSR value.
3023 @param EDX Upper 32-bits of MSR value.
3025 <b>Example usage</b>
3029 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
3030 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
3032 @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
3034 #define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B
3038 Package. Uncore C-box 3 perfmon for box-wide control.
3040 @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
3041 @param EAX Lower 32-bits of MSR value.
3042 @param EDX Upper 32-bits of MSR value.
3044 <b>Example usage</b>
3048 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
3049 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
3051 @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
3053 #define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30
3057 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
3059 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
3060 @param EAX Lower 32-bits of MSR value.
3061 @param EDX Upper 32-bits of MSR value.
3063 <b>Example usage</b>
3067 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
3068 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
3070 @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
3072 #define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31
3076 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
3078 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
3079 @param EAX Lower 32-bits of MSR value.
3080 @param EDX Upper 32-bits of MSR value.
3082 <b>Example usage</b>
3086 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
3087 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
3089 @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
3091 #define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32
3095 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
3097 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
3098 @param EAX Lower 32-bits of MSR value.
3099 @param EDX Upper 32-bits of MSR value.
3101 <b>Example usage</b>
3105 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
3106 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
3108 @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
3110 #define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33
3114 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
3116 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
3117 @param EAX Lower 32-bits of MSR value.
3118 @param EDX Upper 32-bits of MSR value.
3120 <b>Example usage</b>
3124 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
3125 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
3127 @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3129 #define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34
3133 Package. Uncore C-box 3 perfmon box wide filter 0.
3135 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
3136 @param EAX Lower 32-bits of MSR value.
3137 @param EDX Upper 32-bits of MSR value.
3139 <b>Example usage</b>
3143 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
3144 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
3146 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
3148 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35
3152 Package. Uncore C-box 3 perfmon box wide filter1.
3154 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
3155 @param EAX Lower 32-bits of MSR value.
3156 @param EDX Upper 32-bits of MSR value.
3158 <b>Example usage</b>
3162 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
3163 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
3165 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
3167 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36
3171 Package. Uncore C-box 3 perfmon box wide status.
3173 @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
3174 @param EAX Lower 32-bits of MSR value.
3175 @param EDX Upper 32-bits of MSR value.
3177 <b>Example usage</b>
3181 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
3182 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
3184 @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
3186 #define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37
3190 Package. Uncore C-box 3 perfmon counter 0.
3192 @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
3193 @param EAX Lower 32-bits of MSR value.
3194 @param EDX Upper 32-bits of MSR value.
3196 <b>Example usage</b>
3200 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
3201 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
3203 @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3205 #define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38
3209 Package. Uncore C-box 3 perfmon counter 1.
3211 @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
3212 @param EAX Lower 32-bits of MSR value.
3213 @param EDX Upper 32-bits of MSR value.
3215 <b>Example usage</b>
3219 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
3220 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
3222 @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3224 #define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39
3228 Package. Uncore C-box 3 perfmon counter 2.
3230 @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
3231 @param EAX Lower 32-bits of MSR value.
3232 @param EDX Upper 32-bits of MSR value.
3234 <b>Example usage</b>
3238 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
3239 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
3241 @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
3243 #define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A
3247 Package. Uncore C-box 3 perfmon counter 3.
3249 @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
3250 @param EAX Lower 32-bits of MSR value.
3251 @param EDX Upper 32-bits of MSR value.
3253 <b>Example usage</b>
3257 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
3258 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
3260 @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
3262 #define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B
3266 Package. Uncore C-box 4 perfmon for box-wide control.
3268 @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
3269 @param EAX Lower 32-bits of MSR value.
3270 @param EDX Upper 32-bits of MSR value.
3272 <b>Example usage</b>
3276 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
3277 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
3279 @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
3281 #define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40
3285 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
3287 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
3288 @param EAX Lower 32-bits of MSR value.
3289 @param EDX Upper 32-bits of MSR value.
3291 <b>Example usage</b>
3295 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
3296 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
3298 @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
3300 #define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41
3304 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
3306 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
3307 @param EAX Lower 32-bits of MSR value.
3308 @param EDX Upper 32-bits of MSR value.
3310 <b>Example usage</b>
3314 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
3315 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
3317 @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
3319 #define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42
3323 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
3325 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
3326 @param EAX Lower 32-bits of MSR value.
3327 @param EDX Upper 32-bits of MSR value.
3329 <b>Example usage</b>
3333 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
3334 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
3336 @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
3338 #define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43
3342 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
3344 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
3345 @param EAX Lower 32-bits of MSR value.
3346 @param EDX Upper 32-bits of MSR value.
3348 <b>Example usage</b>
3352 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
3353 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
3355 @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
3357 #define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44
3361 Package. Uncore C-box 4 perfmon box wide filter 0.
3363 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
3364 @param EAX Lower 32-bits of MSR value.
3365 @param EDX Upper 32-bits of MSR value.
3367 <b>Example usage</b>
3371 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
3372 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
3374 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
3376 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45
3380 Package. Uncore C-box 4 perfmon box wide filter1.
3382 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
3383 @param EAX Lower 32-bits of MSR value.
3384 @param EDX Upper 32-bits of MSR value.
3386 <b>Example usage</b>
3390 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
3391 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
3393 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
3395 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46
3399 Package. Uncore C-box 4 perfmon box wide status.
3401 @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
3402 @param EAX Lower 32-bits of MSR value.
3403 @param EDX Upper 32-bits of MSR value.
3405 <b>Example usage</b>
3409 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
3410 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
3412 @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
3414 #define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47
3418 Package. Uncore C-box 4 perfmon counter 0.
3420 @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
3421 @param EAX Lower 32-bits of MSR value.
3422 @param EDX Upper 32-bits of MSR value.
3424 <b>Example usage</b>
3428 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
3429 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
3431 @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
3433 #define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48
3437 Package. Uncore C-box 4 perfmon counter 1.
3439 @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
3440 @param EAX Lower 32-bits of MSR value.
3441 @param EDX Upper 32-bits of MSR value.
3443 <b>Example usage</b>
3447 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
3448 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
3450 @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
3452 #define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49
3456 Package. Uncore C-box 4 perfmon counter 2.
3458 @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
3459 @param EAX Lower 32-bits of MSR value.
3460 @param EDX Upper 32-bits of MSR value.
3462 <b>Example usage</b>
3466 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
3467 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
3469 @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
3471 #define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A
3475 Package. Uncore C-box 4 perfmon counter 3.
3477 @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
3478 @param EAX Lower 32-bits of MSR value.
3479 @param EDX Upper 32-bits of MSR value.
3481 <b>Example usage</b>
3485 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
3486 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
3488 @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
3490 #define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B
3494 Package. Uncore C-box 5 perfmon for box-wide control.
3496 @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
3497 @param EAX Lower 32-bits of MSR value.
3498 @param EDX Upper 32-bits of MSR value.
3500 <b>Example usage</b>
3504 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
3505 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
3507 @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
3509 #define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50
3513 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
3515 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
3516 @param EAX Lower 32-bits of MSR value.
3517 @param EDX Upper 32-bits of MSR value.
3519 <b>Example usage</b>
3523 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
3524 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
3526 @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
3528 #define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51
3532 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
3534 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
3535 @param EAX Lower 32-bits of MSR value.
3536 @param EDX Upper 32-bits of MSR value.
3538 <b>Example usage</b>
3542 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
3543 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
3545 @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
3547 #define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52
3551 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
3553 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
3554 @param EAX Lower 32-bits of MSR value.
3555 @param EDX Upper 32-bits of MSR value.
3557 <b>Example usage</b>
3561 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
3562 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
3564 @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
3566 #define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53
3570 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
3572 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
3573 @param EAX Lower 32-bits of MSR value.
3574 @param EDX Upper 32-bits of MSR value.
3576 <b>Example usage</b>
3580 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
3581 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
3583 @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
3585 #define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54
3589 Package. Uncore C-box 5 perfmon box wide filter 0.
3591 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
3592 @param EAX Lower 32-bits of MSR value.
3593 @param EDX Upper 32-bits of MSR value.
3595 <b>Example usage</b>
3599 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
3600 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
3602 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
3604 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55
3608 Package. Uncore C-box 5 perfmon box wide filter1.
3610 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
3611 @param EAX Lower 32-bits of MSR value.
3612 @param EDX Upper 32-bits of MSR value.
3614 <b>Example usage</b>
3618 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
3619 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
3621 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
3623 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56
3627 Package. Uncore C-box 5 perfmon box wide status.
3629 @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
3630 @param EAX Lower 32-bits of MSR value.
3631 @param EDX Upper 32-bits of MSR value.
3633 <b>Example usage</b>
3637 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
3638 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
3640 @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
3642 #define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57
3646 Package. Uncore C-box 5 perfmon counter 0.
3648 @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
3649 @param EAX Lower 32-bits of MSR value.
3650 @param EDX Upper 32-bits of MSR value.
3652 <b>Example usage</b>
3656 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
3657 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
3659 @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
3661 #define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58
3665 Package. Uncore C-box 5 perfmon counter 1.
3667 @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
3668 @param EAX Lower 32-bits of MSR value.
3669 @param EDX Upper 32-bits of MSR value.
3671 <b>Example usage</b>
3675 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
3676 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
3678 @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
3680 #define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59
3684 Package. Uncore C-box 5 perfmon counter 2.
3686 @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
3687 @param EAX Lower 32-bits of MSR value.
3688 @param EDX Upper 32-bits of MSR value.
3690 <b>Example usage</b>
3694 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
3695 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
3697 @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
3699 #define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A
3703 Package. Uncore C-box 5 perfmon counter 3.
3705 @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
3706 @param EAX Lower 32-bits of MSR value.
3707 @param EDX Upper 32-bits of MSR value.
3709 <b>Example usage</b>
3713 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
3714 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
3716 @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
3718 #define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B
3722 Package. Uncore C-box 6 perfmon for box-wide control.
3724 @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
3725 @param EAX Lower 32-bits of MSR value.
3726 @param EDX Upper 32-bits of MSR value.
3728 <b>Example usage</b>
3732 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
3733 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
3735 @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
3737 #define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60
3741 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
3743 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
3744 @param EAX Lower 32-bits of MSR value.
3745 @param EDX Upper 32-bits of MSR value.
3747 <b>Example usage</b>
3751 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
3752 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
3754 @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
3756 #define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61
3760 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
3762 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
3763 @param EAX Lower 32-bits of MSR value.
3764 @param EDX Upper 32-bits of MSR value.
3766 <b>Example usage</b>
3770 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
3771 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
3773 @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
3775 #define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62
3779 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
3781 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
3782 @param EAX Lower 32-bits of MSR value.
3783 @param EDX Upper 32-bits of MSR value.
3785 <b>Example usage</b>
3789 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
3790 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
3792 @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
3794 #define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63
3798 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
3800 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
3801 @param EAX Lower 32-bits of MSR value.
3802 @param EDX Upper 32-bits of MSR value.
3804 <b>Example usage</b>
3808 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
3809 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
3811 @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
3813 #define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64
3817 Package. Uncore C-box 6 perfmon box wide filter 0.
3819 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
3820 @param EAX Lower 32-bits of MSR value.
3821 @param EDX Upper 32-bits of MSR value.
3823 <b>Example usage</b>
3827 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
3828 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
3830 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
3832 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65
3836 Package. Uncore C-box 6 perfmon box wide filter1.
3838 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
3839 @param EAX Lower 32-bits of MSR value.
3840 @param EDX Upper 32-bits of MSR value.
3842 <b>Example usage</b>
3846 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
3847 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
3849 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
3851 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66
3855 Package. Uncore C-box 6 perfmon box wide status.
3857 @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
3858 @param EAX Lower 32-bits of MSR value.
3859 @param EDX Upper 32-bits of MSR value.
3861 <b>Example usage</b>
3865 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
3866 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
3868 @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
3870 #define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67
3874 Package. Uncore C-box 6 perfmon counter 0.
3876 @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
3877 @param EAX Lower 32-bits of MSR value.
3878 @param EDX Upper 32-bits of MSR value.
3880 <b>Example usage</b>
3884 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
3885 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
3887 @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
3889 #define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68
3893 Package. Uncore C-box 6 perfmon counter 1.
3895 @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
3896 @param EAX Lower 32-bits of MSR value.
3897 @param EDX Upper 32-bits of MSR value.
3899 <b>Example usage</b>
3903 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
3904 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
3906 @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
3908 #define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69
3912 Package. Uncore C-box 6 perfmon counter 2.
3914 @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
3915 @param EAX Lower 32-bits of MSR value.
3916 @param EDX Upper 32-bits of MSR value.
3918 <b>Example usage</b>
3922 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
3923 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
3925 @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
3927 #define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A
3931 Package. Uncore C-box 6 perfmon counter 3.
3933 @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
3934 @param EAX Lower 32-bits of MSR value.
3935 @param EDX Upper 32-bits of MSR value.
3937 <b>Example usage</b>
3941 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
3942 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
3944 @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
3946 #define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B
3950 Package. Uncore C-box 7 perfmon for box-wide control.
3952 @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
3953 @param EAX Lower 32-bits of MSR value.
3954 @param EDX Upper 32-bits of MSR value.
3956 <b>Example usage</b>
3960 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
3961 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
3963 @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
3965 #define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70
3969 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
3971 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
3972 @param EAX Lower 32-bits of MSR value.
3973 @param EDX Upper 32-bits of MSR value.
3975 <b>Example usage</b>
3979 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
3980 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
3982 @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
3984 #define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71
3988 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
3990 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
3991 @param EAX Lower 32-bits of MSR value.
3992 @param EDX Upper 32-bits of MSR value.
3994 <b>Example usage</b>
3998 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
3999 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
4001 @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
4003 #define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72
4007 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
4009 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
4010 @param EAX Lower 32-bits of MSR value.
4011 @param EDX Upper 32-bits of MSR value.
4013 <b>Example usage</b>
4017 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
4018 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
4020 @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
4022 #define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73
4026 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
4028 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
4029 @param EAX Lower 32-bits of MSR value.
4030 @param EDX Upper 32-bits of MSR value.
4032 <b>Example usage</b>
4036 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
4037 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
4039 @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
4041 #define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74
4045 Package. Uncore C-box 7 perfmon box wide filter 0.
4047 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
4048 @param EAX Lower 32-bits of MSR value.
4049 @param EDX Upper 32-bits of MSR value.
4051 <b>Example usage</b>
4055 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
4056 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
4058 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
4060 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75
4064 Package. Uncore C-box 7 perfmon box wide filter1.
4066 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
4067 @param EAX Lower 32-bits of MSR value.
4068 @param EDX Upper 32-bits of MSR value.
4070 <b>Example usage</b>
4074 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
4075 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
4077 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
4079 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76
4083 Package. Uncore C-box 7 perfmon box wide status.
4085 @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
4086 @param EAX Lower 32-bits of MSR value.
4087 @param EDX Upper 32-bits of MSR value.
4089 <b>Example usage</b>
4093 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
4094 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
4096 @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
4098 #define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77
4102 Package. Uncore C-box 7 perfmon counter 0.
4104 @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
4105 @param EAX Lower 32-bits of MSR value.
4106 @param EDX Upper 32-bits of MSR value.
4108 <b>Example usage</b>
4112 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
4113 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
4115 @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
4117 #define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78
4121 Package. Uncore C-box 7 perfmon counter 1.
4123 @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
4124 @param EAX Lower 32-bits of MSR value.
4125 @param EDX Upper 32-bits of MSR value.
4127 <b>Example usage</b>
4131 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
4132 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
4134 @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
4136 #define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79
4140 Package. Uncore C-box 7 perfmon counter 2.
4142 @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
4143 @param EAX Lower 32-bits of MSR value.
4144 @param EDX Upper 32-bits of MSR value.
4146 <b>Example usage</b>
4150 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
4151 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
4153 @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
4155 #define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A
4159 Package. Uncore C-box 7 perfmon counter 3.
4161 @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
4162 @param EAX Lower 32-bits of MSR value.
4163 @param EDX Upper 32-bits of MSR value.
4165 <b>Example usage</b>
4169 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
4170 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
4172 @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
4174 #define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B
4178 Package. Uncore C-box 8 perfmon local box wide control.
4180 @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
4181 @param EAX Lower 32-bits of MSR value.
4182 @param EDX Upper 32-bits of MSR value.
4184 <b>Example usage</b>
4188 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
4189 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
4191 @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
4193 #define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80
4197 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
4199 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
4200 @param EAX Lower 32-bits of MSR value.
4201 @param EDX Upper 32-bits of MSR value.
4203 <b>Example usage</b>
4207 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
4208 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
4210 @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
4212 #define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81
4216 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
4218 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
4219 @param EAX Lower 32-bits of MSR value.
4220 @param EDX Upper 32-bits of MSR value.
4222 <b>Example usage</b>
4226 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
4227 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
4229 @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
4231 #define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82
4235 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
4237 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
4238 @param EAX Lower 32-bits of MSR value.
4239 @param EDX Upper 32-bits of MSR value.
4241 <b>Example usage</b>
4245 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
4246 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
4248 @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
4250 #define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83
4254 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
4256 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
4257 @param EAX Lower 32-bits of MSR value.
4258 @param EDX Upper 32-bits of MSR value.
4260 <b>Example usage</b>
4264 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
4265 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
4267 @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
4269 #define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84
4273 Package. Uncore C-box 8 perfmon box wide filter0.
4275 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
4276 @param EAX Lower 32-bits of MSR value.
4277 @param EDX Upper 32-bits of MSR value.
4279 <b>Example usage</b>
4283 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
4284 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
4286 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
4288 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85
4292 Package. Uncore C-box 8 perfmon box wide filter1.
4294 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
4295 @param EAX Lower 32-bits of MSR value.
4296 @param EDX Upper 32-bits of MSR value.
4298 <b>Example usage</b>
4302 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
4303 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
4305 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
4307 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86
4311 Package. Uncore C-box 8 perfmon box wide status.
4313 @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
4314 @param EAX Lower 32-bits of MSR value.
4315 @param EDX Upper 32-bits of MSR value.
4317 <b>Example usage</b>
4321 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
4322 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
4324 @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
4326 #define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87
4330 Package. Uncore C-box 8 perfmon counter 0.
4332 @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
4333 @param EAX Lower 32-bits of MSR value.
4334 @param EDX Upper 32-bits of MSR value.
4336 <b>Example usage</b>
4340 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
4341 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
4343 @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
4345 #define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88
4349 Package. Uncore C-box 8 perfmon counter 1.
4351 @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
4352 @param EAX Lower 32-bits of MSR value.
4353 @param EDX Upper 32-bits of MSR value.
4355 <b>Example usage</b>
4359 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
4360 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
4362 @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
4364 #define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89
4368 Package. Uncore C-box 8 perfmon counter 2.
4370 @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
4371 @param EAX Lower 32-bits of MSR value.
4372 @param EDX Upper 32-bits of MSR value.
4374 <b>Example usage</b>
4378 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
4379 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
4381 @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
4383 #define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A
4387 Package. Uncore C-box 8 perfmon counter 3.
4389 @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
4390 @param EAX Lower 32-bits of MSR value.
4391 @param EDX Upper 32-bits of MSR value.
4393 <b>Example usage</b>
4397 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
4398 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
4400 @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
4402 #define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B
4406 Package. Uncore C-box 9 perfmon local box wide control.
4408 @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
4409 @param EAX Lower 32-bits of MSR value.
4410 @param EDX Upper 32-bits of MSR value.
4412 <b>Example usage</b>
4416 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
4417 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
4419 @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
4421 #define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90
4425 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
4427 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
4428 @param EAX Lower 32-bits of MSR value.
4429 @param EDX Upper 32-bits of MSR value.
4431 <b>Example usage</b>
4435 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
4436 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
4438 @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
4440 #define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91
4444 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
4446 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
4447 @param EAX Lower 32-bits of MSR value.
4448 @param EDX Upper 32-bits of MSR value.
4450 <b>Example usage</b>
4454 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
4455 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
4457 @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
4459 #define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92
4463 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
4465 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
4466 @param EAX Lower 32-bits of MSR value.
4467 @param EDX Upper 32-bits of MSR value.
4469 <b>Example usage</b>
4473 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
4474 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
4476 @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
4478 #define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93
4482 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
4484 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
4485 @param EAX Lower 32-bits of MSR value.
4486 @param EDX Upper 32-bits of MSR value.
4488 <b>Example usage</b>
4492 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
4493 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
4495 @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
4497 #define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94
4501 Package. Uncore C-box 9 perfmon box wide filter0.
4503 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
4504 @param EAX Lower 32-bits of MSR value.
4505 @param EDX Upper 32-bits of MSR value.
4507 <b>Example usage</b>
4511 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
4512 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
4514 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
4516 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95
4520 Package. Uncore C-box 9 perfmon box wide filter1.
4522 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
4523 @param EAX Lower 32-bits of MSR value.
4524 @param EDX Upper 32-bits of MSR value.
4526 <b>Example usage</b>
4530 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
4531 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
4533 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
4535 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96
4539 Package. Uncore C-box 9 perfmon box wide status.
4541 @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
4542 @param EAX Lower 32-bits of MSR value.
4543 @param EDX Upper 32-bits of MSR value.
4545 <b>Example usage</b>
4549 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
4550 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
4552 @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
4554 #define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97
4558 Package. Uncore C-box 9 perfmon counter 0.
4560 @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
4561 @param EAX Lower 32-bits of MSR value.
4562 @param EDX Upper 32-bits of MSR value.
4564 <b>Example usage</b>
4568 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
4569 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
4571 @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
4573 #define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98
4577 Package. Uncore C-box 9 perfmon counter 1.
4579 @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
4580 @param EAX Lower 32-bits of MSR value.
4581 @param EDX Upper 32-bits of MSR value.
4583 <b>Example usage</b>
4587 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
4588 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
4590 @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
4592 #define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99
4596 Package. Uncore C-box 9 perfmon counter 2.
4598 @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
4599 @param EAX Lower 32-bits of MSR value.
4600 @param EDX Upper 32-bits of MSR value.
4602 <b>Example usage</b>
4606 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
4607 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
4609 @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
4611 #define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A
4615 Package. Uncore C-box 9 perfmon counter 3.
4617 @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
4618 @param EAX Lower 32-bits of MSR value.
4619 @param EDX Upper 32-bits of MSR value.
4621 <b>Example usage</b>
4625 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
4626 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
4628 @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
4630 #define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B
4634 Package. Uncore C-box 10 perfmon local box wide control.
4636 @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
4637 @param EAX Lower 32-bits of MSR value.
4638 @param EDX Upper 32-bits of MSR value.
4640 <b>Example usage</b>
4644 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
4645 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
4647 @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
4649 #define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0
4653 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
4655 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
4656 @param EAX Lower 32-bits of MSR value.
4657 @param EDX Upper 32-bits of MSR value.
4659 <b>Example usage</b>
4663 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
4664 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
4666 @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
4668 #define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1
4672 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
4674 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
4675 @param EAX Lower 32-bits of MSR value.
4676 @param EDX Upper 32-bits of MSR value.
4678 <b>Example usage</b>
4682 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
4683 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
4685 @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
4687 #define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2
4691 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
4693 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
4694 @param EAX Lower 32-bits of MSR value.
4695 @param EDX Upper 32-bits of MSR value.
4697 <b>Example usage</b>
4701 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
4702 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
4704 @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
4706 #define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3
4710 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
4712 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
4713 @param EAX Lower 32-bits of MSR value.
4714 @param EDX Upper 32-bits of MSR value.
4716 <b>Example usage</b>
4720 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
4721 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
4723 @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
4725 #define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4
4729 Package. Uncore C-box 10 perfmon box wide filter0.
4731 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
4732 @param EAX Lower 32-bits of MSR value.
4733 @param EDX Upper 32-bits of MSR value.
4735 <b>Example usage</b>
4739 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
4740 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
4742 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
4744 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5
4748 Package. Uncore C-box 10 perfmon box wide filter1.
4750 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
4751 @param EAX Lower 32-bits of MSR value.
4752 @param EDX Upper 32-bits of MSR value.
4754 <b>Example usage</b>
4758 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
4759 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
4761 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
4763 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6
4767 Package. Uncore C-box 10 perfmon box wide status.
4769 @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
4770 @param EAX Lower 32-bits of MSR value.
4771 @param EDX Upper 32-bits of MSR value.
4773 <b>Example usage</b>
4777 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
4778 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
4780 @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
4782 #define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7
4786 Package. Uncore C-box 10 perfmon counter 0.
4788 @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
4789 @param EAX Lower 32-bits of MSR value.
4790 @param EDX Upper 32-bits of MSR value.
4792 <b>Example usage</b>
4796 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
4797 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
4799 @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
4801 #define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8
4805 Package. Uncore C-box 10 perfmon counter 1.
4807 @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
4808 @param EAX Lower 32-bits of MSR value.
4809 @param EDX Upper 32-bits of MSR value.
4811 <b>Example usage</b>
4815 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
4816 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
4818 @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
4820 #define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9
4824 Package. Uncore C-box 10 perfmon counter 2.
4826 @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
4827 @param EAX Lower 32-bits of MSR value.
4828 @param EDX Upper 32-bits of MSR value.
4830 <b>Example usage</b>
4834 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
4835 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
4837 @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
4839 #define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA
4843 Package. Uncore C-box 10 perfmon counter 3.
4845 @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
4846 @param EAX Lower 32-bits of MSR value.
4847 @param EDX Upper 32-bits of MSR value.
4849 <b>Example usage</b>
4853 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
4854 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
4856 @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
4858 #define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB
4862 Package. Uncore C-box 11 perfmon local box wide control.
4864 @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
4865 @param EAX Lower 32-bits of MSR value.
4866 @param EDX Upper 32-bits of MSR value.
4868 <b>Example usage</b>
4872 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
4873 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
4875 @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
4877 #define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0
4881 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
4883 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
4884 @param EAX Lower 32-bits of MSR value.
4885 @param EDX Upper 32-bits of MSR value.
4887 <b>Example usage</b>
4891 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
4892 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
4894 @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
4896 #define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1
4900 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
4902 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
4903 @param EAX Lower 32-bits of MSR value.
4904 @param EDX Upper 32-bits of MSR value.
4906 <b>Example usage</b>
4910 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
4911 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
4913 @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
4915 #define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2
4919 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
4921 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
4922 @param EAX Lower 32-bits of MSR value.
4923 @param EDX Upper 32-bits of MSR value.
4925 <b>Example usage</b>
4929 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
4930 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
4932 @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
4934 #define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3
4938 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
4940 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
4941 @param EAX Lower 32-bits of MSR value.
4942 @param EDX Upper 32-bits of MSR value.
4944 <b>Example usage</b>
4948 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
4949 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
4951 @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
4953 #define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4
4957 Package. Uncore C-box 11 perfmon box wide filter0.
4959 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
4960 @param EAX Lower 32-bits of MSR value.
4961 @param EDX Upper 32-bits of MSR value.
4963 <b>Example usage</b>
4967 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
4968 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
4970 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
4972 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5
4976 Package. Uncore C-box 11 perfmon box wide filter1.
4978 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
4979 @param EAX Lower 32-bits of MSR value.
4980 @param EDX Upper 32-bits of MSR value.
4982 <b>Example usage</b>
4986 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
4987 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
4989 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
4991 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6
4995 Package. Uncore C-box 11 perfmon box wide status.
4997 @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
4998 @param EAX Lower 32-bits of MSR value.
4999 @param EDX Upper 32-bits of MSR value.
5001 <b>Example usage</b>
5005 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
5006 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
5008 @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
5010 #define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7
5014 Package. Uncore C-box 11 perfmon counter 0.
5016 @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
5017 @param EAX Lower 32-bits of MSR value.
5018 @param EDX Upper 32-bits of MSR value.
5020 <b>Example usage</b>
5024 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
5025 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
5027 @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
5029 #define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8
5033 Package. Uncore C-box 11 perfmon counter 1.
5035 @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
5036 @param EAX Lower 32-bits of MSR value.
5037 @param EDX Upper 32-bits of MSR value.
5039 <b>Example usage</b>
5043 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
5044 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
5046 @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
5048 #define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9
5052 Package. Uncore C-box 11 perfmon counter 2.
5054 @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
5055 @param EAX Lower 32-bits of MSR value.
5056 @param EDX Upper 32-bits of MSR value.
5058 <b>Example usage</b>
5062 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
5063 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
5065 @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
5067 #define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA
5071 Package. Uncore C-box 11 perfmon counter 3.
5073 @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
5074 @param EAX Lower 32-bits of MSR value.
5075 @param EDX Upper 32-bits of MSR value.
5077 <b>Example usage</b>
5081 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
5082 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
5084 @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
5086 #define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB
5090 Package. Uncore C-box 12 perfmon local box wide control.
5092 @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
5093 @param EAX Lower 32-bits of MSR value.
5094 @param EDX Upper 32-bits of MSR value.
5096 <b>Example usage</b>
5100 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
5101 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
5103 @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
5105 #define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0
5109 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
5111 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
5112 @param EAX Lower 32-bits of MSR value.
5113 @param EDX Upper 32-bits of MSR value.
5115 <b>Example usage</b>
5119 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
5120 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
5122 @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
5124 #define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1
5128 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
5130 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
5131 @param EAX Lower 32-bits of MSR value.
5132 @param EDX Upper 32-bits of MSR value.
5134 <b>Example usage</b>
5138 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
5139 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
5141 @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
5143 #define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2
5147 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
5149 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
5150 @param EAX Lower 32-bits of MSR value.
5151 @param EDX Upper 32-bits of MSR value.
5153 <b>Example usage</b>
5157 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
5158 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
5160 @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
5162 #define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3
5166 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
5168 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
5169 @param EAX Lower 32-bits of MSR value.
5170 @param EDX Upper 32-bits of MSR value.
5172 <b>Example usage</b>
5176 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
5177 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
5179 @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
5181 #define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4
5185 Package. Uncore C-box 12 perfmon box wide filter0.
5187 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
5188 @param EAX Lower 32-bits of MSR value.
5189 @param EDX Upper 32-bits of MSR value.
5191 <b>Example usage</b>
5195 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
5196 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
5198 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
5200 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5
5204 Package. Uncore C-box 12 perfmon box wide filter1.
5206 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
5207 @param EAX Lower 32-bits of MSR value.
5208 @param EDX Upper 32-bits of MSR value.
5210 <b>Example usage</b>
5214 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
5215 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
5217 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
5219 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6
5223 Package. Uncore C-box 12 perfmon box wide status.
5225 @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
5226 @param EAX Lower 32-bits of MSR value.
5227 @param EDX Upper 32-bits of MSR value.
5229 <b>Example usage</b>
5233 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
5234 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
5236 @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
5238 #define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7
5242 Package. Uncore C-box 12 perfmon counter 0.
5244 @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
5245 @param EAX Lower 32-bits of MSR value.
5246 @param EDX Upper 32-bits of MSR value.
5248 <b>Example usage</b>
5252 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
5253 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
5255 @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
5257 #define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8
5261 Package. Uncore C-box 12 perfmon counter 1.
5263 @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
5264 @param EAX Lower 32-bits of MSR value.
5265 @param EDX Upper 32-bits of MSR value.
5267 <b>Example usage</b>
5271 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
5272 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
5274 @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
5276 #define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9
5280 Package. Uncore C-box 12 perfmon counter 2.
5282 @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
5283 @param EAX Lower 32-bits of MSR value.
5284 @param EDX Upper 32-bits of MSR value.
5286 <b>Example usage</b>
5290 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
5291 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
5293 @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
5295 #define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA
5299 Package. Uncore C-box 12 perfmon counter 3.
5301 @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
5302 @param EAX Lower 32-bits of MSR value.
5303 @param EDX Upper 32-bits of MSR value.
5305 <b>Example usage</b>
5309 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
5310 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
5312 @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
5314 #define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB
5318 Package. Uncore C-box 13 perfmon local box wide control.
5320 @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
5321 @param EAX Lower 32-bits of MSR value.
5322 @param EDX Upper 32-bits of MSR value.
5324 <b>Example usage</b>
5328 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
5329 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
5331 @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
5333 #define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0
5337 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
5339 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
5340 @param EAX Lower 32-bits of MSR value.
5341 @param EDX Upper 32-bits of MSR value.
5343 <b>Example usage</b>
5347 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
5348 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
5350 @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
5352 #define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1
5356 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
5358 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
5359 @param EAX Lower 32-bits of MSR value.
5360 @param EDX Upper 32-bits of MSR value.
5362 <b>Example usage</b>
5366 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
5367 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
5369 @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
5371 #define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2
5375 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
5377 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
5378 @param EAX Lower 32-bits of MSR value.
5379 @param EDX Upper 32-bits of MSR value.
5381 <b>Example usage</b>
5385 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
5386 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
5388 @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
5390 #define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3
5394 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
5396 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
5397 @param EAX Lower 32-bits of MSR value.
5398 @param EDX Upper 32-bits of MSR value.
5400 <b>Example usage</b>
5404 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
5405 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
5407 @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
5409 #define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4
5413 Package. Uncore C-box 13 perfmon box wide filter0.
5415 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
5416 @param EAX Lower 32-bits of MSR value.
5417 @param EDX Upper 32-bits of MSR value.
5419 <b>Example usage</b>
5423 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
5424 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
5426 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
5428 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5
5432 Package. Uncore C-box 13 perfmon box wide filter1.
5434 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
5435 @param EAX Lower 32-bits of MSR value.
5436 @param EDX Upper 32-bits of MSR value.
5438 <b>Example usage</b>
5442 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
5443 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
5445 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
5447 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6
5451 Package. Uncore C-box 13 perfmon box wide status.
5453 @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
5454 @param EAX Lower 32-bits of MSR value.
5455 @param EDX Upper 32-bits of MSR value.
5457 <b>Example usage</b>
5461 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
5462 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
5464 @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
5466 #define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7
5470 Package. Uncore C-box 13 perfmon counter 0.
5472 @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
5473 @param EAX Lower 32-bits of MSR value.
5474 @param EDX Upper 32-bits of MSR value.
5476 <b>Example usage</b>
5480 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
5481 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
5483 @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
5485 #define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8
5489 Package. Uncore C-box 13 perfmon counter 1.
5491 @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
5492 @param EAX Lower 32-bits of MSR value.
5493 @param EDX Upper 32-bits of MSR value.
5495 <b>Example usage</b>
5499 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
5500 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
5502 @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
5504 #define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9
5508 Package. Uncore C-box 13 perfmon counter 2.
5510 @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
5511 @param EAX Lower 32-bits of MSR value.
5512 @param EDX Upper 32-bits of MSR value.
5514 <b>Example usage</b>
5518 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
5519 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
5521 @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
5523 #define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA
5527 Package. Uncore C-box 13 perfmon counter 3.
5529 @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
5530 @param EAX Lower 32-bits of MSR value.
5531 @param EDX Upper 32-bits of MSR value.
5533 <b>Example usage</b>
5537 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
5538 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
5540 @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
5542 #define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB
5546 Package. Uncore C-box 14 perfmon local box wide control.
5548 @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
5549 @param EAX Lower 32-bits of MSR value.
5550 @param EDX Upper 32-bits of MSR value.
5552 <b>Example usage</b>
5556 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
5557 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
5559 @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
5561 #define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0
5565 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
5567 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
5568 @param EAX Lower 32-bits of MSR value.
5569 @param EDX Upper 32-bits of MSR value.
5571 <b>Example usage</b>
5575 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
5576 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
5578 @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
5580 #define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1
5584 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
5586 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
5587 @param EAX Lower 32-bits of MSR value.
5588 @param EDX Upper 32-bits of MSR value.
5590 <b>Example usage</b>
5594 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
5595 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
5597 @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
5599 #define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2
5603 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
5605 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
5606 @param EAX Lower 32-bits of MSR value.
5607 @param EDX Upper 32-bits of MSR value.
5609 <b>Example usage</b>
5613 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
5614 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
5616 @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
5618 #define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3
5622 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
5624 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
5625 @param EAX Lower 32-bits of MSR value.
5626 @param EDX Upper 32-bits of MSR value.
5628 <b>Example usage</b>
5632 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
5633 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
5635 @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
5637 #define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4
5641 Package. Uncore C-box 14 perfmon box wide filter0.
5643 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
5644 @param EAX Lower 32-bits of MSR value.
5645 @param EDX Upper 32-bits of MSR value.
5647 <b>Example usage</b>
5651 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
5652 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
5654 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
5656 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5
5660 Package. Uncore C-box 14 perfmon box wide filter1.
5662 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
5663 @param EAX Lower 32-bits of MSR value.
5664 @param EDX Upper 32-bits of MSR value.
5666 <b>Example usage</b>
5670 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
5671 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
5673 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
5675 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6
5679 Package. Uncore C-box 14 perfmon box wide status.
5681 @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
5682 @param EAX Lower 32-bits of MSR value.
5683 @param EDX Upper 32-bits of MSR value.
5685 <b>Example usage</b>
5689 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
5690 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
5692 @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
5694 #define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7
5698 Package. Uncore C-box 14 perfmon counter 0.
5700 @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
5701 @param EAX Lower 32-bits of MSR value.
5702 @param EDX Upper 32-bits of MSR value.
5704 <b>Example usage</b>
5708 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
5709 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
5711 @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
5713 #define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8
5717 Package. Uncore C-box 14 perfmon counter 1.
5719 @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
5720 @param EAX Lower 32-bits of MSR value.
5721 @param EDX Upper 32-bits of MSR value.
5723 <b>Example usage</b>
5727 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
5728 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
5730 @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
5732 #define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9
5736 Package. Uncore C-box 14 perfmon counter 2.
5738 @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
5739 @param EAX Lower 32-bits of MSR value.
5740 @param EDX Upper 32-bits of MSR value.
5742 <b>Example usage</b>
5746 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
5747 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
5749 @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
5751 #define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA
5755 Package. Uncore C-box 14 perfmon counter 3.
5757 @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
5758 @param EAX Lower 32-bits of MSR value.
5759 @param EDX Upper 32-bits of MSR value.
5761 <b>Example usage</b>
5765 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
5766 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
5768 @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
5770 #define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB
5774 Package. Uncore C-box 15 perfmon local box wide control.
5776 @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
5777 @param EAX Lower 32-bits of MSR value.
5778 @param EDX Upper 32-bits of MSR value.
5780 <b>Example usage</b>
5784 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
5785 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
5787 @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
5789 #define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0
5793 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
5795 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
5796 @param EAX Lower 32-bits of MSR value.
5797 @param EDX Upper 32-bits of MSR value.
5799 <b>Example usage</b>
5803 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
5804 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
5806 @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
5808 #define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1
5812 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
5814 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
5815 @param EAX Lower 32-bits of MSR value.
5816 @param EDX Upper 32-bits of MSR value.
5818 <b>Example usage</b>
5822 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
5823 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
5825 @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
5827 #define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2
5831 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
5833 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
5834 @param EAX Lower 32-bits of MSR value.
5835 @param EDX Upper 32-bits of MSR value.
5837 <b>Example usage</b>
5841 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
5842 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
5844 @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
5846 #define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3
5850 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
5852 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
5853 @param EAX Lower 32-bits of MSR value.
5854 @param EDX Upper 32-bits of MSR value.
5856 <b>Example usage</b>
5860 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
5861 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
5863 @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
5865 #define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4
5869 Package. Uncore C-box 15 perfmon box wide filter0.
5871 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
5872 @param EAX Lower 32-bits of MSR value.
5873 @param EDX Upper 32-bits of MSR value.
5875 <b>Example usage</b>
5879 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
5880 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
5882 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
5884 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5
5888 Package. Uncore C-box 15 perfmon box wide filter1.
5890 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
5891 @param EAX Lower 32-bits of MSR value.
5892 @param EDX Upper 32-bits of MSR value.
5894 <b>Example usage</b>
5898 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
5899 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
5901 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
5903 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6
5907 Package. Uncore C-box 15 perfmon box wide status.
5909 @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
5910 @param EAX Lower 32-bits of MSR value.
5911 @param EDX Upper 32-bits of MSR value.
5913 <b>Example usage</b>
5917 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
5918 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
5920 @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
5922 #define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7
5926 Package. Uncore C-box 15 perfmon counter 0.
5928 @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
5929 @param EAX Lower 32-bits of MSR value.
5930 @param EDX Upper 32-bits of MSR value.
5932 <b>Example usage</b>
5936 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
5937 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
5939 @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
5941 #define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8
5945 Package. Uncore C-box 15 perfmon counter 1.
5947 @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
5948 @param EAX Lower 32-bits of MSR value.
5949 @param EDX Upper 32-bits of MSR value.
5951 <b>Example usage</b>
5955 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
5956 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
5958 @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
5960 #define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9
5964 Package. Uncore C-box 15 perfmon counter 2.
5966 @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
5967 @param EAX Lower 32-bits of MSR value.
5968 @param EDX Upper 32-bits of MSR value.
5970 <b>Example usage</b>
5974 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
5975 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
5977 @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
5979 #define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA
5983 Package. Uncore C-box 15 perfmon counter 3.
5985 @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
5986 @param EAX Lower 32-bits of MSR value.
5987 @param EDX Upper 32-bits of MSR value.
5989 <b>Example usage</b>
5993 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
5994 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
5996 @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
5998 #define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB
6002 Package. Uncore C-box 16 perfmon for box-wide control.
6004 @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
6005 @param EAX Lower 32-bits of MSR value.
6006 @param EDX Upper 32-bits of MSR value.
6008 <b>Example usage</b>
6012 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
6013 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
6015 @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
6017 #define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00
6021 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
6023 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
6024 @param EAX Lower 32-bits of MSR value.
6025 @param EDX Upper 32-bits of MSR value.
6027 <b>Example usage</b>
6031 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
6032 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
6034 @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
6036 #define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01
6040 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
6042 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
6043 @param EAX Lower 32-bits of MSR value.
6044 @param EDX Upper 32-bits of MSR value.
6046 <b>Example usage</b>
6050 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
6051 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
6053 @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
6055 #define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02
6059 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
6061 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
6062 @param EAX Lower 32-bits of MSR value.
6063 @param EDX Upper 32-bits of MSR value.
6065 <b>Example usage</b>
6069 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
6070 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
6072 @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
6074 #define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03
6078 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
6080 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
6081 @param EAX Lower 32-bits of MSR value.
6082 @param EDX Upper 32-bits of MSR value.
6084 <b>Example usage</b>
6088 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
6089 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
6091 @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
6093 #define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04
6097 Package. Uncore C-box 16 perfmon box wide filter 0.
6099 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
6100 @param EAX Lower 32-bits of MSR value.
6101 @param EDX Upper 32-bits of MSR value.
6103 <b>Example usage</b>
6107 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
6108 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
6110 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
6112 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05
6116 Package. Uncore C-box 16 perfmon box wide filter 1.
6118 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
6119 @param EAX Lower 32-bits of MSR value.
6120 @param EDX Upper 32-bits of MSR value.
6122 <b>Example usage</b>
6126 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
6127 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
6129 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
6131 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06
6135 Package. Uncore C-box 16 perfmon box wide status.
6137 @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
6138 @param EAX Lower 32-bits of MSR value.
6139 @param EDX Upper 32-bits of MSR value.
6141 <b>Example usage</b>
6145 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
6146 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
6148 @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
6150 #define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07
6154 Package. Uncore C-box 16 perfmon counter 0.
6156 @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
6157 @param EAX Lower 32-bits of MSR value.
6158 @param EDX Upper 32-bits of MSR value.
6160 <b>Example usage</b>
6164 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
6165 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
6167 @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
6169 #define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08
6173 Package. Uncore C-box 16 perfmon counter 1.
6175 @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
6176 @param EAX Lower 32-bits of MSR value.
6177 @param EDX Upper 32-bits of MSR value.
6179 <b>Example usage</b>
6183 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
6184 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
6186 @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
6188 #define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09
6192 Package. Uncore C-box 16 perfmon counter 2.
6194 @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
6195 @param EAX Lower 32-bits of MSR value.
6196 @param EDX Upper 32-bits of MSR value.
6198 <b>Example usage</b>
6202 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
6203 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
6205 @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
6207 #define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A
6211 Package. Uncore C-box 16 perfmon counter 3.
6213 @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
6214 @param EAX Lower 32-bits of MSR value.
6215 @param EDX Upper 32-bits of MSR value.
6217 <b>Example usage</b>
6221 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
6222 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
6224 @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
6226 #define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B
6230 Package. Uncore C-box 17 perfmon for box-wide control.
6232 @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
6233 @param EAX Lower 32-bits of MSR value.
6234 @param EDX Upper 32-bits of MSR value.
6236 <b>Example usage</b>
6240 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
6241 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
6243 @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
6245 #define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10
6249 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
6251 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
6252 @param EAX Lower 32-bits of MSR value.
6253 @param EDX Upper 32-bits of MSR value.
6255 <b>Example usage</b>
6259 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
6260 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
6262 @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
6264 #define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11
6268 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
6270 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
6271 @param EAX Lower 32-bits of MSR value.
6272 @param EDX Upper 32-bits of MSR value.
6274 <b>Example usage</b>
6278 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
6279 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
6281 @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
6283 #define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12
6287 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
6289 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
6290 @param EAX Lower 32-bits of MSR value.
6291 @param EDX Upper 32-bits of MSR value.
6293 <b>Example usage</b>
6297 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
6298 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
6300 @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
6302 #define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13
6306 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
6308 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
6309 @param EAX Lower 32-bits of MSR value.
6310 @param EDX Upper 32-bits of MSR value.
6312 <b>Example usage</b>
6316 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
6317 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
6319 @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
6321 #define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14
6325 Package. Uncore C-box 17 perfmon box wide filter 0.
6327 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
6328 @param EAX Lower 32-bits of MSR value.
6329 @param EDX Upper 32-bits of MSR value.
6331 <b>Example usage</b>
6335 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
6336 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
6338 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
6340 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15
6344 Package. Uncore C-box 17 perfmon box wide filter1.
6346 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
6347 @param EAX Lower 32-bits of MSR value.
6348 @param EDX Upper 32-bits of MSR value.
6350 <b>Example usage</b>
6354 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
6355 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
6357 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
6359 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16
6362 Package. Uncore C-box 17 perfmon box wide status.
6364 @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
6365 @param EAX Lower 32-bits of MSR value.
6366 @param EDX Upper 32-bits of MSR value.
6368 <b>Example usage</b>
6372 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
6373 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
6375 @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
6377 #define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17
6381 Package. Uncore C-box 17 perfmon counter n.
6383 @param ECX MSR_HASWELL_E_C17_PMON_CTRn
6384 @param EAX Lower 32-bits of MSR value.
6385 @param EDX Upper 32-bits of MSR value.
6387 <b>Example usage</b>
6391 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
6392 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
6394 @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.
6395 MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.
6396 MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.
6397 MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
6400 #define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18
6401 #define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19
6402 #define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A
6403 #define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B