2 MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __IVY_BRIDGE_MSR_H__
25 #define __IVY_BRIDGE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Ivy Bridge microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x3A || \
42 DisplayModel == 0x3E \
47 Package. See http://biosbits.org.
49 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
50 @param EAX Lower 32-bits of MSR value.
51 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
52 @param EDX Upper 32-bits of MSR value.
53 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
57 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
59 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
60 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
62 @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
64 #define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE
67 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
71 /// Individual bit fields
76 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
77 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
80 UINT32 MaximumNonTurboRatio
:8;
83 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
84 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
85 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
86 /// Turbo mode is disabled.
90 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
91 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
92 /// and when set to 0, indicates TDP Limit for Turbo mode is not
98 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
99 /// indicates that LPM is supported, and when set to 0, indicates LPM is
102 UINT32 LowPowerModeSupport
:1;
104 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
105 /// TDP level available. 01: One additional TDP level available. 02: Two
106 /// additional TDP level available. 11: Reserved.
108 UINT32 ConfigTDPLevels
:2;
111 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
112 /// minimum ratio (maximum efficiency) that the processor can operates, in
115 UINT32 MaximumEfficiencyRatio
:8;
117 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
118 /// minimum supported operating ratio in units of 100 MHz.
120 UINT32 MinimumOperatingRatio
:8;
124 /// All bit fields as a 64-bit value
127 } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
;
131 Core. C-State Configuration Control (R/W) Note: C-state values are
132 processor specific C-state code names, unrelated to MWAIT extension C-state
133 parameters or ACPI C-States. See http://biosbits.org.
135 @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
136 @param EAX Lower 32-bits of MSR value.
137 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
138 @param EDX Upper 32-bits of MSR value.
139 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
143 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
145 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
146 AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
148 @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
150 #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
153 MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL
157 /// Individual bit fields
161 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
162 /// processor-specific C-state code name (consuming the least power). for
163 /// the package. The default is set as factory-configured package C-state
164 /// limit. The following C-state code name encodings are supported: 000b:
165 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
166 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
167 /// This field cannot be used to limit package C-state to C3.
172 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
173 /// IO_read instructions sent to IO register specified by
174 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
179 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
180 /// until next reset.
185 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
186 /// will conditionally demote C6/C7 requests to C3 based on uncore
187 /// auto-demote information.
189 UINT32 C3AutoDemotion
:1;
191 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
192 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
193 /// auto-demote information.
195 UINT32 C1AutoDemotion
:1;
197 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
200 UINT32 C3Undemotion
:1;
202 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
205 UINT32 C1Undemotion
:1;
210 /// All bit fields as a 32-bit value
214 /// All bit fields as a 64-bit value
217 } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
;
221 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
224 @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
225 @param EAX Lower 32-bits of MSR value.
226 @param EDX Upper 32-bits of MSR value.
232 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);
234 @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
236 #define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
240 Package. Base TDP Ratio (R/O).
242 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
243 @param EAX Lower 32-bits of MSR value.
244 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
245 @param EDX Upper 32-bits of MSR value.
246 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
250 MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr;
252 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
254 @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
256 #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648
259 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL
263 /// Individual bit fields
267 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
268 /// specific processor (in units of 100 MHz).
270 UINT32 Config_TDP_Base
:8;
275 /// All bit fields as a 32-bit value
279 /// All bit fields as a 64-bit value
282 } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER
;
286 Package. ConfigTDP Level 1 ratio and power level (R/O).
288 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)
289 @param EAX Lower 32-bits of MSR value.
290 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
291 @param EDX Upper 32-bits of MSR value.
292 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
296 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr;
298 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
300 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
302 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649
305 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1
309 /// Individual bit fields
313 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
315 UINT32 PKG_TDP_LVL1
:15;
318 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
319 /// for this specific processor.
321 UINT32 Config_TDP_LVL1_Ratio
:8;
324 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
327 UINT32 PKG_MAX_PWR_LVL1
:15;
330 /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
333 UINT32 PKG_MIN_PWR_LVL1
:15;
337 /// All bit fields as a 64-bit value
340 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
;
344 Package. ConfigTDP Level 2 ratio and power level (R/O).
346 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)
347 @param EAX Lower 32-bits of MSR value.
348 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
349 @param EDX Upper 32-bits of MSR value.
350 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
354 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr;
356 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
358 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
360 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A
363 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
367 /// Individual bit fields
371 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
373 UINT32 PKG_TDP_LVL2
:15;
376 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
377 /// for this specific processor.
379 UINT32 Config_TDP_LVL2_Ratio
:8;
382 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
385 UINT32 PKG_MAX_PWR_LVL2
:15;
388 /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
391 UINT32 PKG_MIN_PWR_LVL2
:15;
395 /// All bit fields as a 64-bit value
398 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
;
402 Package. ConfigTDP Control (R/W).
404 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)
405 @param EAX Lower 32-bits of MSR value.
406 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
407 @param EDX Upper 32-bits of MSR value.
408 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
412 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr;
414 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
415 AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
417 @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
419 #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B
422 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL
426 /// Individual bit fields
430 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
435 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
436 /// this register is locked until a reset.
438 UINT32 Config_TDP_Lock
:1;
442 /// All bit fields as a 32-bit value
446 /// All bit fields as a 64-bit value
449 } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
;
453 Package. ConfigTDP Control (R/W).
455 @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)
456 @param EAX Lower 32-bits of MSR value.
457 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
458 @param EDX Upper 32-bits of MSR value.
459 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
463 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr;
465 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
466 AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
468 @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
470 #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C
473 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO
477 /// Individual bit fields
481 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
484 UINT32 MAX_NON_TURBO_RATIO
:8;
487 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
488 /// content of this register is locked until a reset.
490 UINT32 TURBO_ACTIVATION_RATIO_Lock
:1;
494 /// All bit fields as a 32-bit value
498 /// All bit fields as a 64-bit value
501 } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
;
505 Package. Protected Processor Inventory Number Enable Control (R/W).
507 @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)
508 @param EAX Lower 32-bits of MSR value.
509 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
510 @param EDX Upper 32-bits of MSR value.
511 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
515 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr;
517 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
518 AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
520 @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
522 #define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E
525 MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL
529 /// Individual bit fields
533 /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.
534 /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit
535 /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to
536 /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged
537 /// inventory initialization agent to access MSR_PPIN. After reading
538 /// MSR_PPIN, the privileged inventory initialization agent should write
539 /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
540 /// prevent unauthorized modification to MSR_PPIN_CTL.
544 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
545 /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will
546 /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default
549 UINT32 Enable_PPIN
:1;
554 /// All bit fields as a 32-bit value
558 /// All bit fields as a 64-bit value
561 } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER
;
565 Package. Protected Processor Inventory Number (R/O). Protected Processor
566 Inventory Number (R/O) A unique value within a given CPUID
567 family/model/stepping signature that a privileged inventory initialization
568 agent can access to identify each physical processor, when access to
569 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
570 MSR_PPIN_CTL[bits 1:0] = '10b'.
572 @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F)
573 @param EAX Lower 32-bits of MSR value.
574 @param EDX Upper 32-bits of MSR value.
580 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
582 @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.
584 #define MSR_IVY_BRIDGE_PPIN 0x0000004F
588 Package. See http://biosbits.org.
590 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)
591 @param EAX Lower 32-bits of MSR value.
592 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
593 @param EDX Upper 32-bits of MSR value.
594 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
598 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr;
600 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
601 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
603 @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.
605 #define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE
608 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1
612 /// Individual bit fields
617 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
618 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
621 UINT32 MaximumNonTurboRatio
:8;
624 /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that
625 /// Protected Processor Inventory Number (PPIN) capability can be enabled
626 /// for privileged system inventory agent to read PPIN from MSR_PPIN. When
627 /// set to 0, PPIN capability is not supported. An attempt to access
628 /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.
633 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
634 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
635 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
636 /// Turbo mode is disabled.
640 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
641 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
642 /// and when set to 0, indicates TDP Limit for Turbo mode is not
647 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,
648 /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
649 /// specify an temperature offset.
655 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
656 /// minimum ratio (maximum efficiency) that the processor can operates, in
659 UINT32 MaximumEfficiencyRatio
:8;
663 /// All bit fields as a 64-bit value
666 } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER
;
670 Package. MC Bank Error Configuration (R/W).
672 @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)
673 @param EAX Lower 32-bits of MSR value.
674 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
675 @param EDX Upper 32-bits of MSR value.
676 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
680 MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
682 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
683 AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
685 @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
687 #define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F
690 MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL
694 /// Individual bit fields
699 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
700 /// to log additional info in bits 36:32.
702 UINT32 MemErrorLogEnable
:1;
707 /// All bit fields as a 32-bit value
711 /// All bit fields as a 64-bit value
714 } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER
;
720 @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
721 @param EAX Lower 32-bits of MSR value.
722 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
723 @param EDX Upper 32-bits of MSR value.
724 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
728 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
730 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
731 AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
733 @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
735 #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
738 MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET
742 /// Individual bit fields
747 /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which
748 /// PROCHOT# will be asserted. The value is degree C.
750 UINT32 TemperatureTarget
:8;
752 /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature
753 /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#
754 /// will assert at the offset target temperature. Write is permitted only
755 /// MSR_PLATFORM_INFO.[30] is set.
757 UINT32 TCCActivationOffset
:4;
762 /// All bit fields as a 32-bit value
766 /// All bit fields as a 64-bit value
769 } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER
;
773 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
774 RW if MSR_PLATFORM_INFO.[28] = 1.
776 @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)
777 @param EAX Lower 32-bits of MSR value.
778 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
779 @param EDX Upper 32-bits of MSR value.
780 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
784 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr;
786 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
788 @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
790 #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE
793 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1
797 /// Individual bit fields
801 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
802 /// limit of 9 core active.
806 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
807 /// limit of 10core active.
811 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
812 /// limit of 11 core active.
816 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
817 /// limit of 12 core active.
821 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
822 /// limit of 13 core active.
826 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
827 /// limit of 14 core active.
831 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
832 /// limit of 15 core active.
837 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
838 /// the processor uses override configuration specified in
839 /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor
840 /// uses factory-set configuration (Default).
842 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
845 /// All bit fields as a 64-bit value
848 } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER
;
852 Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
854 @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
855 @param EAX Lower 32-bits of MSR value.
856 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
857 @param EDX Upper 32-bits of MSR value.
858 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
862 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;
864 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
866 @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
868 #define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B
871 MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
875 /// Individual bit fields
879 /// [Bits 5:0] Recoverable Address LSB.
881 UINT32 RecoverableAddressLSB
:6;
883 /// [Bits 8:6] Address Mode.
885 UINT32 AddressMode
:3;
888 /// [Bits 31:16] PCI Express Requestor ID.
890 UINT32 PCIExpressRequestorID
:16;
892 /// [Bits 39:32] PCI Express Segment Number.
894 UINT32 PCIExpressSegmentNumber
:8;
898 /// All bit fields as a 64-bit value
901 } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
;
905 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
906 15.3.2.4, "IA32_MCi_MISC MSRs.".
908 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
909 and its corresponding slice of L3.
911 @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL
912 @param EAX Lower 32-bits of MSR value.
913 @param EDX Upper 32-bits of MSR value.
919 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
920 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);
922 @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.
923 MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.
924 MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.
927 #define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474
928 #define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478
929 #define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C
934 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
935 15.3.2.4, "IA32_MCi_MISC MSRs.".
937 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
938 and its corresponding slice of L3.
940 @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS
941 @param EAX Lower 32-bits of MSR value.
942 @param EDX Upper 32-bits of MSR value.
948 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
949 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);
951 @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.
952 MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.
953 MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.
956 #define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475
957 #define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479
958 #define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D
963 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
964 15.3.2.4, "IA32_MCi_MISC MSRs.".
966 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
967 and its corresponding slice of L3.
969 @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR
970 @param EAX Lower 32-bits of MSR value.
971 @param EDX Upper 32-bits of MSR value.
977 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
978 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);
980 @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.
981 MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.
982 MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.
985 #define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476
986 #define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A
987 #define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E
992 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
993 15.3.2.4, "IA32_MCi_MISC MSRs.".
995 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
996 and its corresponding slice of L3.
998 @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC
999 @param EAX Lower 32-bits of MSR value.
1000 @param EDX Upper 32-bits of MSR value.
1002 <b>Example usage</b>
1006 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
1007 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);
1009 @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.
1010 MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.
1011 MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.
1014 #define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477
1015 #define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B
1016 #define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F
1021 Package. Package RAPL Perf Status (R/O).
1023 @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)
1024 @param EAX Lower 32-bits of MSR value.
1025 @param EDX Upper 32-bits of MSR value.
1027 <b>Example usage</b>
1031 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);
1033 @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1035 #define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613
1039 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1042 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
1043 @param EAX Lower 32-bits of MSR value.
1044 @param EDX Upper 32-bits of MSR value.
1046 <b>Example usage</b>
1050 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
1051 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);
1053 @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1055 #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
1059 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1061 @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
1062 @param EAX Lower 32-bits of MSR value.
1063 @param EDX Upper 32-bits of MSR value.
1065 <b>Example usage</b>
1069 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);
1071 @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1073 #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
1077 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1080 @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
1081 @param EAX Lower 32-bits of MSR value.
1082 @param EDX Upper 32-bits of MSR value.
1084 <b>Example usage</b>
1088 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);
1090 @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1092 #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
1096 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1098 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
1099 @param EAX Lower 32-bits of MSR value.
1100 @param EDX Upper 32-bits of MSR value.
1102 <b>Example usage</b>
1106 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
1107 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);
1109 @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1111 #define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C
1115 Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
1117 @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
1118 @param EAX Lower 32-bits of MSR value.
1119 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1120 @param EDX Upper 32-bits of MSR value.
1121 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1123 <b>Example usage</b>
1125 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
1127 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
1128 AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1130 @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1132 #define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1
1135 MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE
1139 /// Individual bit fields
1143 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1145 UINT32 PEBS_EN_PMC0
:1;
1147 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1149 UINT32 PEBS_EN_PMC1
:1;
1151 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1153 UINT32 PEBS_EN_PMC2
:1;
1155 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1157 UINT32 PEBS_EN_PMC3
:1;
1158 UINT32 Reserved1
:28;
1160 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1162 UINT32 LL_EN_PMC0
:1;
1164 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1166 UINT32 LL_EN_PMC1
:1;
1168 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1170 UINT32 LL_EN_PMC2
:1;
1172 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1174 UINT32 LL_EN_PMC3
:1;
1175 UINT32 Reserved2
:28;
1178 /// All bit fields as a 64-bit value
1181 } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER
;
1185 Package. Uncore perfmon per-socket global control.
1187 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)
1188 @param EAX Lower 32-bits of MSR value.
1189 @param EDX Upper 32-bits of MSR value.
1191 <b>Example usage</b>
1195 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
1196 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);
1198 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1200 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00
1204 Package. Uncore perfmon per-socket global status.
1206 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)
1207 @param EAX Lower 32-bits of MSR value.
1208 @param EDX Upper 32-bits of MSR value.
1210 <b>Example usage</b>
1214 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
1215 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);
1217 @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1219 #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01
1223 Package. Uncore perfmon per-socket global configuration.
1225 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)
1226 @param EAX Lower 32-bits of MSR value.
1227 @param EDX Upper 32-bits of MSR value.
1229 <b>Example usage</b>
1233 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
1234 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);
1236 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1238 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06
1242 Package. Uncore U-box perfmon U-box wide status.
1244 @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)
1245 @param EAX Lower 32-bits of MSR value.
1246 @param EDX Upper 32-bits of MSR value.
1248 <b>Example usage</b>
1252 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
1253 AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);
1255 @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1257 #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15
1261 Package. Uncore PCU perfmon box wide status.
1263 @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)
1264 @param EAX Lower 32-bits of MSR value.
1265 @param EDX Upper 32-bits of MSR value.
1267 <b>Example usage</b>
1271 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
1272 AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);
1274 @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1276 #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35
1280 Package. Uncore C-box 0 perfmon box wide filter1.
1282 @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)
1283 @param EAX Lower 32-bits of MSR value.
1284 @param EDX Upper 32-bits of MSR value.
1286 <b>Example usage</b>
1290 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
1291 AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);
1293 @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
1295 #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A
1299 Package. Uncore C-box 1 perfmon box wide filter1.
1301 @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)
1302 @param EAX Lower 32-bits of MSR value.
1303 @param EDX Upper 32-bits of MSR value.
1305 <b>Example usage</b>
1309 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
1310 AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);
1312 @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
1314 #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A
1318 Package. Uncore C-box 2 perfmon box wide filter1.
1320 @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)
1321 @param EAX Lower 32-bits of MSR value.
1322 @param EDX Upper 32-bits of MSR value.
1324 <b>Example usage</b>
1328 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
1329 AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);
1331 @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
1333 #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A
1337 Package. Uncore C-box 3 perfmon box wide filter1.
1339 @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)
1340 @param EAX Lower 32-bits of MSR value.
1341 @param EDX Upper 32-bits of MSR value.
1343 <b>Example usage</b>
1347 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
1348 AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);
1350 @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
1352 #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A
1356 Package. Uncore C-box 4 perfmon box wide filter1.
1358 @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)
1359 @param EAX Lower 32-bits of MSR value.
1360 @param EDX Upper 32-bits of MSR value.
1362 <b>Example usage</b>
1366 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
1367 AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);
1369 @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
1371 #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A
1375 Package. Uncore C-box 5 perfmon box wide filter1.
1377 @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)
1378 @param EAX Lower 32-bits of MSR value.
1379 @param EDX Upper 32-bits of MSR value.
1381 <b>Example usage</b>
1385 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
1386 AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);
1388 @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
1390 #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA
1394 Package. Uncore C-box 6 perfmon box wide filter1.
1396 @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)
1397 @param EAX Lower 32-bits of MSR value.
1398 @param EDX Upper 32-bits of MSR value.
1400 <b>Example usage</b>
1404 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
1405 AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);
1407 @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
1409 #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA
1413 Package. Uncore C-box 7 perfmon box wide filter1.
1415 @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)
1416 @param EAX Lower 32-bits of MSR value.
1417 @param EDX Upper 32-bits of MSR value.
1419 <b>Example usage</b>
1423 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
1424 AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);
1426 @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
1428 #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA
1432 Package. Uncore C-box 8 perfmon local box wide control.
1434 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)
1435 @param EAX Lower 32-bits of MSR value.
1436 @param EDX Upper 32-bits of MSR value.
1438 <b>Example usage</b>
1442 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
1443 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);
1445 @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
1447 #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04
1451 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
1453 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)
1454 @param EAX Lower 32-bits of MSR value.
1455 @param EDX Upper 32-bits of MSR value.
1457 <b>Example usage</b>
1461 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
1462 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);
1464 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
1466 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10
1470 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
1472 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)
1473 @param EAX Lower 32-bits of MSR value.
1474 @param EDX Upper 32-bits of MSR value.
1476 <b>Example usage</b>
1480 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
1481 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);
1483 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
1485 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11
1489 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
1491 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)
1492 @param EAX Lower 32-bits of MSR value.
1493 @param EDX Upper 32-bits of MSR value.
1495 <b>Example usage</b>
1499 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
1500 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);
1502 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
1504 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12
1508 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
1510 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)
1511 @param EAX Lower 32-bits of MSR value.
1512 @param EDX Upper 32-bits of MSR value.
1514 <b>Example usage</b>
1518 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
1519 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);
1521 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
1523 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13
1527 Package. Uncore C-box 8 perfmon box wide filter.
1529 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)
1530 @param EAX Lower 32-bits of MSR value.
1531 @param EDX Upper 32-bits of MSR value.
1533 <b>Example usage</b>
1537 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
1538 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);
1540 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.
1542 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14
1546 Package. Uncore C-box 8 perfmon counter 0.
1548 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)
1549 @param EAX Lower 32-bits of MSR value.
1550 @param EDX Upper 32-bits of MSR value.
1552 <b>Example usage</b>
1556 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
1557 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);
1559 @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
1561 #define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16
1565 Package. Uncore C-box 8 perfmon counter 1.
1567 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)
1568 @param EAX Lower 32-bits of MSR value.
1569 @param EDX Upper 32-bits of MSR value.
1571 <b>Example usage</b>
1575 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
1576 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);
1578 @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
1580 #define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17
1584 Package. Uncore C-box 8 perfmon counter 2.
1586 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)
1587 @param EAX Lower 32-bits of MSR value.
1588 @param EDX Upper 32-bits of MSR value.
1590 <b>Example usage</b>
1594 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
1595 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);
1597 @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
1599 #define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18
1603 Package. Uncore C-box 8 perfmon counter 3.
1605 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)
1606 @param EAX Lower 32-bits of MSR value.
1607 @param EDX Upper 32-bits of MSR value.
1609 <b>Example usage</b>
1613 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
1614 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);
1616 @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
1618 #define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19
1622 Package. Uncore C-box 8 perfmon box wide filter1.
1624 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)
1625 @param EAX Lower 32-bits of MSR value.
1626 @param EDX Upper 32-bits of MSR value.
1628 <b>Example usage</b>
1632 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
1633 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);
1635 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
1637 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A
1641 Package. Uncore C-box 9 perfmon local box wide control.
1643 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)
1644 @param EAX Lower 32-bits of MSR value.
1645 @param EDX Upper 32-bits of MSR value.
1647 <b>Example usage</b>
1651 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
1652 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);
1654 @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
1656 #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24
1660 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
1662 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)
1663 @param EAX Lower 32-bits of MSR value.
1664 @param EDX Upper 32-bits of MSR value.
1666 <b>Example usage</b>
1670 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
1671 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);
1673 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
1675 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30
1679 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
1681 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)
1682 @param EAX Lower 32-bits of MSR value.
1683 @param EDX Upper 32-bits of MSR value.
1685 <b>Example usage</b>
1689 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
1690 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);
1692 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
1694 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31
1698 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
1700 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)
1701 @param EAX Lower 32-bits of MSR value.
1702 @param EDX Upper 32-bits of MSR value.
1704 <b>Example usage</b>
1708 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
1709 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);
1711 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
1713 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32
1717 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
1719 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)
1720 @param EAX Lower 32-bits of MSR value.
1721 @param EDX Upper 32-bits of MSR value.
1723 <b>Example usage</b>
1727 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
1728 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);
1730 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
1732 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33
1736 Package. Uncore C-box 9 perfmon box wide filter.
1738 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)
1739 @param EAX Lower 32-bits of MSR value.
1740 @param EDX Upper 32-bits of MSR value.
1742 <b>Example usage</b>
1746 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
1747 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);
1749 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.
1751 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34
1755 Package. Uncore C-box 9 perfmon counter 0.
1757 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)
1758 @param EAX Lower 32-bits of MSR value.
1759 @param EDX Upper 32-bits of MSR value.
1761 <b>Example usage</b>
1765 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
1766 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);
1768 @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
1770 #define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36
1774 Package. Uncore C-box 9 perfmon counter 1.
1776 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)
1777 @param EAX Lower 32-bits of MSR value.
1778 @param EDX Upper 32-bits of MSR value.
1780 <b>Example usage</b>
1784 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
1785 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);
1787 @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
1789 #define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37
1793 Package. Uncore C-box 9 perfmon counter 2.
1795 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)
1796 @param EAX Lower 32-bits of MSR value.
1797 @param EDX Upper 32-bits of MSR value.
1799 <b>Example usage</b>
1803 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
1804 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);
1806 @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
1808 #define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38
1812 Package. Uncore C-box 9 perfmon counter 3.
1814 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)
1815 @param EAX Lower 32-bits of MSR value.
1816 @param EDX Upper 32-bits of MSR value.
1818 <b>Example usage</b>
1822 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
1823 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);
1825 @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
1827 #define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39
1831 Package. Uncore C-box 9 perfmon box wide filter1.
1833 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)
1834 @param EAX Lower 32-bits of MSR value.
1835 @param EDX Upper 32-bits of MSR value.
1837 <b>Example usage</b>
1841 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
1842 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);
1844 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
1846 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A
1850 Package. Uncore C-box 10 perfmon local box wide control.
1852 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)
1853 @param EAX Lower 32-bits of MSR value.
1854 @param EDX Upper 32-bits of MSR value.
1856 <b>Example usage</b>
1860 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
1861 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);
1863 @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
1865 #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44
1869 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
1871 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)
1872 @param EAX Lower 32-bits of MSR value.
1873 @param EDX Upper 32-bits of MSR value.
1875 <b>Example usage</b>
1879 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
1880 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);
1882 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
1884 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50
1888 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
1890 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)
1891 @param EAX Lower 32-bits of MSR value.
1892 @param EDX Upper 32-bits of MSR value.
1894 <b>Example usage</b>
1898 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
1899 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);
1901 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
1903 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51
1907 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
1909 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)
1910 @param EAX Lower 32-bits of MSR value.
1911 @param EDX Upper 32-bits of MSR value.
1913 <b>Example usage</b>
1917 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
1918 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);
1920 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
1922 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52
1926 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
1928 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)
1929 @param EAX Lower 32-bits of MSR value.
1930 @param EDX Upper 32-bits of MSR value.
1932 <b>Example usage</b>
1936 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
1937 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);
1939 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
1941 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53
1945 Package. Uncore C-box 10 perfmon box wide filter.
1947 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)
1948 @param EAX Lower 32-bits of MSR value.
1949 @param EDX Upper 32-bits of MSR value.
1951 <b>Example usage</b>
1955 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
1956 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);
1958 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.
1960 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54
1964 Package. Uncore C-box 10 perfmon counter 0.
1966 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)
1967 @param EAX Lower 32-bits of MSR value.
1968 @param EDX Upper 32-bits of MSR value.
1970 <b>Example usage</b>
1974 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
1975 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);
1977 @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
1979 #define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56
1983 Package. Uncore C-box 10 perfmon counter 1.
1985 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)
1986 @param EAX Lower 32-bits of MSR value.
1987 @param EDX Upper 32-bits of MSR value.
1989 <b>Example usage</b>
1993 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
1994 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);
1996 @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
1998 #define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57
2002 Package. Uncore C-box 10 perfmon counter 2.
2004 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)
2005 @param EAX Lower 32-bits of MSR value.
2006 @param EDX Upper 32-bits of MSR value.
2008 <b>Example usage</b>
2012 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
2013 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);
2015 @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
2017 #define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58
2021 Package. Uncore C-box 10 perfmon counter 3.
2023 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)
2024 @param EAX Lower 32-bits of MSR value.
2025 @param EDX Upper 32-bits of MSR value.
2027 <b>Example usage</b>
2031 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
2032 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);
2034 @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
2036 #define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59
2040 Package. Uncore C-box 10 perfmon box wide filter1.
2042 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)
2043 @param EAX Lower 32-bits of MSR value.
2044 @param EDX Upper 32-bits of MSR value.
2046 <b>Example usage</b>
2050 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
2051 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);
2053 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
2055 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A
2059 Package. Uncore C-box 11 perfmon local box wide control.
2061 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)
2062 @param EAX Lower 32-bits of MSR value.
2063 @param EDX Upper 32-bits of MSR value.
2065 <b>Example usage</b>
2069 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
2070 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);
2072 @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
2074 #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64
2078 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
2080 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)
2081 @param EAX Lower 32-bits of MSR value.
2082 @param EDX Upper 32-bits of MSR value.
2084 <b>Example usage</b>
2088 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
2089 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);
2091 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
2093 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70
2097 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
2099 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)
2100 @param EAX Lower 32-bits of MSR value.
2101 @param EDX Upper 32-bits of MSR value.
2103 <b>Example usage</b>
2107 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
2108 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);
2110 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
2112 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71
2116 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
2118 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)
2119 @param EAX Lower 32-bits of MSR value.
2120 @param EDX Upper 32-bits of MSR value.
2122 <b>Example usage</b>
2126 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
2127 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);
2129 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
2131 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72
2135 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
2137 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)
2138 @param EAX Lower 32-bits of MSR value.
2139 @param EDX Upper 32-bits of MSR value.
2141 <b>Example usage</b>
2145 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
2146 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);
2148 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
2150 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73
2154 Package. Uncore C-box 11 perfmon box wide filter.
2156 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)
2157 @param EAX Lower 32-bits of MSR value.
2158 @param EDX Upper 32-bits of MSR value.
2160 <b>Example usage</b>
2164 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
2165 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);
2167 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.
2169 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74
2173 Package. Uncore C-box 11 perfmon counter 0.
2175 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)
2176 @param EAX Lower 32-bits of MSR value.
2177 @param EDX Upper 32-bits of MSR value.
2179 <b>Example usage</b>
2183 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
2184 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);
2186 @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
2188 #define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76
2192 Package. Uncore C-box 11 perfmon counter 1.
2194 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)
2195 @param EAX Lower 32-bits of MSR value.
2196 @param EDX Upper 32-bits of MSR value.
2198 <b>Example usage</b>
2202 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
2203 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);
2205 @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
2207 #define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77
2211 Package. Uncore C-box 11 perfmon counter 2.
2213 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)
2214 @param EAX Lower 32-bits of MSR value.
2215 @param EDX Upper 32-bits of MSR value.
2217 <b>Example usage</b>
2221 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
2222 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);
2224 @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
2226 #define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78
2230 Package. Uncore C-box 11 perfmon counter 3.
2232 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)
2233 @param EAX Lower 32-bits of MSR value.
2234 @param EDX Upper 32-bits of MSR value.
2236 <b>Example usage</b>
2240 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
2241 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);
2243 @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
2245 #define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79
2249 Package. Uncore C-box 11 perfmon box wide filter1.
2251 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)
2252 @param EAX Lower 32-bits of MSR value.
2253 @param EDX Upper 32-bits of MSR value.
2255 <b>Example usage</b>
2259 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
2260 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);
2262 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
2264 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A
2268 Package. Uncore C-box 12 perfmon local box wide control.
2270 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)
2271 @param EAX Lower 32-bits of MSR value.
2272 @param EDX Upper 32-bits of MSR value.
2274 <b>Example usage</b>
2278 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
2279 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);
2281 @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
2283 #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84
2287 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
2289 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)
2290 @param EAX Lower 32-bits of MSR value.
2291 @param EDX Upper 32-bits of MSR value.
2293 <b>Example usage</b>
2297 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
2298 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);
2300 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
2302 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90
2306 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
2308 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)
2309 @param EAX Lower 32-bits of MSR value.
2310 @param EDX Upper 32-bits of MSR value.
2312 <b>Example usage</b>
2316 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
2317 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);
2319 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
2321 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91
2325 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
2327 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)
2328 @param EAX Lower 32-bits of MSR value.
2329 @param EDX Upper 32-bits of MSR value.
2331 <b>Example usage</b>
2335 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
2336 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);
2338 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
2340 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92
2344 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
2346 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)
2347 @param EAX Lower 32-bits of MSR value.
2348 @param EDX Upper 32-bits of MSR value.
2350 <b>Example usage</b>
2354 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
2355 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);
2357 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
2359 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93
2363 Package. Uncore C-box 12 perfmon box wide filter.
2365 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)
2366 @param EAX Lower 32-bits of MSR value.
2367 @param EDX Upper 32-bits of MSR value.
2369 <b>Example usage</b>
2373 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
2374 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);
2376 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.
2378 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94
2382 Package. Uncore C-box 12 perfmon counter 0.
2384 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)
2385 @param EAX Lower 32-bits of MSR value.
2386 @param EDX Upper 32-bits of MSR value.
2388 <b>Example usage</b>
2392 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
2393 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);
2395 @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
2397 #define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96
2401 Package. Uncore C-box 12 perfmon counter 1.
2403 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)
2404 @param EAX Lower 32-bits of MSR value.
2405 @param EDX Upper 32-bits of MSR value.
2407 <b>Example usage</b>
2411 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
2412 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);
2414 @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
2416 #define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97
2420 Package. Uncore C-box 12 perfmon counter 2.
2422 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)
2423 @param EAX Lower 32-bits of MSR value.
2424 @param EDX Upper 32-bits of MSR value.
2426 <b>Example usage</b>
2430 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
2431 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);
2433 @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
2435 #define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98
2439 Package. Uncore C-box 12 perfmon counter 3.
2441 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)
2442 @param EAX Lower 32-bits of MSR value.
2443 @param EDX Upper 32-bits of MSR value.
2445 <b>Example usage</b>
2449 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
2450 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);
2452 @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
2454 #define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99
2458 Package. Uncore C-box 12 perfmon box wide filter1.
2460 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)
2461 @param EAX Lower 32-bits of MSR value.
2462 @param EDX Upper 32-bits of MSR value.
2464 <b>Example usage</b>
2468 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
2469 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);
2471 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
2473 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A
2477 Package. Uncore C-box 13 perfmon local box wide control.
2479 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)
2480 @param EAX Lower 32-bits of MSR value.
2481 @param EDX Upper 32-bits of MSR value.
2483 <b>Example usage</b>
2487 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
2488 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);
2490 @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
2492 #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4
2496 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
2498 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)
2499 @param EAX Lower 32-bits of MSR value.
2500 @param EDX Upper 32-bits of MSR value.
2502 <b>Example usage</b>
2506 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
2507 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);
2509 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
2511 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0
2515 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
2517 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)
2518 @param EAX Lower 32-bits of MSR value.
2519 @param EDX Upper 32-bits of MSR value.
2521 <b>Example usage</b>
2525 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
2526 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);
2528 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
2530 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1
2534 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
2536 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)
2537 @param EAX Lower 32-bits of MSR value.
2538 @param EDX Upper 32-bits of MSR value.
2540 <b>Example usage</b>
2544 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
2545 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);
2547 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
2549 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2
2553 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
2555 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)
2556 @param EAX Lower 32-bits of MSR value.
2557 @param EDX Upper 32-bits of MSR value.
2559 <b>Example usage</b>
2563 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
2564 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);
2566 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
2568 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3
2572 Package. Uncore C-box 13 perfmon box wide filter.
2574 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)
2575 @param EAX Lower 32-bits of MSR value.
2576 @param EDX Upper 32-bits of MSR value.
2578 <b>Example usage</b>
2582 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
2583 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);
2585 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.
2587 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4
2591 Package. Uncore C-box 13 perfmon counter 0.
2593 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)
2594 @param EAX Lower 32-bits of MSR value.
2595 @param EDX Upper 32-bits of MSR value.
2597 <b>Example usage</b>
2601 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
2602 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);
2604 @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
2606 #define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6
2610 Package. Uncore C-box 13 perfmon counter 1.
2612 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)
2613 @param EAX Lower 32-bits of MSR value.
2614 @param EDX Upper 32-bits of MSR value.
2616 <b>Example usage</b>
2620 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
2621 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);
2623 @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
2625 #define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7
2629 Package. Uncore C-box 13 perfmon counter 2.
2631 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)
2632 @param EAX Lower 32-bits of MSR value.
2633 @param EDX Upper 32-bits of MSR value.
2635 <b>Example usage</b>
2639 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
2640 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);
2642 @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
2644 #define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8
2648 Package. Uncore C-box 13 perfmon counter 3.
2650 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)
2651 @param EAX Lower 32-bits of MSR value.
2652 @param EDX Upper 32-bits of MSR value.
2654 <b>Example usage</b>
2658 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
2659 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);
2661 @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
2663 #define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9
2667 Package. Uncore C-box 13 perfmon box wide filter1.
2669 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)
2670 @param EAX Lower 32-bits of MSR value.
2671 @param EDX Upper 32-bits of MSR value.
2673 <b>Example usage</b>
2677 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
2678 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);
2680 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
2682 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA
2686 Package. Uncore C-box 14 perfmon local box wide control.
2688 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)
2689 @param EAX Lower 32-bits of MSR value.
2690 @param EDX Upper 32-bits of MSR value.
2692 <b>Example usage</b>
2696 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
2697 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);
2699 @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
2701 #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4
2705 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
2707 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)
2708 @param EAX Lower 32-bits of MSR value.
2709 @param EDX Upper 32-bits of MSR value.
2711 <b>Example usage</b>
2715 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
2716 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);
2718 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
2720 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0
2724 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
2726 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)
2727 @param EAX Lower 32-bits of MSR value.
2728 @param EDX Upper 32-bits of MSR value.
2730 <b>Example usage</b>
2734 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
2735 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);
2737 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
2739 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1
2743 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
2745 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)
2746 @param EAX Lower 32-bits of MSR value.
2747 @param EDX Upper 32-bits of MSR value.
2749 <b>Example usage</b>
2753 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
2754 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);
2756 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
2758 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2
2762 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
2764 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)
2765 @param EAX Lower 32-bits of MSR value.
2766 @param EDX Upper 32-bits of MSR value.
2768 <b>Example usage</b>
2772 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
2773 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);
2775 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
2777 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3
2781 Package. Uncore C-box 14 perfmon box wide filter.
2783 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)
2784 @param EAX Lower 32-bits of MSR value.
2785 @param EDX Upper 32-bits of MSR value.
2787 <b>Example usage</b>
2791 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
2792 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);
2794 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
2796 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4
2800 Package. Uncore C-box 14 perfmon counter 0.
2802 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)
2803 @param EAX Lower 32-bits of MSR value.
2804 @param EDX Upper 32-bits of MSR value.
2806 <b>Example usage</b>
2810 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
2811 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);
2813 @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
2815 #define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6
2819 Package. Uncore C-box 14 perfmon counter 1.
2821 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)
2822 @param EAX Lower 32-bits of MSR value.
2823 @param EDX Upper 32-bits of MSR value.
2825 <b>Example usage</b>
2829 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
2830 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);
2832 @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
2834 #define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7
2838 Package. Uncore C-box 14 perfmon counter 2.
2840 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)
2841 @param EAX Lower 32-bits of MSR value.
2842 @param EDX Upper 32-bits of MSR value.
2844 <b>Example usage</b>
2848 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
2849 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);
2851 @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
2853 #define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8
2857 Package. Uncore C-box 14 perfmon counter 3.
2859 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)
2860 @param EAX Lower 32-bits of MSR value.
2861 @param EDX Upper 32-bits of MSR value.
2863 <b>Example usage</b>
2867 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
2868 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);
2870 @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
2872 #define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9
2876 Package. Uncore C-box 14 perfmon box wide filter1.
2878 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)
2879 @param EAX Lower 32-bits of MSR value.
2880 @param EDX Upper 32-bits of MSR value.
2882 <b>Example usage</b>
2886 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
2887 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);
2889 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
2891 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA