2 MSR Definitions for Intel processors based on the Nehalem microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5.
24 #ifndef __NEHALEM_MSR_H__
25 #define __NEHALEM_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Package. Model Specific Platform ID (R).
32 @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
40 MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
44 @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
46 #define MSR_NEHALEM_PLATFORM_ID 0x00000017
49 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID
53 /// Individual bit fields
59 /// [Bits 52:50] See Table 35-2.
65 /// All bit fields as a 64-bit value
68 } MSR_NEHALEM_PLATFORM_ID_REGISTER
;
72 Thread. SMI Counter (R/O).
74 @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)
75 @param EAX Lower 32-bits of MSR value.
76 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
77 @param EDX Upper 32-bits of MSR value.
78 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
82 MSR_NEHALEM_SMI_COUNT_REGISTER Msr;
84 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
86 @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
88 #define MSR_NEHALEM_SMI_COUNT 0x00000034
91 MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT
95 /// Individual bit fields
99 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
106 /// All bit fields as a 32-bit value
110 /// All bit fields as a 64-bit value
113 } MSR_NEHALEM_SMI_COUNT_REGISTER
;
117 Package. see http://biosbits.org.
119 @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)
120 @param EAX Lower 32-bits of MSR value.
121 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
122 @param EDX Upper 32-bits of MSR value.
123 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
127 MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;
129 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
130 AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
132 @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
134 #define MSR_NEHALEM_PLATFORM_INFO 0x000000CE
137 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO
141 /// Individual bit fields
146 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
147 /// of the frequency that invariant TSC runs at. The invariant TSC
148 /// frequency can be computed by multiplying this ratio by 133.33 MHz.
150 UINT32 MaximumNonTurboRatio
:8;
153 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
154 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
155 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
156 /// Turbo mode is disabled.
160 /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)
161 /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are
162 /// programmable, and when set to 0, indicates TDC and TDP Limits for
163 /// Turbo mode are not programmable.
165 UINT32 TDC_TDPLimit
:1;
169 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
170 /// minimum ratio (maximum efficiency) that the processor can operates, in
171 /// units of 133.33MHz.
173 UINT32 MaximumEfficiencyRatio
:8;
177 /// All bit fields as a 64-bit value
180 } MSR_NEHALEM_PLATFORM_INFO_REGISTER
;
184 Core. C-State Configuration Control (R/W) Note: C-state values are
185 processor specific C-state code names, unrelated to MWAIT extension C-state
186 parameters or ACPI CStates. See http://biosbits.org.
188 @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)
189 @param EAX Lower 32-bits of MSR value.
190 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
191 @param EDX Upper 32-bits of MSR value.
192 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
196 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
198 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
199 AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
201 @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
203 #define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2
206 MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL
210 /// Individual bit fields
214 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
215 /// processor-specific C-state code name (consuming the least power). for
216 /// the package. The default is set as factory-configured package C-state
217 /// limit. The following C-state code name encodings are supported: 000b:
218 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
219 /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package
220 /// C-state limit. Note: This field cannot be used to limit package
226 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
227 /// IO_read instructions sent to IO register specified by
228 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
233 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
234 /// until next reset.
239 /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores
240 /// in a deep C-State will wake only when the event message is destined
241 /// for that core. When 0, all processor cores in a deep C-State will wake
242 /// for an event message.
244 UINT32 InterruptFiltering
:1;
246 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
247 /// will conditionally demote C6/C7 requests to C3 based on uncore
248 /// auto-demote information.
250 UINT32 C3AutoDemotion
:1;
252 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
253 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
254 /// auto-demote information.
256 UINT32 C1AutoDemotion
:1;
261 /// All bit fields as a 32-bit value
265 /// All bit fields as a 64-bit value
268 } MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
;
272 Core. Power Management IO Redirection in C-state (R/W) See
275 @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)
276 @param EAX Lower 32-bits of MSR value.
277 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
278 @param EDX Upper 32-bits of MSR value.
279 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
283 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;
285 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
286 AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
288 @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
290 #define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4
293 MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE
297 /// Individual bit fields
301 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
302 /// visible to software for IO redirection. If IO MWAIT Redirection is
303 /// enabled, reads to this address will be consumed by the power
304 /// management logic and decoded to MWAIT instructions. When IO port
305 /// address redirection is enabled, this is the IO port address reported
306 /// to the OS/software.
310 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
311 /// maximum C-State code name to be included when IO read to MWAIT
312 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
313 /// is the max C-State to include 001b - C6 is the max C-State to include
314 /// 010b - C7 is the max C-State to include.
316 UINT32 CStateRange
:3;
321 /// All bit fields as a 32-bit value
325 /// All bit fields as a 64-bit value
328 } MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER
;
332 Enable Misc. Processor Features (R/W) Allows a variety of processor
333 functions to be enabled and disabled.
335 @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)
336 @param EAX Lower 32-bits of MSR value.
337 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
338 @param EDX Upper 32-bits of MSR value.
339 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
343 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;
345 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
346 AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
348 @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
350 #define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0
353 MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE
357 /// Individual bit fields
361 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
363 UINT32 FastStrings
:1;
366 /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
369 UINT32 AutomaticThermalControlCircuit
:1;
372 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
374 UINT32 PerformanceMonitoring
:1;
377 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
381 /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See
387 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
393 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
398 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
400 UINT32 LimitCpuidMaxval
:1;
402 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
404 UINT32 xTPR_Message_Disable
:1;
408 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
413 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
414 /// that support Intel Turbo Boost Technology, the turbo mode feature is
415 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
416 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
417 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
418 /// the power-on default value is used by BIOS to detect hardware support
419 /// of turbo mode. If power-on default value is 1, turbo mode is available
420 /// in the processor. If power-on default value is 0, turbo mode is not
423 UINT32 TurboModeDisable
:1;
424 UINT32 Reserved10
:25;
427 /// All bit fields as a 64-bit value
430 } MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER
;
436 @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)
437 @param EAX Lower 32-bits of MSR value.
438 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
439 @param EDX Upper 32-bits of MSR value.
440 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
444 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;
446 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
447 AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
449 @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
451 #define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2
454 MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET
458 /// Individual bit fields
463 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
464 /// PROCHOT# will be asserted. The value is degree C.
466 UINT32 TemperatureTarget
:8;
471 /// All bit fields as a 32-bit value
475 /// All bit fields as a 64-bit value
478 } MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER
;
482 Miscellaneous Feature Control (R/W).
484 @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)
485 @param EAX Lower 32-bits of MSR value.
486 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
487 @param EDX Upper 32-bits of MSR value.
488 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
492 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;
494 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
495 AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
497 @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
499 #define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4
502 MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL
506 /// Individual bit fields
510 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
511 /// L2 hardware prefetcher, which fetches additional lines of code or data
512 /// into the L2 cache.
514 UINT32 L2HardwarePrefetcherDisable
:1;
516 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
517 /// disables the adjacent cache line prefetcher, which fetches the cache
518 /// line that comprises a cache line pair (128 bytes).
520 UINT32 L2AdjacentCacheLinePrefetcherDisable
:1;
522 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
523 /// the L1 data cache prefetcher, which fetches the next cache line into
526 UINT32 DCUHardwarePrefetcherDisable
:1;
528 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
529 /// data cache IP prefetcher, which uses sequential load history (based on
530 /// instruction Pointer of previous loads) to determine whether to
531 /// prefetch additional lines.
533 UINT32 DCUIPPrefetcherDisable
:1;
538 /// All bit fields as a 32-bit value
542 /// All bit fields as a 64-bit value
545 } MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER
;
549 Thread. Offcore Response Event Select Register (R/W).
551 @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)
552 @param EAX Lower 32-bits of MSR value.
553 @param EDX Upper 32-bits of MSR value.
559 Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
560 AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
562 @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
564 #define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6
568 See http://biosbits.org.
570 @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)
571 @param EAX Lower 32-bits of MSR value.
572 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
573 @param EDX Upper 32-bits of MSR value.
574 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
578 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;
580 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
581 AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
583 @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
585 #define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA
588 MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT
592 /// Individual bit fields
596 /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,
597 /// enables hardware coordination of Enhanced Intel Speedstep Technology
598 /// request from processor cores; When 1, disables hardware coordination
599 /// of Enhanced Intel Speedstep Technology requests.
601 UINT32 EISTHardwareCoordinationDisable
:1;
603 /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes
604 /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with
605 /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by
606 /// CPUID.(EAX=06h):ECX[3].
608 UINT32 EnergyPerformanceBiasEnable
:1;
613 /// All bit fields as a 32-bit value
617 /// All bit fields as a 64-bit value
620 } MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
;
624 See http://biosbits.org.
626 @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)
627 @param EAX Lower 32-bits of MSR value.
628 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
629 @param EDX Upper 32-bits of MSR value.
630 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
634 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;
636 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
637 AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
639 @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.
641 #define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC
644 MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT
648 /// Individual bit fields
652 /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt
657 /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0
658 /// indicates override is not active, and a value = 1 indicates active.
660 UINT32 TDPLimitOverrideEnable
:1;
662 /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp
667 /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0
668 /// indicates override is not active, and a value = 1 indicates active.
670 UINT32 TDCLimitOverrideEnable
:1;
674 /// All bit fields as a 32-bit value
678 /// All bit fields as a 64-bit value
681 } MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
;
685 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
686 RW if MSR_PLATFORM_INFO.[28] = 1.
688 @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)
689 @param EAX Lower 32-bits of MSR value.
690 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
691 @param EDX Upper 32-bits of MSR value.
692 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
696 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;
698 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
700 @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
702 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD
705 MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT
709 /// Individual bit fields
713 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
714 /// limit of 1 core active.
718 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
719 /// limit of 2 core active.
723 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
724 /// limit of 3 core active.
728 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
729 /// limit of 4 core active.
735 /// All bit fields as a 32-bit value
739 /// All bit fields as a 64-bit value
742 } MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER
;
746 Core. Last Branch Record Filtering Select Register (R/W) See Section
747 17.6.2, "Filtering of Last Branch Records.".
749 @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)
750 @param EAX Lower 32-bits of MSR value.
751 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
752 @param EDX Upper 32-bits of MSR value.
753 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
757 MSR_NEHALEM_LBR_SELECT_REGISTER Msr;
759 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
760 AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
762 @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
764 #define MSR_NEHALEM_LBR_SELECT 0x000001C8
767 MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT
771 /// Individual bit fields
775 /// [Bit 0] CPL_EQ_0.
779 /// [Bit 1] CPL_NEQ_0.
787 /// [Bit 3] NEAR_REL_CALL.
789 UINT32 NEAR_REL_CALL
:1;
791 /// [Bit 4] NEAR_IND_CALL.
793 UINT32 NEAR_IND_CALL
:1;
795 /// [Bit 5] NEAR_RET.
799 /// [Bit 6] NEAR_IND_JMP.
801 UINT32 NEAR_IND_JMP
:1;
803 /// [Bit 7] NEAR_REL_JMP.
805 UINT32 NEAR_REL_JMP
:1;
807 /// [Bit 8] FAR_BRANCH.
814 /// All bit fields as a 32-bit value
818 /// All bit fields as a 64-bit value
821 } MSR_NEHALEM_LBR_SELECT_REGISTER
;
825 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
826 that points to the MSR containing the most recent branch record. See
827 MSR_LASTBRANCH_0_FROM_IP (at 680H).
829 @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)
830 @param EAX Lower 32-bits of MSR value.
831 @param EDX Upper 32-bits of MSR value.
837 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
838 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
840 @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
842 #define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9
846 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
847 last branch instruction that the processor executed prior to the last
848 exception that was generated or the last interrupt that was handled.
850 @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)
851 @param EAX Lower 32-bits of MSR value.
852 @param EDX Upper 32-bits of MSR value.
858 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
860 @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
862 #define MSR_NEHALEM_LER_FROM_LIP 0x000001DD
866 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
867 to the target of the last branch instruction that the processor executed
868 prior to the last exception that was generated or the last interrupt that
871 @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)
872 @param EAX Lower 32-bits of MSR value.
873 @param EDX Upper 32-bits of MSR value.
879 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);
881 @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
883 #define MSR_NEHALEM_LER_TO_LIP 0x000001DE
887 Core. Power Control Register. See http://biosbits.org.
889 @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)
890 @param EAX Lower 32-bits of MSR value.
891 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
892 @param EDX Upper 32-bits of MSR value.
893 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
897 MSR_NEHALEM_POWER_CTL_REGISTER Msr;
899 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
900 AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);
902 @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.
904 #define MSR_NEHALEM_POWER_CTL 0x000001FC
907 MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL
911 /// Individual bit fields
916 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the
917 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
918 /// operating point when all execution cores enter MWAIT (C1).
925 /// All bit fields as a 32-bit value
929 /// All bit fields as a 64-bit value
932 } MSR_NEHALEM_POWER_CTL_REGISTER
;
936 Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
939 @param ECX MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS (0x0000038E)
940 @param EAX Lower 32-bits of MSR value.
941 @param EDX Upper 32-bits of MSR value.
947 Msr = AsmReadMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS);
948 AsmWriteMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS, Msr);
950 @note MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
952 #define MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS 0x0000038E
958 @param ECX MSR_NEHALEM_PERF_GLOBAL_STAUS (0x0000038E)
959 @param EAX Lower 32-bits of MSR value.
960 Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.
961 @param EDX Upper 32-bits of MSR value.
962 Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.
966 MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER Msr;
968 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STAUS);
970 @note MSR_NEHALEM_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.
972 #define MSR_NEHALEM_PERF_GLOBAL_STAUS 0x0000038E
975 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STAUS
979 /// Individual bit fields
985 /// [Bit 61] UNC_Ovf Uncore overflowed if 1.
991 /// All bit fields as a 64-bit value
994 } MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER
;
1000 @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)
1001 @param EAX Lower 32-bits of MSR value.
1002 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
1003 @param EDX Upper 32-bits of MSR value.
1004 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
1006 <b>Example usage</b>
1008 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1010 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
1011 AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1013 @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
1015 #define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390
1018 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL
1022 /// Individual bit fields
1025 UINT32 Reserved1
:32;
1026 UINT32 Reserved2
:29;
1028 /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.
1030 UINT32 Ovf_Uncore
:1;
1034 /// All bit fields as a 64-bit value
1037 } MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1041 Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
1043 @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
1044 @param EAX Lower 32-bits of MSR value.
1045 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1046 @param EDX Upper 32-bits of MSR value.
1047 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1049 <b>Example usage</b>
1051 MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;
1053 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
1054 AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);
1056 @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1058 #define MSR_NEHALEM_PEBS_ENABLE 0x000003F1
1061 MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE
1065 /// Individual bit fields
1069 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1071 UINT32 PEBS_EN_PMC0
:1;
1073 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1075 UINT32 PEBS_EN_PMC1
:1;
1077 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1079 UINT32 PEBS_EN_PMC2
:1;
1081 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1083 UINT32 PEBS_EN_PMC3
:1;
1084 UINT32 Reserved1
:28;
1086 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1088 UINT32 LL_EN_PMC0
:1;
1090 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1092 UINT32 LL_EN_PMC1
:1;
1094 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1096 UINT32 LL_EN_PMC2
:1;
1098 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1100 UINT32 LL_EN_PMC3
:1;
1101 UINT32 Reserved2
:28;
1104 /// All bit fields as a 64-bit value
1107 } MSR_NEHALEM_PEBS_ENABLE_REGISTER
;
1111 Thread. See Section 18.7.1.2, "Load Latency Performance Monitoring
1114 @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
1115 @param EAX Lower 32-bits of MSR value.
1116 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1117 @param EDX Upper 32-bits of MSR value.
1118 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1120 <b>Example usage</b>
1122 MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;
1124 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
1125 AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);
1127 @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
1129 #define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6
1132 MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT
1136 /// Individual bit fields
1140 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1141 /// that will be counted. (R/W).
1143 UINT32 MinimumThreshold
:16;
1144 UINT32 Reserved1
:16;
1145 UINT32 Reserved2
:32;
1148 /// All bit fields as a 32-bit value
1152 /// All bit fields as a 64-bit value
1155 } MSR_NEHALEM_PEBS_LD_LAT_REGISTER
;
1159 Package. Note: C-state values are processor specific C-state code names,
1160 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1161 Residency Counter. (R/O) Value since last reset that this package is in
1162 processor-specific C3 states. Count at the same frequency as the TSC.
1164 @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)
1165 @param EAX Lower 32-bits of MSR value.
1166 @param EDX Upper 32-bits of MSR value.
1168 <b>Example usage</b>
1172 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);
1173 AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);
1175 @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1177 #define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8
1181 Package. Note: C-state values are processor specific C-state code names,
1182 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1183 Residency Counter. (R/O) Value since last reset that this package is in
1184 processor-specific C6 states. Count at the same frequency as the TSC.
1186 @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)
1187 @param EAX Lower 32-bits of MSR value.
1188 @param EDX Upper 32-bits of MSR value.
1190 <b>Example usage</b>
1194 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);
1195 AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);
1197 @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1199 #define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9
1203 Package. Note: C-state values are processor specific C-state code names,
1204 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1205 Residency Counter. (R/O) Value since last reset that this package is in
1206 processor-specific C7 states. Count at the same frequency as the TSC.
1208 @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)
1209 @param EAX Lower 32-bits of MSR value.
1210 @param EDX Upper 32-bits of MSR value.
1212 <b>Example usage</b>
1216 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);
1217 AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);
1219 @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1221 #define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA
1225 Core. Note: C-state values are processor specific C-state code names,
1226 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1227 Residency Counter. (R/O) Value since last reset that this core is in
1228 processor-specific C3 states. Count at the same frequency as the TSC.
1230 @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)
1231 @param EAX Lower 32-bits of MSR value.
1232 @param EDX Upper 32-bits of MSR value.
1234 <b>Example usage</b>
1238 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);
1239 AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);
1241 @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1243 #define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC
1247 Core. Note: C-state values are processor specific C-state code names,
1248 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1249 Residency Counter. (R/O) Value since last reset that this core is in
1250 processor-specific C6 states. Count at the same frequency as the TSC.
1252 @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)
1253 @param EAX Lower 32-bits of MSR value.
1254 @param EDX Upper 32-bits of MSR value.
1256 <b>Example usage</b>
1260 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);
1261 AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);
1263 @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1265 #define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD
1269 See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".
1271 @param ECX MSR_NEHALEM_MCi_MISC
1272 @param EAX Lower 32-bits of MSR value.
1273 @param EDX Upper 32-bits of MSR value.
1275 <b>Example usage</b>
1279 Msr = AsmReadMsr64 (MSR_NEHALEM_MC0_MISC);
1280 AsmWriteMsr64 (MSR_NEHALEM_MC0_MISC, Msr);
1282 @note MSR_NEHALEM_MC0_MISC is defined as MSR_MC0_MISC in SDM.
1283 MSR_NEHALEM_MC1_MISC is defined as MSR_MC1_MISC in SDM.
1284 MSR_NEHALEM_MC2_MISC is defined as MSR_MC2_MISC in SDM.
1285 MSR_NEHALEM_MC3_MISC is defined as MSR_MC3_MISC in SDM.
1286 MSR_NEHALEM_MC4_MISC is defined as MSR_MC4_MISC in SDM.
1287 MSR_NEHALEM_MC5_MISC is defined as MSR_MC5_MISC in SDM.
1288 MSR_NEHALEM_MC6_MISC is defined as MSR_MC6_MISC in SDM.
1289 MSR_NEHALEM_MC7_MISC is defined as MSR_MC7_MISC in SDM.
1290 MSR_NEHALEM_MC8_MISC is defined as MSR_MC8_MISC in SDM.
1291 MSR_NEHALEM_MC9_MISC is defined as MSR_MC9_MISC in SDM.
1292 MSR_NEHALEM_MC10_MISC is defined as MSR_MC10_MISC in SDM.
1293 MSR_NEHALEM_MC11_MISC is defined as MSR_MC11_MISC in SDM.
1294 MSR_NEHALEM_MC12_MISC is defined as MSR_MC12_MISC in SDM.
1295 MSR_NEHALEM_MC13_MISC is defined as MSR_MC13_MISC in SDM.
1296 MSR_NEHALEM_MC14_MISC is defined as MSR_MC14_MISC in SDM.
1297 MSR_NEHALEM_MC15_MISC is defined as MSR_MC15_MISC in SDM.
1298 MSR_NEHALEM_MC16_MISC is defined as MSR_MC16_MISC in SDM.
1299 MSR_NEHALEM_MC17_MISC is defined as MSR_MC17_MISC in SDM.
1300 MSR_NEHALEM_MC18_MISC is defined as MSR_MC18_MISC in SDM.
1301 MSR_NEHALEM_MC19_MISC is defined as MSR_MC19_MISC in SDM.
1302 MSR_NEHALEM_MC20_MISC is defined as MSR_MC20_MISC in SDM.
1303 MSR_NEHALEM_MC21_MISC is defined as MSR_MC21_MISC in SDM.
1306 #define MSR_NEHALEM_MC0_MISC 0x00000403
1307 #define MSR_NEHALEM_MC1_MISC 0x00000407
1308 #define MSR_NEHALEM_MC2_MISC 0x0000040B
1309 #define MSR_NEHALEM_MC3_MISC 0x0000040F
1310 #define MSR_NEHALEM_MC4_MISC 0x00000413
1311 #define MSR_NEHALEM_MC5_MISC 0x00000417
1312 #define MSR_NEHALEM_MC6_MISC 0x0000041B
1313 #define MSR_NEHALEM_MC7_MISC 0x0000041F
1314 #define MSR_NEHALEM_MC8_MISC 0x00000423
1315 #define MSR_NEHALEM_MC9_MISC 0x00000427
1316 #define MSR_NEHALEM_MC10_MISC 0x0000042B
1317 #define MSR_NEHALEM_MC11_MISC 0x0000042F
1318 #define MSR_NEHALEM_MC12_MISC 0x00000433
1319 #define MSR_NEHALEM_MC13_MISC 0x00000437
1320 #define MSR_NEHALEM_MC14_MISC 0x0000043B
1321 #define MSR_NEHALEM_MC15_MISC 0x0000043F
1322 #define MSR_NEHALEM_MC16_MISC 0x00000443
1323 #define MSR_NEHALEM_MC17_MISC 0x00000447
1324 #define MSR_NEHALEM_MC18_MISC 0x0000044B
1325 #define MSR_NEHALEM_MC19_MISC 0x0000044F
1326 #define MSR_NEHALEM_MC20_MISC 0x00000453
1327 #define MSR_NEHALEM_MC21_MISC 0x00000457
1332 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1334 @param ECX MSR_NEHALEM_MCi_CTL
1335 @param EAX Lower 32-bits of MSR value.
1336 @param EDX Upper 32-bits of MSR value.
1338 <b>Example usage</b>
1342 Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_CTL);
1343 AsmWriteMsr64 (MSR_NEHALEM_MC3_CTL, Msr);
1345 @note MSR_NEHALEM_MC3_CTL is defined as MSR_MC3_CTL in SDM.
1346 MSR_NEHALEM_MC4_CTL is defined as MSR_MC4_CTL in SDM.
1347 MSR_NEHALEM_MC5_CTL is defined as MSR_MC5_CTL in SDM.
1348 MSR_NEHALEM_MC6_CTL is defined as MSR_MC6_CTL in SDM.
1349 MSR_NEHALEM_MC7_CTL is defined as MSR_MC7_CTL in SDM.
1350 MSR_NEHALEM_MC8_CTL is defined as MSR_MC8_CTL in SDM.
1351 MSR_NEHALEM_MC9_CTL is defined as MSR_MC9_CTL in SDM.
1352 MSR_NEHALEM_MC10_CTL is defined as MSR_MC10_CTL in SDM.
1353 MSR_NEHALEM_MC11_CTL is defined as MSR_MC11_CTL in SDM.
1354 MSR_NEHALEM_MC12_CTL is defined as MSR_MC12_CTL in SDM.
1355 MSR_NEHALEM_MC13_CTL is defined as MSR_MC13_CTL in SDM.
1356 MSR_NEHALEM_MC14_CTL is defined as MSR_MC14_CTL in SDM.
1357 MSR_NEHALEM_MC15_CTL is defined as MSR_MC15_CTL in SDM.
1358 MSR_NEHALEM_MC16_CTL is defined as MSR_MC16_CTL in SDM.
1359 MSR_NEHALEM_MC17_CTL is defined as MSR_MC17_CTL in SDM.
1360 MSR_NEHALEM_MC18_CTL is defined as MSR_MC18_CTL in SDM.
1361 MSR_NEHALEM_MC19_CTL is defined as MSR_MC19_CTL in SDM.
1362 MSR_NEHALEM_MC20_CTL is defined as MSR_MC20_CTL in SDM.
1363 MSR_NEHALEM_MC21_CTL is defined as MSR_MC21_CTL in SDM.
1366 #define MSR_NEHALEM_MC3_CTL 0x0000040C
1367 #define MSR_NEHALEM_MC4_CTL 0x00000410
1368 #define MSR_NEHALEM_MC5_CTL 0x00000414
1369 #define MSR_NEHALEM_MC6_CTL 0x00000418
1370 #define MSR_NEHALEM_MC7_CTL 0x0000041C
1371 #define MSR_NEHALEM_MC8_CTL 0x00000420
1372 #define MSR_NEHALEM_MC9_CTL 0x00000424
1373 #define MSR_NEHALEM_MC10_CTL 0x00000428
1374 #define MSR_NEHALEM_MC11_CTL 0x0000042C
1375 #define MSR_NEHALEM_MC12_CTL 0x00000430
1376 #define MSR_NEHALEM_MC13_CTL 0x00000434
1377 #define MSR_NEHALEM_MC14_CTL 0x00000438
1378 #define MSR_NEHALEM_MC15_CTL 0x0000043C
1379 #define MSR_NEHALEM_MC16_CTL 0x00000440
1380 #define MSR_NEHALEM_MC17_CTL 0x00000444
1381 #define MSR_NEHALEM_MC18_CTL 0x00000448
1382 #define MSR_NEHALEM_MC19_CTL 0x0000044C
1383 #define MSR_NEHALEM_MC20_CTL 0x00000450
1384 #define MSR_NEHALEM_MC21_CTL 0x00000454
1389 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.
1391 @param ECX MSR_NEHALEM_MCi_STATUS (0x0000040D)
1392 @param EAX Lower 32-bits of MSR value.
1393 @param EDX Upper 32-bits of MSR value.
1395 <b>Example usage</b>
1399 Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_STATUS);
1400 AsmWriteMsr64 (MSR_NEHALEM_MC3_STATUS, Msr);
1402 @note MSR_NEHALEM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
1403 MSR_NEHALEM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
1404 MSR_NEHALEM_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
1405 MSR_NEHALEM_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
1406 MSR_NEHALEM_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.
1407 MSR_NEHALEM_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.
1408 MSR_NEHALEM_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.
1409 MSR_NEHALEM_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
1410 MSR_NEHALEM_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
1411 MSR_NEHALEM_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
1412 MSR_NEHALEM_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
1413 MSR_NEHALEM_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
1414 MSR_NEHALEM_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
1415 MSR_NEHALEM_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
1416 MSR_NEHALEM_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
1417 MSR_NEHALEM_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
1418 MSR_NEHALEM_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
1419 MSR_NEHALEM_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
1420 MSR_NEHALEM_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
1423 #define MSR_NEHALEM_MC3_STATUS 0x0000040D
1424 #define MSR_NEHALEM_MC4_STATUS 0x00000411
1425 #define MSR_NEHALEM_MC5_STATUS 0x00000415
1426 #define MSR_NEHALEM_MC6_STATUS 0x00000419
1427 #define MSR_NEHALEM_MC7_STATUS 0x0000041D
1428 #define MSR_NEHALEM_MC8_STATUS 0x00000421
1429 #define MSR_NEHALEM_MC9_STATUS 0x00000425
1430 #define MSR_NEHALEM_MC10_STATUS 0x00000429
1431 #define MSR_NEHALEM_MC11_STATUS 0x0000042D
1432 #define MSR_NEHALEM_MC12_STATUS 0x00000431
1433 #define MSR_NEHALEM_MC13_STATUS 0x00000435
1434 #define MSR_NEHALEM_MC14_STATUS 0x00000439
1435 #define MSR_NEHALEM_MC15_STATUS 0x0000043D
1436 #define MSR_NEHALEM_MC16_STATUS 0x00000441
1437 #define MSR_NEHALEM_MC17_STATUS 0x00000445
1438 #define MSR_NEHALEM_MC18_STATUS 0x00000449
1439 #define MSR_NEHALEM_MC19_STATUS 0x0000044D
1440 #define MSR_NEHALEM_MC20_STATUS 0x00000451
1441 #define MSR_NEHALEM_MC21_STATUS 0x00000455
1446 Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs."
1448 The MSR_MC3_ADDR register is either not implemented or contains no address
1449 if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not
1450 implemented in the processor, all reads and writes to this MSR will cause a
1451 general-protection exception.
1453 The MSR_MC4_ADDR register is either not implemented or contains no address
1454 if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not
1455 implemented in the processor, all reads and writes to this MSR will cause a
1456 general-protection exception.
1458 @param ECX MSR_NEHALEM_MC3_ADDR (0x0000040E)
1459 @param EAX Lower 32-bits of MSR value.
1460 @param EDX Upper 32-bits of MSR value.
1462 <b>Example usage</b>
1466 Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_ADDR);
1467 AsmWriteMsr64 (MSR_NEHALEM_MC3_ADDR, Msr);
1469 @note MSR_NEHALEM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
1470 MSR_NEHALEM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
1471 MSR_NEHALEM_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
1472 MSR_NEHALEM_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.
1473 MSR_NEHALEM_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.
1474 MSR_NEHALEM_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.
1475 MSR_NEHALEM_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.
1476 MSR_NEHALEM_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
1477 MSR_NEHALEM_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
1478 MSR_NEHALEM_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
1479 MSR_NEHALEM_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
1480 MSR_NEHALEM_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
1481 MSR_NEHALEM_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
1482 MSR_NEHALEM_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
1483 MSR_NEHALEM_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
1484 MSR_NEHALEM_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
1485 MSR_NEHALEM_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
1486 MSR_NEHALEM_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
1487 MSR_NEHALEM_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
1490 #define MSR_NEHALEM_MC3_ADDR 0x0000040E
1491 #define MSR_NEHALEM_MC4_ADDR 0x00000412
1492 #define MSR_NEHALEM_MC5_ADDR 0x00000416
1493 #define MSR_NEHALEM_MC6_ADDR 0x0000041A
1494 #define MSR_NEHALEM_MC7_ADDR 0x0000041E
1495 #define MSR_NEHALEM_MC8_ADDR 0x00000422
1496 #define MSR_NEHALEM_MC9_ADDR 0x00000426
1497 #define MSR_NEHALEM_MC10_ADDR 0x0000042A
1498 #define MSR_NEHALEM_MC11_ADDR 0x0000042E
1499 #define MSR_NEHALEM_MC12_ADDR 0x00000432
1500 #define MSR_NEHALEM_MC13_ADDR 0x00000436
1501 #define MSR_NEHALEM_MC14_ADDR 0x0000043A
1502 #define MSR_NEHALEM_MC15_ADDR 0x0000043E
1503 #define MSR_NEHALEM_MC16_ADDR 0x00000442
1504 #define MSR_NEHALEM_MC17_ADDR 0x00000446
1505 #define MSR_NEHALEM_MC18_ADDR 0x0000044A
1506 #define MSR_NEHALEM_MC19_ADDR 0x0000044E
1507 #define MSR_NEHALEM_MC20_ADDR 0x00000452
1508 #define MSR_NEHALEM_MC21_ADDR 0x00000456
1513 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1514 branch record registers on the last branch record stack. This part of the
1515 stack contains pointers to the source instruction for one of the last
1516 sixteen branches, exceptions, or interrupts taken by the processor. See
1517 also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR
1520 @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP
1521 @param EAX Lower 32-bits of MSR value.
1522 @param EDX Upper 32-bits of MSR value.
1524 <b>Example usage</b>
1528 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
1529 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);
1531 @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
1532 MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
1533 MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
1534 MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
1535 MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
1536 MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
1537 MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
1538 MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
1539 MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
1540 MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
1541 MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
1542 MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
1543 MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
1544 MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
1545 MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
1546 MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
1549 #define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680
1550 #define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681
1551 #define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682
1552 #define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683
1553 #define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684
1554 #define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685
1555 #define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686
1556 #define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687
1557 #define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688
1558 #define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689
1559 #define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A
1560 #define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B
1561 #define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C
1562 #define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D
1563 #define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E
1564 #define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F
1569 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1570 record registers on the last branch record stack. This part of the stack
1571 contains pointers to the destination instruction for one of the last sixteen
1572 branches, exceptions, or interrupts taken by the processor.
1574 @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP
1575 @param EAX Lower 32-bits of MSR value.
1576 @param EDX Upper 32-bits of MSR value.
1578 <b>Example usage</b>
1582 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
1583 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);
1585 @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
1586 MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
1587 MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
1588 MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
1589 MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
1590 MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
1591 MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
1592 MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
1593 MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
1594 MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
1595 MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
1596 MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
1597 MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
1598 MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
1599 MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
1600 MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
1603 #define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0
1604 #define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1
1605 #define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2
1606 #define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3
1607 #define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4
1608 #define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5
1609 #define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6
1610 #define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7
1611 #define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8
1612 #define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9
1613 #define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA
1614 #define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB
1615 #define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC
1616 #define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD
1617 #define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE
1618 #define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF
1625 @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)
1626 @param EAX Lower 32-bits of MSR value.
1627 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1628 @param EDX Upper 32-bits of MSR value.
1629 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1631 <b>Example usage</b>
1633 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;
1635 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);
1636 AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);
1638 @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.
1640 #define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301
1643 MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF
1647 /// Individual bit fields
1651 /// [Bit 0] From M to S (R/W).
1655 /// [Bit 1] From E to S (R/W).
1659 /// [Bit 2] From S to S (R/W).
1663 /// [Bit 3] From F to S (R/W).
1667 /// [Bit 4] From M to I (R/W).
1671 /// [Bit 5] From E to I (R/W).
1675 /// [Bit 6] From S to I (R/W).
1679 /// [Bit 7] From F to I (R/W).
1682 UINT32 Reserved1
:24;
1683 UINT32 Reserved2
:32;
1686 /// All bit fields as a 32-bit value
1690 /// All bit fields as a 64-bit value
1693 } MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
;
1697 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1700 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
1701 @param EAX Lower 32-bits of MSR value.
1702 @param EDX Upper 32-bits of MSR value.
1704 <b>Example usage</b>
1708 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);
1709 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);
1711 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.
1713 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391
1717 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1720 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
1721 @param EAX Lower 32-bits of MSR value.
1722 @param EDX Upper 32-bits of MSR value.
1724 <b>Example usage</b>
1728 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);
1729 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);
1731 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.
1733 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392
1737 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1740 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
1741 @param EAX Lower 32-bits of MSR value.
1742 @param EDX Upper 32-bits of MSR value.
1744 <b>Example usage</b>
1748 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);
1749 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);
1751 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.
1753 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393
1757 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1760 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
1761 @param EAX Lower 32-bits of MSR value.
1762 @param EDX Upper 32-bits of MSR value.
1764 <b>Example usage</b>
1768 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);
1769 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);
1771 @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.
1773 #define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394
1777 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1780 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
1781 @param EAX Lower 32-bits of MSR value.
1782 @param EDX Upper 32-bits of MSR value.
1784 <b>Example usage</b>
1788 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);
1789 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);
1791 @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.
1793 #define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395
1797 Package. See Section 18.7.2.3, "Uncore Address/Opcode Match MSR.".
1799 @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
1800 @param EAX Lower 32-bits of MSR value.
1801 @param EDX Upper 32-bits of MSR value.
1803 <b>Example usage</b>
1807 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);
1808 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);
1810 @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.
1812 #define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396
1816 Package. See Section 18.7.2.2, "Uncore Performance Event Configuration
1819 @param ECX MSR_NEHALEM_UNCORE_PMCi
1820 @param EAX Lower 32-bits of MSR value.
1821 @param EDX Upper 32-bits of MSR value.
1823 <b>Example usage</b>
1827 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
1828 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);
1830 @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.
1831 MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.
1832 MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.
1833 MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.
1834 MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.
1835 MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.
1836 MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.
1837 MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.
1840 #define MSR_NEHALEM_UNCORE_PMC0 0x000003B0
1841 #define MSR_NEHALEM_UNCORE_PMC1 0x000003B1
1842 #define MSR_NEHALEM_UNCORE_PMC2 0x000003B2
1843 #define MSR_NEHALEM_UNCORE_PMC3 0x000003B3
1844 #define MSR_NEHALEM_UNCORE_PMC4 0x000003B4
1845 #define MSR_NEHALEM_UNCORE_PMC5 0x000003B5
1846 #define MSR_NEHALEM_UNCORE_PMC6 0x000003B6
1847 #define MSR_NEHALEM_UNCORE_PMC7 0x000003B7
1851 Package. See Section 18.7.2.2, "Uncore Performance Event Configuration
1854 @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi
1855 @param EAX Lower 32-bits of MSR value.
1856 @param EDX Upper 32-bits of MSR value.
1858 <b>Example usage</b>
1862 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
1863 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);
1865 @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.
1866 MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.
1867 MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.
1868 MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.
1869 MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.
1870 MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.
1871 MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.
1872 MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.
1875 #define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0
1876 #define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1
1877 #define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2
1878 #define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3
1879 #define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4
1880 #define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5
1881 #define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6
1882 #define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7
1887 Package. Uncore W-box perfmon fixed counter.
1889 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)
1890 @param EAX Lower 32-bits of MSR value.
1891 @param EDX Upper 32-bits of MSR value.
1893 <b>Example usage</b>
1897 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);
1898 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);
1900 @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.
1902 #define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394
1906 Package. Uncore U-box perfmon fixed counter control MSR.
1908 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)
1909 @param EAX Lower 32-bits of MSR value.
1910 @param EDX Upper 32-bits of MSR value.
1912 <b>Example usage</b>
1916 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);
1917 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);
1919 @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.
1921 #define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395
1925 Package. Uncore U-box perfmon global control MSR.
1927 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)
1928 @param EAX Lower 32-bits of MSR value.
1929 @param EDX Upper 32-bits of MSR value.
1931 <b>Example usage</b>
1935 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);
1936 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);
1938 @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.
1940 #define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00
1944 Package. Uncore U-box perfmon global status MSR.
1946 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)
1947 @param EAX Lower 32-bits of MSR value.
1948 @param EDX Upper 32-bits of MSR value.
1950 <b>Example usage</b>
1954 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);
1955 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);
1957 @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.
1959 #define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01
1963 Package. Uncore U-box perfmon global overflow control MSR.
1965 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)
1966 @param EAX Lower 32-bits of MSR value.
1967 @param EDX Upper 32-bits of MSR value.
1969 <b>Example usage</b>
1973 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);
1974 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);
1976 @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.
1978 #define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02
1982 Package. Uncore U-box perfmon event select MSR.
1984 @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)
1985 @param EAX Lower 32-bits of MSR value.
1986 @param EDX Upper 32-bits of MSR value.
1988 <b>Example usage</b>
1992 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);
1993 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);
1995 @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.
1997 #define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10
2001 Package. Uncore U-box perfmon counter MSR.
2003 @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)
2004 @param EAX Lower 32-bits of MSR value.
2005 @param EDX Upper 32-bits of MSR value.
2007 <b>Example usage</b>
2011 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);
2012 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);
2014 @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.
2016 #define MSR_NEHALEM_U_PMON_CTR 0x00000C11
2020 Package. Uncore B-box 0 perfmon local box control MSR.
2022 @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)
2023 @param EAX Lower 32-bits of MSR value.
2024 @param EDX Upper 32-bits of MSR value.
2026 <b>Example usage</b>
2030 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);
2031 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);
2033 @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.
2035 #define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20
2039 Package. Uncore B-box 0 perfmon local box status MSR.
2041 @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)
2042 @param EAX Lower 32-bits of MSR value.
2043 @param EDX Upper 32-bits of MSR value.
2045 <b>Example usage</b>
2049 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);
2050 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);
2052 @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.
2054 #define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21
2058 Package. Uncore B-box 0 perfmon local box overflow control MSR.
2060 @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)
2061 @param EAX Lower 32-bits of MSR value.
2062 @param EDX Upper 32-bits of MSR value.
2064 <b>Example usage</b>
2068 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);
2069 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);
2071 @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.
2073 #define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22
2077 Package. Uncore B-box 0 perfmon event select MSR.
2079 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)
2080 @param EAX Lower 32-bits of MSR value.
2081 @param EDX Upper 32-bits of MSR value.
2083 <b>Example usage</b>
2087 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);
2088 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);
2090 @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.
2092 #define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30
2096 Package. Uncore B-box 0 perfmon counter MSR.
2098 @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)
2099 @param EAX Lower 32-bits of MSR value.
2100 @param EDX Upper 32-bits of MSR value.
2102 <b>Example usage</b>
2106 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);
2107 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);
2109 @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.
2111 #define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31
2115 Package. Uncore B-box 0 perfmon event select MSR.
2117 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)
2118 @param EAX Lower 32-bits of MSR value.
2119 @param EDX Upper 32-bits of MSR value.
2121 <b>Example usage</b>
2125 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);
2126 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);
2128 @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.
2130 #define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32
2134 Package. Uncore B-box 0 perfmon counter MSR.
2136 @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)
2137 @param EAX Lower 32-bits of MSR value.
2138 @param EDX Upper 32-bits of MSR value.
2140 <b>Example usage</b>
2144 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);
2145 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);
2147 @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.
2149 #define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33
2153 Package. Uncore B-box 0 perfmon event select MSR.
2155 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)
2156 @param EAX Lower 32-bits of MSR value.
2157 @param EDX Upper 32-bits of MSR value.
2159 <b>Example usage</b>
2163 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);
2164 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);
2166 @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.
2168 #define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34
2172 Package. Uncore B-box 0 perfmon counter MSR.
2174 @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)
2175 @param EAX Lower 32-bits of MSR value.
2176 @param EDX Upper 32-bits of MSR value.
2178 <b>Example usage</b>
2182 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);
2183 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);
2185 @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.
2187 #define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35
2191 Package. Uncore B-box 0 perfmon event select MSR.
2193 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)
2194 @param EAX Lower 32-bits of MSR value.
2195 @param EDX Upper 32-bits of MSR value.
2197 <b>Example usage</b>
2201 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);
2202 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);
2204 @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.
2206 #define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36
2210 Package. Uncore B-box 0 perfmon counter MSR.
2212 @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)
2213 @param EAX Lower 32-bits of MSR value.
2214 @param EDX Upper 32-bits of MSR value.
2216 <b>Example usage</b>
2220 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);
2221 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);
2223 @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.
2225 #define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37
2229 Package. Uncore S-box 0 perfmon local box control MSR.
2231 @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)
2232 @param EAX Lower 32-bits of MSR value.
2233 @param EDX Upper 32-bits of MSR value.
2235 <b>Example usage</b>
2239 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);
2240 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);
2242 @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.
2244 #define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40
2248 Package. Uncore S-box 0 perfmon local box status MSR.
2250 @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)
2251 @param EAX Lower 32-bits of MSR value.
2252 @param EDX Upper 32-bits of MSR value.
2254 <b>Example usage</b>
2258 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);
2259 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);
2261 @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.
2263 #define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41
2267 Package. Uncore S-box 0 perfmon local box overflow control MSR.
2269 @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)
2270 @param EAX Lower 32-bits of MSR value.
2271 @param EDX Upper 32-bits of MSR value.
2273 <b>Example usage</b>
2277 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);
2278 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);
2280 @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.
2282 #define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42
2286 Package. Uncore S-box 0 perfmon event select MSR.
2288 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)
2289 @param EAX Lower 32-bits of MSR value.
2290 @param EDX Upper 32-bits of MSR value.
2292 <b>Example usage</b>
2296 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);
2297 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);
2299 @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.
2301 #define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50
2305 Package. Uncore S-box 0 perfmon counter MSR.
2307 @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)
2308 @param EAX Lower 32-bits of MSR value.
2309 @param EDX Upper 32-bits of MSR value.
2311 <b>Example usage</b>
2315 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);
2316 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);
2318 @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
2320 #define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51
2324 Package. Uncore S-box 0 perfmon event select MSR.
2326 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)
2327 @param EAX Lower 32-bits of MSR value.
2328 @param EDX Upper 32-bits of MSR value.
2330 <b>Example usage</b>
2334 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);
2335 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);
2337 @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.
2339 #define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52
2343 Package. Uncore S-box 0 perfmon counter MSR.
2345 @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)
2346 @param EAX Lower 32-bits of MSR value.
2347 @param EDX Upper 32-bits of MSR value.
2349 <b>Example usage</b>
2353 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);
2354 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);
2356 @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
2358 #define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53
2362 Package. Uncore S-box 0 perfmon event select MSR.
2364 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)
2365 @param EAX Lower 32-bits of MSR value.
2366 @param EDX Upper 32-bits of MSR value.
2368 <b>Example usage</b>
2372 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);
2373 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);
2375 @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.
2377 #define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54
2381 Package. Uncore S-box 0 perfmon counter MSR.
2383 @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)
2384 @param EAX Lower 32-bits of MSR value.
2385 @param EDX Upper 32-bits of MSR value.
2387 <b>Example usage</b>
2391 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);
2392 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);
2394 @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
2396 #define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55
2400 Package. Uncore S-box 0 perfmon event select MSR.
2402 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)
2403 @param EAX Lower 32-bits of MSR value.
2404 @param EDX Upper 32-bits of MSR value.
2406 <b>Example usage</b>
2410 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);
2411 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);
2413 @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.
2415 #define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56
2419 Package. Uncore S-box 0 perfmon counter MSR.
2421 @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)
2422 @param EAX Lower 32-bits of MSR value.
2423 @param EDX Upper 32-bits of MSR value.
2425 <b>Example usage</b>
2429 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);
2430 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);
2432 @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
2434 #define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57
2438 Package. Uncore B-box 1 perfmon local box control MSR.
2440 @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)
2441 @param EAX Lower 32-bits of MSR value.
2442 @param EDX Upper 32-bits of MSR value.
2444 <b>Example usage</b>
2448 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);
2449 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);
2451 @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.
2453 #define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60
2457 Package. Uncore B-box 1 perfmon local box status MSR.
2459 @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)
2460 @param EAX Lower 32-bits of MSR value.
2461 @param EDX Upper 32-bits of MSR value.
2463 <b>Example usage</b>
2467 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);
2468 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);
2470 @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.
2472 #define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61
2476 Package. Uncore B-box 1 perfmon local box overflow control MSR.
2478 @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)
2479 @param EAX Lower 32-bits of MSR value.
2480 @param EDX Upper 32-bits of MSR value.
2482 <b>Example usage</b>
2486 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);
2487 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);
2489 @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.
2491 #define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62
2495 Package. Uncore B-box 1 perfmon event select MSR.
2497 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)
2498 @param EAX Lower 32-bits of MSR value.
2499 @param EDX Upper 32-bits of MSR value.
2501 <b>Example usage</b>
2505 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);
2506 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);
2508 @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.
2510 #define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70
2514 Package. Uncore B-box 1 perfmon counter MSR.
2516 @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)
2517 @param EAX Lower 32-bits of MSR value.
2518 @param EDX Upper 32-bits of MSR value.
2520 <b>Example usage</b>
2524 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);
2525 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);
2527 @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.
2529 #define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71
2533 Package. Uncore B-box 1 perfmon event select MSR.
2535 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)
2536 @param EAX Lower 32-bits of MSR value.
2537 @param EDX Upper 32-bits of MSR value.
2539 <b>Example usage</b>
2543 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);
2544 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);
2546 @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.
2548 #define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72
2552 Package. Uncore B-box 1 perfmon counter MSR.
2554 @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)
2555 @param EAX Lower 32-bits of MSR value.
2556 @param EDX Upper 32-bits of MSR value.
2558 <b>Example usage</b>
2562 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);
2563 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);
2565 @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.
2567 #define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73
2571 Package. Uncore B-box 1 perfmon event select MSR.
2573 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)
2574 @param EAX Lower 32-bits of MSR value.
2575 @param EDX Upper 32-bits of MSR value.
2577 <b>Example usage</b>
2581 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);
2582 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);
2584 @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.
2586 #define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74
2590 Package. Uncore B-box 1 perfmon counter MSR.
2592 @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)
2593 @param EAX Lower 32-bits of MSR value.
2594 @param EDX Upper 32-bits of MSR value.
2596 <b>Example usage</b>
2600 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);
2601 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);
2603 @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.
2605 #define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75
2609 Package. Uncore B-box 1vperfmon event select MSR.
2611 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)
2612 @param EAX Lower 32-bits of MSR value.
2613 @param EDX Upper 32-bits of MSR value.
2615 <b>Example usage</b>
2619 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);
2620 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);
2622 @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.
2624 #define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76
2628 Package. Uncore B-box 1 perfmon counter MSR.
2630 @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)
2631 @param EAX Lower 32-bits of MSR value.
2632 @param EDX Upper 32-bits of MSR value.
2634 <b>Example usage</b>
2638 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);
2639 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);
2641 @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.
2643 #define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77
2647 Package. Uncore W-box perfmon local box control MSR.
2649 @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)
2650 @param EAX Lower 32-bits of MSR value.
2651 @param EDX Upper 32-bits of MSR value.
2653 <b>Example usage</b>
2657 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);
2658 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);
2660 @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.
2662 #define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80
2666 Package. Uncore W-box perfmon local box status MSR.
2668 @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)
2669 @param EAX Lower 32-bits of MSR value.
2670 @param EDX Upper 32-bits of MSR value.
2672 <b>Example usage</b>
2676 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);
2677 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);
2679 @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.
2681 #define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81
2685 Package. Uncore W-box perfmon local box overflow control MSR.
2687 @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)
2688 @param EAX Lower 32-bits of MSR value.
2689 @param EDX Upper 32-bits of MSR value.
2691 <b>Example usage</b>
2695 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);
2696 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);
2698 @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.
2700 #define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82
2704 Package. Uncore W-box perfmon event select MSR.
2706 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)
2707 @param EAX Lower 32-bits of MSR value.
2708 @param EDX Upper 32-bits of MSR value.
2710 <b>Example usage</b>
2714 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);
2715 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);
2717 @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.
2719 #define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90
2723 Package. Uncore W-box perfmon counter MSR.
2725 @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)
2726 @param EAX Lower 32-bits of MSR value.
2727 @param EDX Upper 32-bits of MSR value.
2729 <b>Example usage</b>
2733 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);
2734 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);
2736 @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.
2738 #define MSR_NEHALEM_W_PMON_CTR0 0x00000C91
2742 Package. Uncore W-box perfmon event select MSR.
2744 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)
2745 @param EAX Lower 32-bits of MSR value.
2746 @param EDX Upper 32-bits of MSR value.
2748 <b>Example usage</b>
2752 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);
2753 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);
2755 @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.
2757 #define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92
2761 Package. Uncore W-box perfmon counter MSR.
2763 @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)
2764 @param EAX Lower 32-bits of MSR value.
2765 @param EDX Upper 32-bits of MSR value.
2767 <b>Example usage</b>
2771 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);
2772 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);
2774 @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.
2776 #define MSR_NEHALEM_W_PMON_CTR1 0x00000C93
2780 Package. Uncore W-box perfmon event select MSR.
2782 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)
2783 @param EAX Lower 32-bits of MSR value.
2784 @param EDX Upper 32-bits of MSR value.
2786 <b>Example usage</b>
2790 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);
2791 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);
2793 @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.
2795 #define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94
2799 Package. Uncore W-box perfmon counter MSR.
2801 @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)
2802 @param EAX Lower 32-bits of MSR value.
2803 @param EDX Upper 32-bits of MSR value.
2805 <b>Example usage</b>
2809 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);
2810 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);
2812 @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.
2814 #define MSR_NEHALEM_W_PMON_CTR2 0x00000C95
2818 Package. Uncore W-box perfmon event select MSR.
2820 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)
2821 @param EAX Lower 32-bits of MSR value.
2822 @param EDX Upper 32-bits of MSR value.
2824 <b>Example usage</b>
2828 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);
2829 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);
2831 @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.
2833 #define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96
2837 Package. Uncore W-box perfmon counter MSR.
2839 @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)
2840 @param EAX Lower 32-bits of MSR value.
2841 @param EDX Upper 32-bits of MSR value.
2843 <b>Example usage</b>
2847 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);
2848 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);
2850 @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.
2852 #define MSR_NEHALEM_W_PMON_CTR3 0x00000C97
2856 Package. Uncore M-box 0 perfmon local box control MSR.
2858 @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)
2859 @param EAX Lower 32-bits of MSR value.
2860 @param EDX Upper 32-bits of MSR value.
2862 <b>Example usage</b>
2866 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);
2867 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);
2869 @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.
2871 #define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0
2875 Package. Uncore M-box 0 perfmon local box status MSR.
2877 @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)
2878 @param EAX Lower 32-bits of MSR value.
2879 @param EDX Upper 32-bits of MSR value.
2881 <b>Example usage</b>
2885 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);
2886 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);
2888 @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.
2890 #define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1
2894 Package. Uncore M-box 0 perfmon local box overflow control MSR.
2896 @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)
2897 @param EAX Lower 32-bits of MSR value.
2898 @param EDX Upper 32-bits of MSR value.
2900 <b>Example usage</b>
2904 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);
2905 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);
2907 @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.
2909 #define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2
2913 Package. Uncore M-box 0 perfmon time stamp unit select MSR.
2915 @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)
2916 @param EAX Lower 32-bits of MSR value.
2917 @param EDX Upper 32-bits of MSR value.
2919 <b>Example usage</b>
2923 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);
2924 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);
2926 @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.
2928 #define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4
2932 Package. Uncore M-box 0 perfmon DSP unit select MSR.
2934 @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)
2935 @param EAX Lower 32-bits of MSR value.
2936 @param EDX Upper 32-bits of MSR value.
2938 <b>Example usage</b>
2942 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);
2943 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);
2945 @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.
2947 #define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5
2951 Package. Uncore M-box 0 perfmon ISS unit select MSR.
2953 @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)
2954 @param EAX Lower 32-bits of MSR value.
2955 @param EDX Upper 32-bits of MSR value.
2957 <b>Example usage</b>
2961 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);
2962 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);
2964 @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.
2966 #define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6
2970 Package. Uncore M-box 0 perfmon MAP unit select MSR.
2972 @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)
2973 @param EAX Lower 32-bits of MSR value.
2974 @param EDX Upper 32-bits of MSR value.
2976 <b>Example usage</b>
2980 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);
2981 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);
2983 @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.
2985 #define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7
2989 Package. Uncore M-box 0 perfmon MIC THR select MSR.
2991 @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)
2992 @param EAX Lower 32-bits of MSR value.
2993 @param EDX Upper 32-bits of MSR value.
2995 <b>Example usage</b>
2999 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);
3000 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);
3002 @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.
3004 #define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8
3008 Package. Uncore M-box 0 perfmon PGT unit select MSR.
3010 @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)
3011 @param EAX Lower 32-bits of MSR value.
3012 @param EDX Upper 32-bits of MSR value.
3014 <b>Example usage</b>
3018 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);
3019 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);
3021 @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.
3023 #define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9
3027 Package. Uncore M-box 0 perfmon PLD unit select MSR.
3029 @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)
3030 @param EAX Lower 32-bits of MSR value.
3031 @param EDX Upper 32-bits of MSR value.
3033 <b>Example usage</b>
3037 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);
3038 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);
3040 @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.
3042 #define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA
3046 Package. Uncore M-box 0 perfmon ZDP unit select MSR.
3048 @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)
3049 @param EAX Lower 32-bits of MSR value.
3050 @param EDX Upper 32-bits of MSR value.
3052 <b>Example usage</b>
3056 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);
3057 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);
3059 @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.
3061 #define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB
3065 Package. Uncore M-box 0 perfmon event select MSR.
3067 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)
3068 @param EAX Lower 32-bits of MSR value.
3069 @param EDX Upper 32-bits of MSR value.
3071 <b>Example usage</b>
3075 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);
3076 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);
3078 @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.
3080 #define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0
3084 Package. Uncore M-box 0 perfmon counter MSR.
3086 @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)
3087 @param EAX Lower 32-bits of MSR value.
3088 @param EDX Upper 32-bits of MSR value.
3090 <b>Example usage</b>
3094 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);
3095 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);
3097 @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.
3099 #define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1
3103 Package. Uncore M-box 0 perfmon event select MSR.
3105 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)
3106 @param EAX Lower 32-bits of MSR value.
3107 @param EDX Upper 32-bits of MSR value.
3109 <b>Example usage</b>
3113 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);
3114 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);
3116 @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.
3118 #define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2
3122 Package. Uncore M-box 0 perfmon counter MSR.
3124 @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)
3125 @param EAX Lower 32-bits of MSR value.
3126 @param EDX Upper 32-bits of MSR value.
3128 <b>Example usage</b>
3132 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);
3133 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);
3135 @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.
3137 #define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3
3141 Package. Uncore M-box 0 perfmon event select MSR.
3143 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)
3144 @param EAX Lower 32-bits of MSR value.
3145 @param EDX Upper 32-bits of MSR value.
3147 <b>Example usage</b>
3151 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);
3152 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);
3154 @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.
3156 #define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4
3160 Package. Uncore M-box 0 perfmon counter MSR.
3162 @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)
3163 @param EAX Lower 32-bits of MSR value.
3164 @param EDX Upper 32-bits of MSR value.
3166 <b>Example usage</b>
3170 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);
3171 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);
3173 @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.
3175 #define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5
3179 Package. Uncore M-box 0 perfmon event select MSR.
3181 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)
3182 @param EAX Lower 32-bits of MSR value.
3183 @param EDX Upper 32-bits of MSR value.
3185 <b>Example usage</b>
3189 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);
3190 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);
3192 @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.
3194 #define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6
3198 Package. Uncore M-box 0 perfmon counter MSR.
3200 @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)
3201 @param EAX Lower 32-bits of MSR value.
3202 @param EDX Upper 32-bits of MSR value.
3204 <b>Example usage</b>
3208 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);
3209 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);
3211 @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.
3213 #define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7
3217 Package. Uncore M-box 0 perfmon event select MSR.
3219 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)
3220 @param EAX Lower 32-bits of MSR value.
3221 @param EDX Upper 32-bits of MSR value.
3223 <b>Example usage</b>
3227 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);
3228 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);
3230 @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.
3232 #define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8
3236 Package. Uncore M-box 0 perfmon counter MSR.
3238 @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)
3239 @param EAX Lower 32-bits of MSR value.
3240 @param EDX Upper 32-bits of MSR value.
3242 <b>Example usage</b>
3246 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);
3247 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);
3249 @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.
3251 #define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9
3255 Package. Uncore M-box 0 perfmon event select MSR.
3257 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)
3258 @param EAX Lower 32-bits of MSR value.
3259 @param EDX Upper 32-bits of MSR value.
3261 <b>Example usage</b>
3265 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);
3266 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);
3268 @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.
3270 #define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA
3274 Package. Uncore M-box 0 perfmon counter MSR.
3276 @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)
3277 @param EAX Lower 32-bits of MSR value.
3278 @param EDX Upper 32-bits of MSR value.
3280 <b>Example usage</b>
3284 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);
3285 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);
3287 @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.
3289 #define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB
3293 Package. Uncore S-box 1 perfmon local box control MSR.
3295 @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)
3296 @param EAX Lower 32-bits of MSR value.
3297 @param EDX Upper 32-bits of MSR value.
3299 <b>Example usage</b>
3303 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);
3304 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);
3306 @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.
3308 #define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0
3312 Package. Uncore S-box 1 perfmon local box status MSR.
3314 @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)
3315 @param EAX Lower 32-bits of MSR value.
3316 @param EDX Upper 32-bits of MSR value.
3318 <b>Example usage</b>
3322 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);
3323 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);
3325 @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.
3327 #define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1
3331 Package. Uncore S-box 1 perfmon local box overflow control MSR.
3333 @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)
3334 @param EAX Lower 32-bits of MSR value.
3335 @param EDX Upper 32-bits of MSR value.
3337 <b>Example usage</b>
3341 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);
3342 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);
3344 @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.
3346 #define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2
3350 Package. Uncore S-box 1 perfmon event select MSR.
3352 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)
3353 @param EAX Lower 32-bits of MSR value.
3354 @param EDX Upper 32-bits of MSR value.
3356 <b>Example usage</b>
3360 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);
3361 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);
3363 @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.
3365 #define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0
3369 Package. Uncore S-box 1 perfmon counter MSR.
3371 @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)
3372 @param EAX Lower 32-bits of MSR value.
3373 @param EDX Upper 32-bits of MSR value.
3375 <b>Example usage</b>
3379 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);
3380 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);
3382 @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
3384 #define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1
3388 Package. Uncore S-box 1 perfmon event select MSR.
3390 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)
3391 @param EAX Lower 32-bits of MSR value.
3392 @param EDX Upper 32-bits of MSR value.
3394 <b>Example usage</b>
3398 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);
3399 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);
3401 @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.
3403 #define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2
3407 Package. Uncore S-box 1 perfmon counter MSR.
3409 @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)
3410 @param EAX Lower 32-bits of MSR value.
3411 @param EDX Upper 32-bits of MSR value.
3413 <b>Example usage</b>
3417 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);
3418 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);
3420 @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
3422 #define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3
3426 Package. Uncore S-box 1 perfmon event select MSR.
3428 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)
3429 @param EAX Lower 32-bits of MSR value.
3430 @param EDX Upper 32-bits of MSR value.
3432 <b>Example usage</b>
3436 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);
3437 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);
3439 @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.
3441 #define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4
3445 Package. Uncore S-box 1 perfmon counter MSR.
3447 @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)
3448 @param EAX Lower 32-bits of MSR value.
3449 @param EDX Upper 32-bits of MSR value.
3451 <b>Example usage</b>
3455 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);
3456 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);
3458 @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
3460 #define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5
3464 Package. Uncore S-box 1 perfmon event select MSR.
3466 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)
3467 @param EAX Lower 32-bits of MSR value.
3468 @param EDX Upper 32-bits of MSR value.
3470 <b>Example usage</b>
3474 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);
3475 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);
3477 @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.
3479 #define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6
3483 Package. Uncore S-box 1 perfmon counter MSR.
3485 @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)
3486 @param EAX Lower 32-bits of MSR value.
3487 @param EDX Upper 32-bits of MSR value.
3489 <b>Example usage</b>
3493 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);
3494 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);
3496 @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
3498 #define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7
3502 Package. Uncore M-box 1 perfmon local box control MSR.
3504 @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)
3505 @param EAX Lower 32-bits of MSR value.
3506 @param EDX Upper 32-bits of MSR value.
3508 <b>Example usage</b>
3512 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);
3513 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);
3515 @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.
3517 #define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0
3521 Package. Uncore M-box 1 perfmon local box status MSR.
3523 @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)
3524 @param EAX Lower 32-bits of MSR value.
3525 @param EDX Upper 32-bits of MSR value.
3527 <b>Example usage</b>
3531 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);
3532 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);
3534 @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.
3536 #define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1
3540 Package. Uncore M-box 1 perfmon local box overflow control MSR.
3542 @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)
3543 @param EAX Lower 32-bits of MSR value.
3544 @param EDX Upper 32-bits of MSR value.
3546 <b>Example usage</b>
3550 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);
3551 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);
3553 @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.
3555 #define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2
3559 Package. Uncore M-box 1 perfmon time stamp unit select MSR.
3561 @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)
3562 @param EAX Lower 32-bits of MSR value.
3563 @param EDX Upper 32-bits of MSR value.
3565 <b>Example usage</b>
3569 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);
3570 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);
3572 @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.
3574 #define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4
3578 Package. Uncore M-box 1 perfmon DSP unit select MSR.
3580 @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)
3581 @param EAX Lower 32-bits of MSR value.
3582 @param EDX Upper 32-bits of MSR value.
3584 <b>Example usage</b>
3588 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);
3589 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);
3591 @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.
3593 #define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5
3597 Package. Uncore M-box 1 perfmon ISS unit select MSR.
3599 @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)
3600 @param EAX Lower 32-bits of MSR value.
3601 @param EDX Upper 32-bits of MSR value.
3603 <b>Example usage</b>
3607 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);
3608 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);
3610 @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.
3612 #define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6
3616 Package. Uncore M-box 1 perfmon MAP unit select MSR.
3618 @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)
3619 @param EAX Lower 32-bits of MSR value.
3620 @param EDX Upper 32-bits of MSR value.
3622 <b>Example usage</b>
3626 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);
3627 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);
3629 @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.
3631 #define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7
3635 Package. Uncore M-box 1 perfmon MIC THR select MSR.
3637 @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)
3638 @param EAX Lower 32-bits of MSR value.
3639 @param EDX Upper 32-bits of MSR value.
3641 <b>Example usage</b>
3645 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);
3646 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);
3648 @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.
3650 #define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8
3654 Package. Uncore M-box 1 perfmon PGT unit select MSR.
3656 @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)
3657 @param EAX Lower 32-bits of MSR value.
3658 @param EDX Upper 32-bits of MSR value.
3660 <b>Example usage</b>
3664 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);
3665 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);
3667 @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.
3669 #define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9
3673 Package. Uncore M-box 1 perfmon PLD unit select MSR.
3675 @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)
3676 @param EAX Lower 32-bits of MSR value.
3677 @param EDX Upper 32-bits of MSR value.
3679 <b>Example usage</b>
3683 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);
3684 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);
3686 @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.
3688 #define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA
3692 Package. Uncore M-box 1 perfmon ZDP unit select MSR.
3694 @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)
3695 @param EAX Lower 32-bits of MSR value.
3696 @param EDX Upper 32-bits of MSR value.
3698 <b>Example usage</b>
3702 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);
3703 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);
3705 @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.
3707 #define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB
3711 Package. Uncore M-box 1 perfmon event select MSR.
3713 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)
3714 @param EAX Lower 32-bits of MSR value.
3715 @param EDX Upper 32-bits of MSR value.
3717 <b>Example usage</b>
3721 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);
3722 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);
3724 @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.
3726 #define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0
3730 Package. Uncore M-box 1 perfmon counter MSR.
3732 @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)
3733 @param EAX Lower 32-bits of MSR value.
3734 @param EDX Upper 32-bits of MSR value.
3736 <b>Example usage</b>
3740 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);
3741 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);
3743 @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.
3745 #define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1
3749 Package. Uncore M-box 1 perfmon event select MSR.
3751 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)
3752 @param EAX Lower 32-bits of MSR value.
3753 @param EDX Upper 32-bits of MSR value.
3755 <b>Example usage</b>
3759 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);
3760 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);
3762 @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.
3764 #define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2
3768 Package. Uncore M-box 1 perfmon counter MSR.
3770 @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)
3771 @param EAX Lower 32-bits of MSR value.
3772 @param EDX Upper 32-bits of MSR value.
3774 <b>Example usage</b>
3778 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);
3779 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);
3781 @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.
3783 #define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3
3787 Package. Uncore M-box 1 perfmon event select MSR.
3789 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)
3790 @param EAX Lower 32-bits of MSR value.
3791 @param EDX Upper 32-bits of MSR value.
3793 <b>Example usage</b>
3797 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);
3798 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);
3800 @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.
3802 #define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4
3806 Package. Uncore M-box 1 perfmon counter MSR.
3808 @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)
3809 @param EAX Lower 32-bits of MSR value.
3810 @param EDX Upper 32-bits of MSR value.
3812 <b>Example usage</b>
3816 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);
3817 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);
3819 @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.
3821 #define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5
3825 Package. Uncore M-box 1 perfmon event select MSR.
3827 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)
3828 @param EAX Lower 32-bits of MSR value.
3829 @param EDX Upper 32-bits of MSR value.
3831 <b>Example usage</b>
3835 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);
3836 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);
3838 @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.
3840 #define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6
3844 Package. Uncore M-box 1 perfmon counter MSR.
3846 @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)
3847 @param EAX Lower 32-bits of MSR value.
3848 @param EDX Upper 32-bits of MSR value.
3850 <b>Example usage</b>
3854 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);
3855 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);
3857 @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.
3859 #define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7
3863 Package. Uncore M-box 1 perfmon event select MSR.
3865 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)
3866 @param EAX Lower 32-bits of MSR value.
3867 @param EDX Upper 32-bits of MSR value.
3869 <b>Example usage</b>
3873 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);
3874 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);
3876 @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.
3878 #define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8
3882 Package. Uncore M-box 1 perfmon counter MSR.
3884 @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)
3885 @param EAX Lower 32-bits of MSR value.
3886 @param EDX Upper 32-bits of MSR value.
3888 <b>Example usage</b>
3892 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);
3893 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);
3895 @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.
3897 #define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9
3901 Package. Uncore M-box 1 perfmon event select MSR.
3903 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)
3904 @param EAX Lower 32-bits of MSR value.
3905 @param EDX Upper 32-bits of MSR value.
3907 <b>Example usage</b>
3911 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);
3912 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);
3914 @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.
3916 #define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA
3920 Package. Uncore M-box 1 perfmon counter MSR.
3922 @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)
3923 @param EAX Lower 32-bits of MSR value.
3924 @param EDX Upper 32-bits of MSR value.
3926 <b>Example usage</b>
3930 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);
3931 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);
3933 @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.
3935 #define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB
3939 Package. Uncore C-box 0 perfmon local box control MSR.
3941 @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)
3942 @param EAX Lower 32-bits of MSR value.
3943 @param EDX Upper 32-bits of MSR value.
3945 <b>Example usage</b>
3949 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);
3950 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);
3952 @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.
3954 #define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00
3958 Package. Uncore C-box 0 perfmon local box status MSR.
3960 @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)
3961 @param EAX Lower 32-bits of MSR value.
3962 @param EDX Upper 32-bits of MSR value.
3964 <b>Example usage</b>
3968 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);
3969 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);
3971 @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
3973 #define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01
3977 Package. Uncore C-box 0 perfmon local box overflow control MSR.
3979 @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)
3980 @param EAX Lower 32-bits of MSR value.
3981 @param EDX Upper 32-bits of MSR value.
3983 <b>Example usage</b>
3987 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);
3988 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);
3990 @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.
3992 #define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02
3996 Package. Uncore C-box 0 perfmon event select MSR.
3998 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)
3999 @param EAX Lower 32-bits of MSR value.
4000 @param EDX Upper 32-bits of MSR value.
4002 <b>Example usage</b>
4006 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);
4007 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);
4009 @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.
4011 #define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10
4015 Package. Uncore C-box 0 perfmon counter MSR.
4017 @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)
4018 @param EAX Lower 32-bits of MSR value.
4019 @param EDX Upper 32-bits of MSR value.
4021 <b>Example usage</b>
4025 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);
4026 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);
4028 @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
4030 #define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11
4034 Package. Uncore C-box 0 perfmon event select MSR.
4036 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)
4037 @param EAX Lower 32-bits of MSR value.
4038 @param EDX Upper 32-bits of MSR value.
4040 <b>Example usage</b>
4044 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);
4045 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);
4047 @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.
4049 #define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12
4053 Package. Uncore C-box 0 perfmon counter MSR.
4055 @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)
4056 @param EAX Lower 32-bits of MSR value.
4057 @param EDX Upper 32-bits of MSR value.
4059 <b>Example usage</b>
4063 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);
4064 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);
4066 @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
4068 #define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13
4072 Package. Uncore C-box 0 perfmon event select MSR.
4074 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)
4075 @param EAX Lower 32-bits of MSR value.
4076 @param EDX Upper 32-bits of MSR value.
4078 <b>Example usage</b>
4082 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);
4083 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);
4085 @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.
4087 #define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14
4091 Package. Uncore C-box 0 perfmon counter MSR.
4093 @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)
4094 @param EAX Lower 32-bits of MSR value.
4095 @param EDX Upper 32-bits of MSR value.
4097 <b>Example usage</b>
4101 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);
4102 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);
4104 @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
4106 #define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15
4110 Package. Uncore C-box 0 perfmon event select MSR.
4112 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)
4113 @param EAX Lower 32-bits of MSR value.
4114 @param EDX Upper 32-bits of MSR value.
4116 <b>Example usage</b>
4120 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);
4121 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);
4123 @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.
4125 #define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16
4129 Package. Uncore C-box 0 perfmon counter MSR.
4131 @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)
4132 @param EAX Lower 32-bits of MSR value.
4133 @param EDX Upper 32-bits of MSR value.
4135 <b>Example usage</b>
4139 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);
4140 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);
4142 @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
4144 #define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17
4148 Package. Uncore C-box 0 perfmon event select MSR.
4150 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)
4151 @param EAX Lower 32-bits of MSR value.
4152 @param EDX Upper 32-bits of MSR value.
4154 <b>Example usage</b>
4158 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);
4159 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);
4161 @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.
4163 #define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18
4167 Package. Uncore C-box 0 perfmon counter MSR.
4169 @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)
4170 @param EAX Lower 32-bits of MSR value.
4171 @param EDX Upper 32-bits of MSR value.
4173 <b>Example usage</b>
4177 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);
4178 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);
4180 @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.
4182 #define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19
4186 Package. Uncore C-box 0 perfmon event select MSR.
4188 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)
4189 @param EAX Lower 32-bits of MSR value.
4190 @param EDX Upper 32-bits of MSR value.
4192 <b>Example usage</b>
4196 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);
4197 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);
4199 @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.
4201 #define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A
4205 Package. Uncore C-box 0 perfmon counter MSR.
4207 @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)
4208 @param EAX Lower 32-bits of MSR value.
4209 @param EDX Upper 32-bits of MSR value.
4211 <b>Example usage</b>
4215 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);
4216 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);
4218 @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.
4220 #define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B
4224 Package. Uncore C-box 4 perfmon local box control MSR.
4226 @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)
4227 @param EAX Lower 32-bits of MSR value.
4228 @param EDX Upper 32-bits of MSR value.
4230 <b>Example usage</b>
4234 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);
4235 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);
4237 @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.
4239 #define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20
4243 Package. Uncore C-box 4 perfmon local box status MSR.
4245 @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)
4246 @param EAX Lower 32-bits of MSR value.
4247 @param EDX Upper 32-bits of MSR value.
4249 <b>Example usage</b>
4253 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);
4254 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);
4256 @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
4258 #define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21
4262 Package. Uncore C-box 4 perfmon local box overflow control MSR.
4264 @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)
4265 @param EAX Lower 32-bits of MSR value.
4266 @param EDX Upper 32-bits of MSR value.
4268 <b>Example usage</b>
4272 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);
4273 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);
4275 @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.
4277 #define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22
4281 Package. Uncore C-box 4 perfmon event select MSR.
4283 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)
4284 @param EAX Lower 32-bits of MSR value.
4285 @param EDX Upper 32-bits of MSR value.
4287 <b>Example usage</b>
4291 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);
4292 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);
4294 @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.
4296 #define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30
4300 Package. Uncore C-box 4 perfmon counter MSR.
4302 @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)
4303 @param EAX Lower 32-bits of MSR value.
4304 @param EDX Upper 32-bits of MSR value.
4306 <b>Example usage</b>
4310 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);
4311 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);
4313 @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
4315 #define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31
4319 Package. Uncore C-box 4 perfmon event select MSR.
4321 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)
4322 @param EAX Lower 32-bits of MSR value.
4323 @param EDX Upper 32-bits of MSR value.
4325 <b>Example usage</b>
4329 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);
4330 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);
4332 @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.
4334 #define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32
4338 Package. Uncore C-box 4 perfmon counter MSR.
4340 @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)
4341 @param EAX Lower 32-bits of MSR value.
4342 @param EDX Upper 32-bits of MSR value.
4344 <b>Example usage</b>
4348 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);
4349 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);
4351 @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
4353 #define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33
4357 Package. Uncore C-box 4 perfmon event select MSR.
4359 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)
4360 @param EAX Lower 32-bits of MSR value.
4361 @param EDX Upper 32-bits of MSR value.
4363 <b>Example usage</b>
4367 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);
4368 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);
4370 @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.
4372 #define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34
4376 Package. Uncore C-box 4 perfmon counter MSR.
4378 @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)
4379 @param EAX Lower 32-bits of MSR value.
4380 @param EDX Upper 32-bits of MSR value.
4382 <b>Example usage</b>
4386 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);
4387 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);
4389 @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
4391 #define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35
4395 Package. Uncore C-box 4 perfmon event select MSR.
4397 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)
4398 @param EAX Lower 32-bits of MSR value.
4399 @param EDX Upper 32-bits of MSR value.
4401 <b>Example usage</b>
4405 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);
4406 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);
4408 @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.
4410 #define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36
4414 Package. Uncore C-box 4 perfmon counter MSR.
4416 @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)
4417 @param EAX Lower 32-bits of MSR value.
4418 @param EDX Upper 32-bits of MSR value.
4420 <b>Example usage</b>
4424 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);
4425 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);
4427 @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
4429 #define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37
4433 Package. Uncore C-box 4 perfmon event select MSR.
4435 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)
4436 @param EAX Lower 32-bits of MSR value.
4437 @param EDX Upper 32-bits of MSR value.
4439 <b>Example usage</b>
4443 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);
4444 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);
4446 @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.
4448 #define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38
4452 Package. Uncore C-box 4 perfmon counter MSR.
4454 @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)
4455 @param EAX Lower 32-bits of MSR value.
4456 @param EDX Upper 32-bits of MSR value.
4458 <b>Example usage</b>
4462 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);
4463 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);
4465 @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.
4467 #define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39
4471 Package. Uncore C-box 4 perfmon event select MSR.
4473 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)
4474 @param EAX Lower 32-bits of MSR value.
4475 @param EDX Upper 32-bits of MSR value.
4477 <b>Example usage</b>
4481 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);
4482 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);
4484 @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.
4486 #define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A
4490 Package. Uncore C-box 4 perfmon counter MSR.
4492 @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)
4493 @param EAX Lower 32-bits of MSR value.
4494 @param EDX Upper 32-bits of MSR value.
4496 <b>Example usage</b>
4500 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);
4501 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);
4503 @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.
4505 #define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B
4509 Package. Uncore C-box 2 perfmon local box control MSR.
4511 @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)
4512 @param EAX Lower 32-bits of MSR value.
4513 @param EDX Upper 32-bits of MSR value.
4515 <b>Example usage</b>
4519 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);
4520 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);
4522 @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.
4524 #define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40
4528 Package. Uncore C-box 2 perfmon local box status MSR.
4530 @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)
4531 @param EAX Lower 32-bits of MSR value.
4532 @param EDX Upper 32-bits of MSR value.
4534 <b>Example usage</b>
4538 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);
4539 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);
4541 @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
4543 #define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41
4547 Package. Uncore C-box 2 perfmon local box overflow control MSR.
4549 @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)
4550 @param EAX Lower 32-bits of MSR value.
4551 @param EDX Upper 32-bits of MSR value.
4553 <b>Example usage</b>
4557 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);
4558 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);
4560 @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.
4562 #define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42
4566 Package. Uncore C-box 2 perfmon event select MSR.
4568 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)
4569 @param EAX Lower 32-bits of MSR value.
4570 @param EDX Upper 32-bits of MSR value.
4572 <b>Example usage</b>
4576 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);
4577 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);
4579 @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.
4581 #define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50
4585 Package. Uncore C-box 2 perfmon counter MSR.
4587 @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)
4588 @param EAX Lower 32-bits of MSR value.
4589 @param EDX Upper 32-bits of MSR value.
4591 <b>Example usage</b>
4595 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);
4596 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);
4598 @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
4600 #define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51
4604 Package. Uncore C-box 2 perfmon event select MSR.
4606 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)
4607 @param EAX Lower 32-bits of MSR value.
4608 @param EDX Upper 32-bits of MSR value.
4610 <b>Example usage</b>
4614 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);
4615 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);
4617 @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.
4619 #define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52
4623 Package. Uncore C-box 2 perfmon counter MSR.
4625 @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)
4626 @param EAX Lower 32-bits of MSR value.
4627 @param EDX Upper 32-bits of MSR value.
4629 <b>Example usage</b>
4633 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);
4634 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);
4636 @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
4638 #define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53
4642 Package. Uncore C-box 2 perfmon event select MSR.
4644 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)
4645 @param EAX Lower 32-bits of MSR value.
4646 @param EDX Upper 32-bits of MSR value.
4648 <b>Example usage</b>
4652 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);
4653 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);
4655 @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.
4657 #define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54
4661 Package. Uncore C-box 2 perfmon counter MSR.
4663 @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)
4664 @param EAX Lower 32-bits of MSR value.
4665 @param EDX Upper 32-bits of MSR value.
4667 <b>Example usage</b>
4671 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);
4672 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);
4674 @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
4676 #define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55
4680 Package. Uncore C-box 2 perfmon event select MSR.
4682 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)
4683 @param EAX Lower 32-bits of MSR value.
4684 @param EDX Upper 32-bits of MSR value.
4686 <b>Example usage</b>
4690 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);
4691 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);
4693 @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.
4695 #define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56
4699 Package. Uncore C-box 2 perfmon counter MSR.
4701 @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)
4702 @param EAX Lower 32-bits of MSR value.
4703 @param EDX Upper 32-bits of MSR value.
4705 <b>Example usage</b>
4709 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);
4710 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);
4712 @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
4714 #define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57
4718 Package. Uncore C-box 2 perfmon event select MSR.
4720 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)
4721 @param EAX Lower 32-bits of MSR value.
4722 @param EDX Upper 32-bits of MSR value.
4724 <b>Example usage</b>
4728 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);
4729 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);
4731 @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.
4733 #define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58
4737 Package. Uncore C-box 2 perfmon counter MSR.
4739 @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)
4740 @param EAX Lower 32-bits of MSR value.
4741 @param EDX Upper 32-bits of MSR value.
4743 <b>Example usage</b>
4747 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);
4748 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);
4750 @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.
4752 #define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59
4756 Package. Uncore C-box 2 perfmon event select MSR.
4758 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)
4759 @param EAX Lower 32-bits of MSR value.
4760 @param EDX Upper 32-bits of MSR value.
4762 <b>Example usage</b>
4766 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);
4767 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);
4769 @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.
4771 #define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A
4775 Package. Uncore C-box 2 perfmon counter MSR.
4777 @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)
4778 @param EAX Lower 32-bits of MSR value.
4779 @param EDX Upper 32-bits of MSR value.
4781 <b>Example usage</b>
4785 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);
4786 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);
4788 @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.
4790 #define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B
4794 Package. Uncore C-box 6 perfmon local box control MSR.
4796 @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)
4797 @param EAX Lower 32-bits of MSR value.
4798 @param EDX Upper 32-bits of MSR value.
4800 <b>Example usage</b>
4804 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);
4805 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);
4807 @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.
4809 #define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60
4813 Package. Uncore C-box 6 perfmon local box status MSR.
4815 @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)
4816 @param EAX Lower 32-bits of MSR value.
4817 @param EDX Upper 32-bits of MSR value.
4819 <b>Example usage</b>
4823 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);
4824 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);
4826 @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
4828 #define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61
4832 Package. Uncore C-box 6 perfmon local box overflow control MSR.
4834 @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)
4835 @param EAX Lower 32-bits of MSR value.
4836 @param EDX Upper 32-bits of MSR value.
4838 <b>Example usage</b>
4842 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);
4843 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);
4845 @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.
4847 #define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62
4851 Package. Uncore C-box 6 perfmon event select MSR.
4853 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)
4854 @param EAX Lower 32-bits of MSR value.
4855 @param EDX Upper 32-bits of MSR value.
4857 <b>Example usage</b>
4861 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);
4862 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);
4864 @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.
4866 #define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70
4870 Package. Uncore C-box 6 perfmon counter MSR.
4872 @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)
4873 @param EAX Lower 32-bits of MSR value.
4874 @param EDX Upper 32-bits of MSR value.
4876 <b>Example usage</b>
4880 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);
4881 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);
4883 @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
4885 #define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71
4889 Package. Uncore C-box 6 perfmon event select MSR.
4891 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)
4892 @param EAX Lower 32-bits of MSR value.
4893 @param EDX Upper 32-bits of MSR value.
4895 <b>Example usage</b>
4899 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);
4900 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);
4902 @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.
4904 #define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72
4908 Package. Uncore C-box 6 perfmon counter MSR.
4910 @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)
4911 @param EAX Lower 32-bits of MSR value.
4912 @param EDX Upper 32-bits of MSR value.
4914 <b>Example usage</b>
4918 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);
4919 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);
4921 @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
4923 #define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73
4927 Package. Uncore C-box 6 perfmon event select MSR.
4929 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)
4930 @param EAX Lower 32-bits of MSR value.
4931 @param EDX Upper 32-bits of MSR value.
4933 <b>Example usage</b>
4937 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);
4938 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);
4940 @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.
4942 #define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74
4946 Package. Uncore C-box 6 perfmon counter MSR.
4948 @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)
4949 @param EAX Lower 32-bits of MSR value.
4950 @param EDX Upper 32-bits of MSR value.
4952 <b>Example usage</b>
4956 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);
4957 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);
4959 @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
4961 #define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75
4965 Package. Uncore C-box 6 perfmon event select MSR.
4967 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)
4968 @param EAX Lower 32-bits of MSR value.
4969 @param EDX Upper 32-bits of MSR value.
4971 <b>Example usage</b>
4975 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);
4976 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);
4978 @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.
4980 #define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76
4984 Package. Uncore C-box 6 perfmon counter MSR.
4986 @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)
4987 @param EAX Lower 32-bits of MSR value.
4988 @param EDX Upper 32-bits of MSR value.
4990 <b>Example usage</b>
4994 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);
4995 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);
4997 @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
4999 #define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77
5003 Package. Uncore C-box 6 perfmon event select MSR.
5005 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)
5006 @param EAX Lower 32-bits of MSR value.
5007 @param EDX Upper 32-bits of MSR value.
5009 <b>Example usage</b>
5013 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);
5014 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);
5016 @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.
5018 #define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78
5022 Package. Uncore C-box 6 perfmon counter MSR.
5024 @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)
5025 @param EAX Lower 32-bits of MSR value.
5026 @param EDX Upper 32-bits of MSR value.
5028 <b>Example usage</b>
5032 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);
5033 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);
5035 @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.
5037 #define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79
5041 Package. Uncore C-box 6 perfmon event select MSR.
5043 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)
5044 @param EAX Lower 32-bits of MSR value.
5045 @param EDX Upper 32-bits of MSR value.
5047 <b>Example usage</b>
5051 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);
5052 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);
5054 @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.
5056 #define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A
5060 Package. Uncore C-box 6 perfmon counter MSR.
5062 @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)
5063 @param EAX Lower 32-bits of MSR value.
5064 @param EDX Upper 32-bits of MSR value.
5066 <b>Example usage</b>
5070 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);
5071 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);
5073 @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.
5075 #define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B
5079 Package. Uncore C-box 1 perfmon local box control MSR.
5081 @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)
5082 @param EAX Lower 32-bits of MSR value.
5083 @param EDX Upper 32-bits of MSR value.
5085 <b>Example usage</b>
5089 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);
5090 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);
5092 @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.
5094 #define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80
5098 Package. Uncore C-box 1 perfmon local box status MSR.
5100 @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)
5101 @param EAX Lower 32-bits of MSR value.
5102 @param EDX Upper 32-bits of MSR value.
5104 <b>Example usage</b>
5108 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);
5109 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);
5111 @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
5113 #define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81
5117 Package. Uncore C-box 1 perfmon local box overflow control MSR.
5119 @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)
5120 @param EAX Lower 32-bits of MSR value.
5121 @param EDX Upper 32-bits of MSR value.
5123 <b>Example usage</b>
5127 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);
5128 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);
5130 @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.
5132 #define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82
5136 Package. Uncore C-box 1 perfmon event select MSR.
5138 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)
5139 @param EAX Lower 32-bits of MSR value.
5140 @param EDX Upper 32-bits of MSR value.
5142 <b>Example usage</b>
5146 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);
5147 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);
5149 @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.
5151 #define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90
5155 Package. Uncore C-box 1 perfmon counter MSR.
5157 @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)
5158 @param EAX Lower 32-bits of MSR value.
5159 @param EDX Upper 32-bits of MSR value.
5161 <b>Example usage</b>
5165 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);
5166 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);
5168 @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
5170 #define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91
5174 Package. Uncore C-box 1 perfmon event select MSR.
5176 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)
5177 @param EAX Lower 32-bits of MSR value.
5178 @param EDX Upper 32-bits of MSR value.
5180 <b>Example usage</b>
5184 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);
5185 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);
5187 @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.
5189 #define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92
5193 Package. Uncore C-box 1 perfmon counter MSR.
5195 @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)
5196 @param EAX Lower 32-bits of MSR value.
5197 @param EDX Upper 32-bits of MSR value.
5199 <b>Example usage</b>
5203 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);
5204 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);
5206 @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
5208 #define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93
5212 Package. Uncore C-box 1 perfmon event select MSR.
5214 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)
5215 @param EAX Lower 32-bits of MSR value.
5216 @param EDX Upper 32-bits of MSR value.
5218 <b>Example usage</b>
5222 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);
5223 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);
5225 @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.
5227 #define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94
5231 Package. Uncore C-box 1 perfmon counter MSR.
5233 @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)
5234 @param EAX Lower 32-bits of MSR value.
5235 @param EDX Upper 32-bits of MSR value.
5237 <b>Example usage</b>
5241 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);
5242 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);
5244 @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
5246 #define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95
5250 Package. Uncore C-box 1 perfmon event select MSR.
5252 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)
5253 @param EAX Lower 32-bits of MSR value.
5254 @param EDX Upper 32-bits of MSR value.
5256 <b>Example usage</b>
5260 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);
5261 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);
5263 @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.
5265 #define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96
5269 Package. Uncore C-box 1 perfmon counter MSR.
5271 @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)
5272 @param EAX Lower 32-bits of MSR value.
5273 @param EDX Upper 32-bits of MSR value.
5275 <b>Example usage</b>
5279 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);
5280 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);
5282 @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
5284 #define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97
5288 Package. Uncore C-box 1 perfmon event select MSR.
5290 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)
5291 @param EAX Lower 32-bits of MSR value.
5292 @param EDX Upper 32-bits of MSR value.
5294 <b>Example usage</b>
5298 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);
5299 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);
5301 @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.
5303 #define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98
5307 Package. Uncore C-box 1 perfmon counter MSR.
5309 @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)
5310 @param EAX Lower 32-bits of MSR value.
5311 @param EDX Upper 32-bits of MSR value.
5313 <b>Example usage</b>
5317 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);
5318 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);
5320 @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.
5322 #define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99
5326 Package. Uncore C-box 1 perfmon event select MSR.
5328 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)
5329 @param EAX Lower 32-bits of MSR value.
5330 @param EDX Upper 32-bits of MSR value.
5332 <b>Example usage</b>
5336 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);
5337 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);
5339 @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.
5341 #define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A
5345 Package. Uncore C-box 1 perfmon counter MSR.
5347 @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)
5348 @param EAX Lower 32-bits of MSR value.
5349 @param EDX Upper 32-bits of MSR value.
5351 <b>Example usage</b>
5355 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);
5356 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);
5358 @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.
5360 #define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B
5364 Package. Uncore C-box 5 perfmon local box control MSR.
5366 @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)
5367 @param EAX Lower 32-bits of MSR value.
5368 @param EDX Upper 32-bits of MSR value.
5370 <b>Example usage</b>
5374 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);
5375 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);
5377 @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.
5379 #define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0
5383 Package. Uncore C-box 5 perfmon local box status MSR.
5385 @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)
5386 @param EAX Lower 32-bits of MSR value.
5387 @param EDX Upper 32-bits of MSR value.
5389 <b>Example usage</b>
5393 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);
5394 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);
5396 @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
5398 #define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1
5402 Package. Uncore C-box 5 perfmon local box overflow control MSR.
5404 @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)
5405 @param EAX Lower 32-bits of MSR value.
5406 @param EDX Upper 32-bits of MSR value.
5408 <b>Example usage</b>
5412 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);
5413 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);
5415 @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.
5417 #define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2
5421 Package. Uncore C-box 5 perfmon event select MSR.
5423 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)
5424 @param EAX Lower 32-bits of MSR value.
5425 @param EDX Upper 32-bits of MSR value.
5427 <b>Example usage</b>
5431 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);
5432 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);
5434 @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.
5436 #define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0
5440 Package. Uncore C-box 5 perfmon counter MSR.
5442 @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)
5443 @param EAX Lower 32-bits of MSR value.
5444 @param EDX Upper 32-bits of MSR value.
5446 <b>Example usage</b>
5450 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);
5451 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);
5453 @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
5455 #define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1
5459 Package. Uncore C-box 5 perfmon event select MSR.
5461 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)
5462 @param EAX Lower 32-bits of MSR value.
5463 @param EDX Upper 32-bits of MSR value.
5465 <b>Example usage</b>
5469 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);
5470 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);
5472 @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.
5474 #define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2
5478 Package. Uncore C-box 5 perfmon counter MSR.
5480 @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)
5481 @param EAX Lower 32-bits of MSR value.
5482 @param EDX Upper 32-bits of MSR value.
5484 <b>Example usage</b>
5488 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);
5489 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);
5491 @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
5493 #define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3
5497 Package. Uncore C-box 5 perfmon event select MSR.
5499 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)
5500 @param EAX Lower 32-bits of MSR value.
5501 @param EDX Upper 32-bits of MSR value.
5503 <b>Example usage</b>
5507 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);
5508 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);
5510 @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.
5512 #define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4
5516 Package. Uncore C-box 5 perfmon counter MSR.
5518 @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)
5519 @param EAX Lower 32-bits of MSR value.
5520 @param EDX Upper 32-bits of MSR value.
5522 <b>Example usage</b>
5526 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);
5527 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);
5529 @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
5531 #define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5
5535 Package. Uncore C-box 5 perfmon event select MSR.
5537 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)
5538 @param EAX Lower 32-bits of MSR value.
5539 @param EDX Upper 32-bits of MSR value.
5541 <b>Example usage</b>
5545 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);
5546 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);
5548 @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.
5550 #define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6
5554 Package. Uncore C-box 5 perfmon counter MSR.
5556 @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)
5557 @param EAX Lower 32-bits of MSR value.
5558 @param EDX Upper 32-bits of MSR value.
5560 <b>Example usage</b>
5564 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);
5565 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);
5567 @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
5569 #define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7
5573 Package. Uncore C-box 5 perfmon event select MSR.
5575 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)
5576 @param EAX Lower 32-bits of MSR value.
5577 @param EDX Upper 32-bits of MSR value.
5579 <b>Example usage</b>
5583 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);
5584 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);
5586 @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.
5588 #define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8
5592 Package. Uncore C-box 5 perfmon counter MSR.
5594 @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)
5595 @param EAX Lower 32-bits of MSR value.
5596 @param EDX Upper 32-bits of MSR value.
5598 <b>Example usage</b>
5602 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);
5603 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);
5605 @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.
5607 #define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9
5611 Package. Uncore C-box 5 perfmon event select MSR.
5613 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)
5614 @param EAX Lower 32-bits of MSR value.
5615 @param EDX Upper 32-bits of MSR value.
5617 <b>Example usage</b>
5621 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);
5622 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);
5624 @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.
5626 #define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA
5630 Package. Uncore C-box 5 perfmon counter MSR.
5632 @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)
5633 @param EAX Lower 32-bits of MSR value.
5634 @param EDX Upper 32-bits of MSR value.
5636 <b>Example usage</b>
5640 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);
5641 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);
5643 @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.
5645 #define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB
5649 Package. Uncore C-box 3 perfmon local box control MSR.
5651 @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)
5652 @param EAX Lower 32-bits of MSR value.
5653 @param EDX Upper 32-bits of MSR value.
5655 <b>Example usage</b>
5659 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);
5660 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);
5662 @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.
5664 #define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0
5668 Package. Uncore C-box 3 perfmon local box status MSR.
5670 @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)
5671 @param EAX Lower 32-bits of MSR value.
5672 @param EDX Upper 32-bits of MSR value.
5674 <b>Example usage</b>
5678 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);
5679 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);
5681 @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
5683 #define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1
5687 Package. Uncore C-box 3 perfmon local box overflow control MSR.
5689 @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)
5690 @param EAX Lower 32-bits of MSR value.
5691 @param EDX Upper 32-bits of MSR value.
5693 <b>Example usage</b>
5697 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);
5698 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);
5700 @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.
5702 #define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2
5706 Package. Uncore C-box 3 perfmon event select MSR.
5708 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)
5709 @param EAX Lower 32-bits of MSR value.
5710 @param EDX Upper 32-bits of MSR value.
5712 <b>Example usage</b>
5716 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);
5717 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);
5719 @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.
5721 #define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0
5725 Package. Uncore C-box 3 perfmon counter MSR.
5727 @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)
5728 @param EAX Lower 32-bits of MSR value.
5729 @param EDX Upper 32-bits of MSR value.
5731 <b>Example usage</b>
5735 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);
5736 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);
5738 @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
5740 #define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1
5744 Package. Uncore C-box 3 perfmon event select MSR.
5746 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)
5747 @param EAX Lower 32-bits of MSR value.
5748 @param EDX Upper 32-bits of MSR value.
5750 <b>Example usage</b>
5754 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);
5755 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);
5757 @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.
5759 #define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2
5763 Package. Uncore C-box 3 perfmon counter MSR.
5765 @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)
5766 @param EAX Lower 32-bits of MSR value.
5767 @param EDX Upper 32-bits of MSR value.
5769 <b>Example usage</b>
5773 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);
5774 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);
5776 @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
5778 #define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3
5782 Package. Uncore C-box 3 perfmon event select MSR.
5784 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)
5785 @param EAX Lower 32-bits of MSR value.
5786 @param EDX Upper 32-bits of MSR value.
5788 <b>Example usage</b>
5792 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);
5793 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);
5795 @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.
5797 #define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4
5801 Package. Uncore C-box 3 perfmon counter MSR.
5803 @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)
5804 @param EAX Lower 32-bits of MSR value.
5805 @param EDX Upper 32-bits of MSR value.
5807 <b>Example usage</b>
5811 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);
5812 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);
5814 @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
5816 #define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5
5820 Package. Uncore C-box 3 perfmon event select MSR.
5822 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)
5823 @param EAX Lower 32-bits of MSR value.
5824 @param EDX Upper 32-bits of MSR value.
5826 <b>Example usage</b>
5830 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);
5831 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);
5833 @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.
5835 #define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6
5839 Package. Uncore C-box 3 perfmon counter MSR.
5841 @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)
5842 @param EAX Lower 32-bits of MSR value.
5843 @param EDX Upper 32-bits of MSR value.
5845 <b>Example usage</b>
5849 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);
5850 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);
5852 @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
5854 #define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7
5858 Package. Uncore C-box 3 perfmon event select MSR.
5860 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)
5861 @param EAX Lower 32-bits of MSR value.
5862 @param EDX Upper 32-bits of MSR value.
5864 <b>Example usage</b>
5868 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);
5869 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);
5871 @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.
5873 #define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8
5877 Package. Uncore C-box 3 perfmon counter MSR.
5879 @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)
5880 @param EAX Lower 32-bits of MSR value.
5881 @param EDX Upper 32-bits of MSR value.
5883 <b>Example usage</b>
5887 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);
5888 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);
5890 @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.
5892 #define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9
5896 Package. Uncore C-box 3 perfmon event select MSR.
5898 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)
5899 @param EAX Lower 32-bits of MSR value.
5900 @param EDX Upper 32-bits of MSR value.
5902 <b>Example usage</b>
5906 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);
5907 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);
5909 @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.
5911 #define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA
5915 Package. Uncore C-box 3 perfmon counter MSR.
5917 @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)
5918 @param EAX Lower 32-bits of MSR value.
5919 @param EDX Upper 32-bits of MSR value.
5921 <b>Example usage</b>
5925 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);
5926 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);
5928 @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.
5930 #define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB
5934 Package. Uncore C-box 7 perfmon local box control MSR.
5936 @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)
5937 @param EAX Lower 32-bits of MSR value.
5938 @param EDX Upper 32-bits of MSR value.
5940 <b>Example usage</b>
5944 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);
5945 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);
5947 @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.
5949 #define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0
5953 Package. Uncore C-box 7 perfmon local box status MSR.
5955 @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)
5956 @param EAX Lower 32-bits of MSR value.
5957 @param EDX Upper 32-bits of MSR value.
5959 <b>Example usage</b>
5963 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);
5964 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);
5966 @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
5968 #define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1
5972 Package. Uncore C-box 7 perfmon local box overflow control MSR.
5974 @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)
5975 @param EAX Lower 32-bits of MSR value.
5976 @param EDX Upper 32-bits of MSR value.
5978 <b>Example usage</b>
5982 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);
5983 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);
5985 @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.
5987 #define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2
5991 Package. Uncore C-box 7 perfmon event select MSR.
5993 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)
5994 @param EAX Lower 32-bits of MSR value.
5995 @param EDX Upper 32-bits of MSR value.
5997 <b>Example usage</b>
6001 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);
6002 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);
6004 @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.
6006 #define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0
6010 Package. Uncore C-box 7 perfmon counter MSR.
6012 @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)
6013 @param EAX Lower 32-bits of MSR value.
6014 @param EDX Upper 32-bits of MSR value.
6016 <b>Example usage</b>
6020 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);
6021 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);
6023 @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
6025 #define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1
6029 Package. Uncore C-box 7 perfmon event select MSR.
6031 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)
6032 @param EAX Lower 32-bits of MSR value.
6033 @param EDX Upper 32-bits of MSR value.
6035 <b>Example usage</b>
6039 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);
6040 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);
6042 @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.
6044 #define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2
6048 Package. Uncore C-box 7 perfmon counter MSR.
6050 @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)
6051 @param EAX Lower 32-bits of MSR value.
6052 @param EDX Upper 32-bits of MSR value.
6054 <b>Example usage</b>
6058 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);
6059 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);
6061 @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
6063 #define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3
6067 Package. Uncore C-box 7 perfmon event select MSR.
6069 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)
6070 @param EAX Lower 32-bits of MSR value.
6071 @param EDX Upper 32-bits of MSR value.
6073 <b>Example usage</b>
6077 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);
6078 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);
6080 @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.
6082 #define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4
6086 Package. Uncore C-box 7 perfmon counter MSR.
6088 @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)
6089 @param EAX Lower 32-bits of MSR value.
6090 @param EDX Upper 32-bits of MSR value.
6092 <b>Example usage</b>
6096 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);
6097 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);
6099 @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
6101 #define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5
6105 Package. Uncore C-box 7 perfmon event select MSR.
6107 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)
6108 @param EAX Lower 32-bits of MSR value.
6109 @param EDX Upper 32-bits of MSR value.
6111 <b>Example usage</b>
6115 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);
6116 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);
6118 @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.
6120 #define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6
6124 Package. Uncore C-box 7 perfmon counter MSR.
6126 @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)
6127 @param EAX Lower 32-bits of MSR value.
6128 @param EDX Upper 32-bits of MSR value.
6130 <b>Example usage</b>
6134 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);
6135 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);
6137 @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
6139 #define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7
6143 Package. Uncore C-box 7 perfmon event select MSR.
6145 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)
6146 @param EAX Lower 32-bits of MSR value.
6147 @param EDX Upper 32-bits of MSR value.
6149 <b>Example usage</b>
6153 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);
6154 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);
6156 @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.
6158 #define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8
6162 Package. Uncore C-box 7 perfmon counter MSR.
6164 @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)
6165 @param EAX Lower 32-bits of MSR value.
6166 @param EDX Upper 32-bits of MSR value.
6168 <b>Example usage</b>
6172 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);
6173 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);
6175 @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.
6177 #define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9
6181 Package. Uncore C-box 7 perfmon event select MSR.
6183 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)
6184 @param EAX Lower 32-bits of MSR value.
6185 @param EDX Upper 32-bits of MSR value.
6187 <b>Example usage</b>
6191 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);
6192 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);
6194 @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.
6196 #define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA
6200 Package. Uncore C-box 7 perfmon counter MSR.
6202 @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)
6203 @param EAX Lower 32-bits of MSR value.
6204 @param EDX Upper 32-bits of MSR value.
6206 <b>Example usage</b>
6210 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);
6211 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);
6213 @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.
6215 #define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB
6219 Package. Uncore R-box 0 perfmon local box control MSR.
6221 @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)
6222 @param EAX Lower 32-bits of MSR value.
6223 @param EDX Upper 32-bits of MSR value.
6225 <b>Example usage</b>
6229 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);
6230 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);
6232 @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.
6234 #define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00
6238 Package. Uncore R-box 0 perfmon local box status MSR.
6240 @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)
6241 @param EAX Lower 32-bits of MSR value.
6242 @param EDX Upper 32-bits of MSR value.
6244 <b>Example usage</b>
6248 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);
6249 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);
6251 @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.
6253 #define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01
6257 Package. Uncore R-box 0 perfmon local box overflow control MSR.
6259 @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)
6260 @param EAX Lower 32-bits of MSR value.
6261 @param EDX Upper 32-bits of MSR value.
6263 <b>Example usage</b>
6267 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);
6268 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);
6270 @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.
6272 #define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02
6276 Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.
6278 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)
6279 @param EAX Lower 32-bits of MSR value.
6280 @param EDX Upper 32-bits of MSR value.
6282 <b>Example usage</b>
6286 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);
6287 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);
6289 @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.
6291 #define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04
6295 Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.
6297 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)
6298 @param EAX Lower 32-bits of MSR value.
6299 @param EDX Upper 32-bits of MSR value.
6301 <b>Example usage</b>
6305 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);
6306 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);
6308 @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.
6310 #define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05
6314 Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.
6316 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)
6317 @param EAX Lower 32-bits of MSR value.
6318 @param EDX Upper 32-bits of MSR value.
6320 <b>Example usage</b>
6324 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);
6325 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);
6327 @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.
6329 #define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06
6333 Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.
6335 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)
6336 @param EAX Lower 32-bits of MSR value.
6337 @param EDX Upper 32-bits of MSR value.
6339 <b>Example usage</b>
6343 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);
6344 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);
6346 @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.
6348 #define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07
6352 Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.
6354 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)
6355 @param EAX Lower 32-bits of MSR value.
6356 @param EDX Upper 32-bits of MSR value.
6358 <b>Example usage</b>
6362 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);
6363 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);
6365 @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.
6367 #define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08
6371 Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.
6373 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)
6374 @param EAX Lower 32-bits of MSR value.
6375 @param EDX Upper 32-bits of MSR value.
6377 <b>Example usage</b>
6381 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);
6382 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);
6384 @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.
6386 #define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09
6390 Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.
6392 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)
6393 @param EAX Lower 32-bits of MSR value.
6394 @param EDX Upper 32-bits of MSR value.
6396 <b>Example usage</b>
6400 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);
6401 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);
6403 @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.
6405 #define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A
6409 Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.
6411 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)
6412 @param EAX Lower 32-bits of MSR value.
6413 @param EDX Upper 32-bits of MSR value.
6415 <b>Example usage</b>
6419 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);
6420 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);
6422 @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.
6424 #define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B
6428 Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
6430 @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)
6431 @param EAX Lower 32-bits of MSR value.
6432 @param EDX Upper 32-bits of MSR value.
6434 <b>Example usage</b>
6438 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);
6439 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);
6441 @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.
6443 #define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C
6447 Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
6449 @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)
6450 @param EAX Lower 32-bits of MSR value.
6451 @param EDX Upper 32-bits of MSR value.
6453 <b>Example usage</b>
6457 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);
6458 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);
6460 @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.
6462 #define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D
6466 Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
6468 @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)
6469 @param EAX Lower 32-bits of MSR value.
6470 @param EDX Upper 32-bits of MSR value.
6472 <b>Example usage</b>
6476 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);
6477 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);
6479 @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.
6481 #define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E
6485 Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
6487 @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)
6488 @param EAX Lower 32-bits of MSR value.
6489 @param EDX Upper 32-bits of MSR value.
6491 <b>Example usage</b>
6495 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);
6496 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);
6498 @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.
6500 #define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F
6504 Package. Uncore R-box 0 perfmon event select MSR.
6506 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)
6507 @param EAX Lower 32-bits of MSR value.
6508 @param EDX Upper 32-bits of MSR value.
6510 <b>Example usage</b>
6514 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);
6515 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);
6517 @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.
6519 #define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10
6523 Package. Uncore R-box 0 perfmon counter MSR.
6525 @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)
6526 @param EAX Lower 32-bits of MSR value.
6527 @param EDX Upper 32-bits of MSR value.
6529 <b>Example usage</b>
6533 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);
6534 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);
6536 @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.
6538 #define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11
6542 Package. Uncore R-box 0 perfmon event select MSR.
6544 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)
6545 @param EAX Lower 32-bits of MSR value.
6546 @param EDX Upper 32-bits of MSR value.
6548 <b>Example usage</b>
6552 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);
6553 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);
6555 @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.
6557 #define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12
6561 Package. Uncore R-box 0 perfmon counter MSR.
6563 @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)
6564 @param EAX Lower 32-bits of MSR value.
6565 @param EDX Upper 32-bits of MSR value.
6567 <b>Example usage</b>
6571 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);
6572 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);
6574 @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.
6576 #define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13
6580 Package. Uncore R-box 0 perfmon event select MSR.
6582 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)
6583 @param EAX Lower 32-bits of MSR value.
6584 @param EDX Upper 32-bits of MSR value.
6586 <b>Example usage</b>
6590 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);
6591 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);
6593 @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.
6595 #define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14
6599 Package. Uncore R-box 0 perfmon counter MSR.
6601 @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)
6602 @param EAX Lower 32-bits of MSR value.
6603 @param EDX Upper 32-bits of MSR value.
6605 <b>Example usage</b>
6609 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);
6610 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);
6612 @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.
6614 #define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15
6618 Package. Uncore R-box 0 perfmon event select MSR.
6620 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)
6621 @param EAX Lower 32-bits of MSR value.
6622 @param EDX Upper 32-bits of MSR value.
6624 <b>Example usage</b>
6628 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);
6629 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);
6631 @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.
6633 #define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16
6637 Package. Uncore R-box 0 perfmon counter MSR.
6639 @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)
6640 @param EAX Lower 32-bits of MSR value.
6641 @param EDX Upper 32-bits of MSR value.
6643 <b>Example usage</b>
6647 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);
6648 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);
6650 @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.
6652 #define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17
6656 Package. Uncore R-box 0 perfmon event select MSR.
6658 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)
6659 @param EAX Lower 32-bits of MSR value.
6660 @param EDX Upper 32-bits of MSR value.
6662 <b>Example usage</b>
6666 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);
6667 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);
6669 @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.
6671 #define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18
6675 Package. Uncore R-box 0 perfmon counter MSR.
6677 @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)
6678 @param EAX Lower 32-bits of MSR value.
6679 @param EDX Upper 32-bits of MSR value.
6681 <b>Example usage</b>
6685 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);
6686 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);
6688 @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.
6690 #define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19
6694 Package. Uncore R-box 0 perfmon event select MSR.
6696 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)
6697 @param EAX Lower 32-bits of MSR value.
6698 @param EDX Upper 32-bits of MSR value.
6700 <b>Example usage</b>
6704 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);
6705 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);
6707 @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.
6709 #define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A
6713 Package. Uncore R-box 0 perfmon counter MSR.
6715 @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)
6716 @param EAX Lower 32-bits of MSR value.
6717 @param EDX Upper 32-bits of MSR value.
6719 <b>Example usage</b>
6723 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);
6724 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);
6726 @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.
6728 #define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B
6732 Package. Uncore R-box 0 perfmon event select MSR.
6734 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)
6735 @param EAX Lower 32-bits of MSR value.
6736 @param EDX Upper 32-bits of MSR value.
6738 <b>Example usage</b>
6742 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);
6743 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);
6745 @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.
6747 #define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C
6751 Package. Uncore R-box 0 perfmon counter MSR.
6753 @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)
6754 @param EAX Lower 32-bits of MSR value.
6755 @param EDX Upper 32-bits of MSR value.
6757 <b>Example usage</b>
6761 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);
6762 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);
6764 @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.
6766 #define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D
6770 Package. Uncore R-box 0 perfmon event select MSR.
6772 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)
6773 @param EAX Lower 32-bits of MSR value.
6774 @param EDX Upper 32-bits of MSR value.
6776 <b>Example usage</b>
6780 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);
6781 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);
6783 @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.
6785 #define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E
6789 Package. Uncore R-box 0 perfmon counter MSR.
6791 @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)
6792 @param EAX Lower 32-bits of MSR value.
6793 @param EDX Upper 32-bits of MSR value.
6795 <b>Example usage</b>
6799 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);
6800 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);
6802 @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.
6804 #define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F
6808 Package. Uncore R-box 1 perfmon local box control MSR.
6810 @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)
6811 @param EAX Lower 32-bits of MSR value.
6812 @param EDX Upper 32-bits of MSR value.
6814 <b>Example usage</b>
6818 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);
6819 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);
6821 @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.
6823 #define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20
6827 Package. Uncore R-box 1 perfmon local box status MSR.
6829 @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)
6830 @param EAX Lower 32-bits of MSR value.
6831 @param EDX Upper 32-bits of MSR value.
6833 <b>Example usage</b>
6837 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);
6838 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);
6840 @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.
6842 #define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21
6846 Package. Uncore R-box 1 perfmon local box overflow control MSR.
6848 @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)
6849 @param EAX Lower 32-bits of MSR value.
6850 @param EDX Upper 32-bits of MSR value.
6852 <b>Example usage</b>
6856 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);
6857 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);
6859 @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.
6861 #define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22
6865 Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.
6867 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)
6868 @param EAX Lower 32-bits of MSR value.
6869 @param EDX Upper 32-bits of MSR value.
6871 <b>Example usage</b>
6875 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);
6876 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);
6878 @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.
6880 #define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24
6884 Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.
6886 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)
6887 @param EAX Lower 32-bits of MSR value.
6888 @param EDX Upper 32-bits of MSR value.
6890 <b>Example usage</b>
6894 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);
6895 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);
6897 @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.
6899 #define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25
6903 Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.
6905 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)
6906 @param EAX Lower 32-bits of MSR value.
6907 @param EDX Upper 32-bits of MSR value.
6909 <b>Example usage</b>
6913 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);
6914 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);
6916 @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.
6918 #define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26
6922 Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.
6924 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)
6925 @param EAX Lower 32-bits of MSR value.
6926 @param EDX Upper 32-bits of MSR value.
6928 <b>Example usage</b>
6932 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);
6933 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);
6935 @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.
6937 #define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27
6941 Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.
6943 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)
6944 @param EAX Lower 32-bits of MSR value.
6945 @param EDX Upper 32-bits of MSR value.
6947 <b>Example usage</b>
6951 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);
6952 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);
6954 @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.
6956 #define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28
6960 Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.
6962 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)
6963 @param EAX Lower 32-bits of MSR value.
6964 @param EDX Upper 32-bits of MSR value.
6966 <b>Example usage</b>
6970 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);
6971 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);
6973 @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.
6975 #define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29
6979 Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.
6981 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)
6982 @param EAX Lower 32-bits of MSR value.
6983 @param EDX Upper 32-bits of MSR value.
6985 <b>Example usage</b>
6989 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);
6990 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);
6992 @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.
6994 #define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A
6998 Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.
7000 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)
7001 @param EAX Lower 32-bits of MSR value.
7002 @param EDX Upper 32-bits of MSR value.
7004 <b>Example usage</b>
7008 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);
7009 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);
7011 @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.
7013 #define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B
7017 Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
7019 @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)
7020 @param EAX Lower 32-bits of MSR value.
7021 @param EDX Upper 32-bits of MSR value.
7023 <b>Example usage</b>
7027 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);
7028 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);
7030 @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.
7032 #define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C
7036 Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
7038 @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)
7039 @param EAX Lower 32-bits of MSR value.
7040 @param EDX Upper 32-bits of MSR value.
7042 <b>Example usage</b>
7046 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);
7047 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);
7049 @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.
7051 #define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D
7055 Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
7057 @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)
7058 @param EAX Lower 32-bits of MSR value.
7059 @param EDX Upper 32-bits of MSR value.
7061 <b>Example usage</b>
7065 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);
7066 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);
7068 @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.
7070 #define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E
7074 Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
7076 @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)
7077 @param EAX Lower 32-bits of MSR value.
7078 @param EDX Upper 32-bits of MSR value.
7080 <b>Example usage</b>
7084 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);
7085 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);
7087 @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.
7089 #define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F
7093 Package. Uncore R-box 1 perfmon event select MSR.
7095 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)
7096 @param EAX Lower 32-bits of MSR value.
7097 @param EDX Upper 32-bits of MSR value.
7099 <b>Example usage</b>
7103 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);
7104 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);
7106 @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.
7108 #define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30
7112 Package. Uncore R-box 1 perfmon counter MSR.
7114 @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)
7115 @param EAX Lower 32-bits of MSR value.
7116 @param EDX Upper 32-bits of MSR value.
7118 <b>Example usage</b>
7122 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);
7123 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);
7125 @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.
7127 #define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31
7131 Package. Uncore R-box 1 perfmon event select MSR.
7133 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)
7134 @param EAX Lower 32-bits of MSR value.
7135 @param EDX Upper 32-bits of MSR value.
7137 <b>Example usage</b>
7141 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);
7142 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);
7144 @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.
7146 #define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32
7150 Package. Uncore R-box 1 perfmon counter MSR.
7152 @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)
7153 @param EAX Lower 32-bits of MSR value.
7154 @param EDX Upper 32-bits of MSR value.
7156 <b>Example usage</b>
7160 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);
7161 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);
7163 @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.
7165 #define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33
7169 Package. Uncore R-box 1 perfmon event select MSR.
7171 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)
7172 @param EAX Lower 32-bits of MSR value.
7173 @param EDX Upper 32-bits of MSR value.
7175 <b>Example usage</b>
7179 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);
7180 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);
7182 @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.
7184 #define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34
7188 Package. Uncore R-box 1 perfmon counter MSR.
7190 @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)
7191 @param EAX Lower 32-bits of MSR value.
7192 @param EDX Upper 32-bits of MSR value.
7194 <b>Example usage</b>
7198 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);
7199 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);
7201 @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.
7203 #define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35
7207 Package. Uncore R-box 1 perfmon event select MSR.
7209 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)
7210 @param EAX Lower 32-bits of MSR value.
7211 @param EDX Upper 32-bits of MSR value.
7213 <b>Example usage</b>
7217 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);
7218 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);
7220 @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.
7222 #define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36
7226 Package. Uncore R-box 1 perfmon counter MSR.
7228 @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)
7229 @param EAX Lower 32-bits of MSR value.
7230 @param EDX Upper 32-bits of MSR value.
7232 <b>Example usage</b>
7236 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);
7237 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);
7239 @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.
7241 #define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37
7245 Package. Uncore R-box 1 perfmon event select MSR.
7247 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)
7248 @param EAX Lower 32-bits of MSR value.
7249 @param EDX Upper 32-bits of MSR value.
7251 <b>Example usage</b>
7255 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);
7256 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);
7258 @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.
7260 #define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38
7264 Package. Uncore R-box 1 perfmon counter MSR.
7266 @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)
7267 @param EAX Lower 32-bits of MSR value.
7268 @param EDX Upper 32-bits of MSR value.
7270 <b>Example usage</b>
7274 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);
7275 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);
7277 @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.
7279 #define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39
7283 Package. Uncore R-box 1 perfmon event select MSR.
7285 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)
7286 @param EAX Lower 32-bits of MSR value.
7287 @param EDX Upper 32-bits of MSR value.
7289 <b>Example usage</b>
7293 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);
7294 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);
7296 @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.
7298 #define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A
7302 Package. Uncore R-box 1perfmon counter MSR.
7304 @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)
7305 @param EAX Lower 32-bits of MSR value.
7306 @param EDX Upper 32-bits of MSR value.
7308 <b>Example usage</b>
7312 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);
7313 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);
7315 @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.
7317 #define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B
7321 Package. Uncore R-box 1 perfmon event select MSR.
7323 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)
7324 @param EAX Lower 32-bits of MSR value.
7325 @param EDX Upper 32-bits of MSR value.
7327 <b>Example usage</b>
7331 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);
7332 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);
7334 @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.
7336 #define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C
7340 Package. Uncore R-box 1 perfmon counter MSR.
7342 @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)
7343 @param EAX Lower 32-bits of MSR value.
7344 @param EDX Upper 32-bits of MSR value.
7346 <b>Example usage</b>
7350 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);
7351 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);
7353 @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.
7355 #define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D
7359 Package. Uncore R-box 1 perfmon event select MSR.
7361 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)
7362 @param EAX Lower 32-bits of MSR value.
7363 @param EDX Upper 32-bits of MSR value.
7365 <b>Example usage</b>
7369 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);
7370 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);
7372 @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.
7374 #define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E
7378 Package. Uncore R-box 1 perfmon counter MSR.
7380 @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)
7381 @param EAX Lower 32-bits of MSR value.
7382 @param EDX Upper 32-bits of MSR value.
7384 <b>Example usage</b>
7388 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);
7389 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);
7391 @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.
7393 #define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F
7397 Package. Uncore B-box 0 perfmon local box match MSR.
7399 @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)
7400 @param EAX Lower 32-bits of MSR value.
7401 @param EDX Upper 32-bits of MSR value.
7403 <b>Example usage</b>
7407 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);
7408 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);
7410 @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.
7412 #define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45
7416 Package. Uncore B-box 0 perfmon local box mask MSR.
7418 @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)
7419 @param EAX Lower 32-bits of MSR value.
7420 @param EDX Upper 32-bits of MSR value.
7422 <b>Example usage</b>
7426 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);
7427 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);
7429 @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.
7431 #define MSR_NEHALEM_B0_PMON_MASK 0x00000E46
7435 Package. Uncore S-box 0 perfmon local box match MSR.
7437 @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)
7438 @param EAX Lower 32-bits of MSR value.
7439 @param EDX Upper 32-bits of MSR value.
7441 <b>Example usage</b>
7445 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);
7446 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);
7448 @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.
7450 #define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49
7454 Package. Uncore S-box 0 perfmon local box mask MSR.
7456 @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)
7457 @param EAX Lower 32-bits of MSR value.
7458 @param EDX Upper 32-bits of MSR value.
7460 <b>Example usage</b>
7464 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);
7465 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);
7467 @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.
7469 #define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A
7473 Package. Uncore B-box 1 perfmon local box match MSR.
7475 @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)
7476 @param EAX Lower 32-bits of MSR value.
7477 @param EDX Upper 32-bits of MSR value.
7479 <b>Example usage</b>
7483 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);
7484 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);
7486 @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.
7488 #define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D
7492 Package. Uncore B-box 1 perfmon local box mask MSR.
7494 @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)
7495 @param EAX Lower 32-bits of MSR value.
7496 @param EDX Upper 32-bits of MSR value.
7498 <b>Example usage</b>
7502 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);
7503 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);
7505 @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.
7507 #define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E
7511 Package. Uncore M-box 0 perfmon local box address match/mask config MSR.
7513 @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)
7514 @param EAX Lower 32-bits of MSR value.
7515 @param EDX Upper 32-bits of MSR value.
7517 <b>Example usage</b>
7521 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);
7522 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);
7524 @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.
7526 #define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54
7530 Package. Uncore M-box 0 perfmon local box address match MSR.
7532 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)
7533 @param EAX Lower 32-bits of MSR value.
7534 @param EDX Upper 32-bits of MSR value.
7536 <b>Example usage</b>
7540 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);
7541 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);
7543 @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.
7545 #define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55
7549 Package. Uncore M-box 0 perfmon local box address mask MSR.
7551 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)
7552 @param EAX Lower 32-bits of MSR value.
7553 @param EDX Upper 32-bits of MSR value.
7555 <b>Example usage</b>
7559 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);
7560 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);
7562 @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.
7564 #define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56
7568 Package. Uncore S-box 1 perfmon local box match MSR.
7570 @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)
7571 @param EAX Lower 32-bits of MSR value.
7572 @param EDX Upper 32-bits of MSR value.
7574 <b>Example usage</b>
7578 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);
7579 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);
7581 @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.
7583 #define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59
7587 Package. Uncore S-box 1 perfmon local box mask MSR.
7589 @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)
7590 @param EAX Lower 32-bits of MSR value.
7591 @param EDX Upper 32-bits of MSR value.
7593 <b>Example usage</b>
7597 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);
7598 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);
7600 @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.
7602 #define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A
7606 Package. Uncore M-box 1 perfmon local box address match/mask config MSR.
7608 @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)
7609 @param EAX Lower 32-bits of MSR value.
7610 @param EDX Upper 32-bits of MSR value.
7612 <b>Example usage</b>
7616 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);
7617 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);
7619 @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.
7621 #define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C
7625 Package. Uncore M-box 1 perfmon local box address match MSR.
7627 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)
7628 @param EAX Lower 32-bits of MSR value.
7629 @param EDX Upper 32-bits of MSR value.
7631 <b>Example usage</b>
7635 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);
7636 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);
7638 @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.
7640 #define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D
7644 Package. Uncore M-box 1 perfmon local box address mask MSR.
7646 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)
7647 @param EAX Lower 32-bits of MSR value.
7648 @param EDX Upper 32-bits of MSR value.
7650 <b>Example usage</b>
7654 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);
7655 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);
7657 @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.
7659 #define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E