2 MSR Definitions for Pentium(R) 4 Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __PENTIUM_4_MSR_H__
25 #define __PENTIUM_4_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Pentium(R) 4 Processors?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x0F \
43 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range
46 @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)
47 @param EAX Lower 32-bits of MSR value.
48 @param EDX Upper 32-bits of MSR value.
54 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
55 AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);
57 @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.
59 #define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006
63 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)
64 Enables and disables processor features; (R) indicates current processor
67 @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)
68 @param EAX Lower 32-bits of MSR value.
69 Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
70 @param EDX Upper 32-bits of MSR value.
71 Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
75 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr;
77 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
78 AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);
80 @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.
82 #define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A
85 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON
89 /// Individual bit fields
93 /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state
94 /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.
95 /// The value in this bit is written on the deassertion of RESET#; the bit
96 /// is set to 1 when the address bus signal is asserted.
98 UINT32 OutputTriStateEnabled
:1;
100 /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST
101 /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The
102 /// value in this bit is written on the deassertion of RESET#; the bit is
103 /// set to 1 when the address bus signal is asserted.
105 UINT32 ExecuteBIST
:1;
107 /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue
108 /// depth for the system bus is 1 (1) or up to 12 (0) as set by the
109 /// strapping of A7#. The value in this bit is written on the deassertion
110 /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
112 UINT32 InOrderQueueDepth
:1;
114 /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#
115 /// observation is enabled (0) or disabled (1) as determined by the
116 /// strapping of A9#. The value in this bit is written on the deassertion
117 /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
119 UINT32 MCERR_ObservationDisabled
:1;
121 /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#
122 /// observation is enabled (0) or disabled (1) as determined by the
123 /// strapping of A10#. The value in this bit is written on the deassertion
124 /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
126 UINT32 BINIT_ObservationEnabled
:1;
128 /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID
129 /// value as set by the strapping of A12# and A11#. The logical cluster ID
130 /// value is written into the field on the deassertion of RESET#; the
131 /// field is set to 1 when the address bus signal is asserted.
133 UINT32 APICClusterID
:2;
135 /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled
136 /// (0) or disabled (1) as set by the strapping of A15#. The value in this
137 /// bit is written on the deassertion of RESET#; the bit is set to 1 when
138 /// the address bus signal is asserted.
140 UINT32 BusParkDisable
:1;
143 /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set
144 /// by the strapping of BR[3:0]. The logical ID value is written into the
145 /// field on the deassertion of RESET#; the field is set to 1 when the
146 /// address bus signal is asserted.
153 /// All bit fields as a 32-bit value
157 /// All bit fields as a 64-bit value
160 } MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
;
164 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)
165 Enables and disables processor features.
167 @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)
168 @param EAX Lower 32-bits of MSR value.
169 Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
170 @param EDX Upper 32-bits of MSR value.
171 Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
175 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr;
177 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);
178 AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);
180 @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.
182 #define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B
185 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON
189 /// Individual bit fields
193 /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the
194 /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear
195 /// to disabled (0, default).
199 /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data
200 /// bus parity checking; clear to enable parity checking.
202 UINT32 DataErrorCheckingDisable
:1;
204 /// [Bit 2] Response Error Checking Disable (R/W) Set to disable
205 /// (default); clear to enable.
207 UINT32 ResponseErrorCheckingDisable
:1;
209 /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable
210 /// (default); clear to enable.
212 UINT32 AddressRequestErrorCheckingDisable
:1;
214 /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving
215 /// for initiator bus requests (default); clear to enable.
217 UINT32 InitiatorMCERR_Disable
:1;
219 /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving
220 /// for initiator internal errors (default); clear to enable.
222 UINT32 InternalMCERR_Disable
:1;
224 /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver
225 /// (default); clear to enable driver.
227 UINT32 BINIT_DriverDisable
:1;
232 /// All bit fields as a 32-bit value
236 /// All bit fields as a 64-bit value
239 } MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
;
243 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of
244 this MSR varies according to the MODEL value in the CPUID version
245 information. The following bit field layout applies to Pentium 4 and Xeon
246 Processors with MODEL encoding equal or greater than 2. (R) The field
247 Indicates the current processor frequency configuration.
249 @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)
250 @param EAX Lower 32-bits of MSR value.
251 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
252 @param EDX Upper 32-bits of MSR value.
253 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
257 MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr;
259 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);
261 @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.
263 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C
266 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID
270 /// Individual bit fields
275 /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable
276 /// bus speed: *EncodingScalable Bus Speed*
278 /// 000B 100 MHz (Model 2).
279 /// 000B 266 MHz (Model 3 or 4)
283 /// 100B 333 MHz (Model 6)
285 /// 133.33 MHz should be utilized if performing calculation with System
286 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
287 /// performing calculation with System Bus Speed when encoding is 011B.
288 /// 266.67 MHz should be utilized if performing calculation with System
289 /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33
290 /// MHz should be utilized if performing calculation with System Bus
291 /// Speed when encoding is 100B and model encoding = 6. All other values
294 UINT32 ScalableBusSpeed
:3;
297 /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)
298 /// The processor core clock frequency to system bus frequency ratio
299 /// observed at the de-assertion of the reset pin.
305 /// All bit fields as a 32-bit value
309 /// All bit fields as a 64-bit value
312 } MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER
;
316 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of
317 this MSR varies according to the MODEL value of the CPUID version
318 information. This bit field layout applies to Pentium 4 and Xeon Processors
319 with MODEL encoding less than 2. Indicates current processor frequency
322 @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)
323 @param EAX Lower 32-bits of MSR value.
324 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
325 @param EDX Upper 32-bits of MSR value.
326 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
330 MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr;
332 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);
334 @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.
336 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C
339 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1
343 /// Individual bit fields
348 /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable
349 /// bus speed: *Encoding* *Scalable Bus Speed*
351 /// 000B 100 MHz All others values reserved.
353 UINT32 ScalableBusSpeed
:3;
358 /// All bit fields as a 32-bit value
362 /// All bit fields as a 64-bit value
365 } MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER
;
369 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section
370 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
371 state at time of machine check error. When in non-64-bit modes at the time
372 of the error, bits 63-32 do not contain valid data.
374 @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180)
375 @param EAX Lower 32-bits of MSR value.
376 @param EDX Upper 32-bits of MSR value.
382 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);
383 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);
385 @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.
387 #define MSR_PENTIUM_4_MCG_RAX 0x00000180
391 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section
392 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
393 state at time of machine check error. When in non-64-bit modes at the time
394 of the error, bits 63-32 do not contain valid data.
396 @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181)
397 @param EAX Lower 32-bits of MSR value.
398 @param EDX Upper 32-bits of MSR value.
404 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);
405 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);
407 @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.
409 #define MSR_PENTIUM_4_MCG_RBX 0x00000181
413 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section
414 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
415 state at time of machine check error. When in non-64-bit modes at the time
416 of the error, bits 63-32 do not contain valid data.
418 @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182)
419 @param EAX Lower 32-bits of MSR value.
420 @param EDX Upper 32-bits of MSR value.
426 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);
427 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);
429 @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.
431 #define MSR_PENTIUM_4_MCG_RCX 0x00000182
435 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section
436 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
437 state at time of machine check error. When in non-64-bit modes at the time
438 of the error, bits 63-32 do not contain valid data.
440 @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183)
441 @param EAX Lower 32-bits of MSR value.
442 @param EDX Upper 32-bits of MSR value.
448 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);
449 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);
451 @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.
453 #define MSR_PENTIUM_4_MCG_RDX 0x00000183
457 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section
458 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
459 state at time of machine check error. When in non-64-bit modes at the time
460 of the error, bits 63-32 do not contain valid data.
462 @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184)
463 @param EAX Lower 32-bits of MSR value.
464 @param EDX Upper 32-bits of MSR value.
470 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);
471 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);
473 @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.
475 #define MSR_PENTIUM_4_MCG_RSI 0x00000184
479 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section
480 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
481 state at time of machine check error. When in non-64-bit modes at the time
482 of the error, bits 63-32 do not contain valid data.
484 @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185)
485 @param EAX Lower 32-bits of MSR value.
486 @param EDX Upper 32-bits of MSR value.
492 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);
493 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);
495 @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.
497 #define MSR_PENTIUM_4_MCG_RDI 0x00000185
501 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section
502 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
503 state at time of machine check error. When in non-64-bit modes at the time
504 of the error, bits 63-32 do not contain valid data.
506 @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186)
507 @param EAX Lower 32-bits of MSR value.
508 @param EDX Upper 32-bits of MSR value.
514 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);
515 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);
517 @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.
519 #define MSR_PENTIUM_4_MCG_RBP 0x00000186
523 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section
524 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
525 state at time of machine check error. When in non-64-bit modes at the time
526 of the error, bits 63-32 do not contain valid data.
528 @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187)
529 @param EAX Lower 32-bits of MSR value.
530 @param EDX Upper 32-bits of MSR value.
536 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);
537 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);
539 @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.
541 #define MSR_PENTIUM_4_MCG_RSP 0x00000187
545 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section
546 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
547 state at time of machine check error. When in non-64-bit modes at the time
548 of the error, bits 63-32 do not contain valid data.
550 @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)
551 @param EAX Lower 32-bits of MSR value.
552 @param EDX Upper 32-bits of MSR value.
558 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);
559 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);
561 @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.
563 #define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188
567 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section
568 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
569 state at time of machine check error. When in non-64-bit modes at the time
570 of the error, bits 63-32 do not contain valid data.
572 @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189)
573 @param EAX Lower 32-bits of MSR value.
574 @param EDX Upper 32-bits of MSR value.
580 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);
581 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);
583 @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.
585 #define MSR_PENTIUM_4_MCG_RIP 0x00000189
589 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,
590 "IA32_MCG Extended Machine Check State MSRs.".
592 @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A)
593 @param EAX Lower 32-bits of MSR value.
594 Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
595 @param EDX Upper 32-bits of MSR value.
596 Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
600 MSR_PENTIUM_4_MCG_MISC_REGISTER Msr;
602 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);
603 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);
605 @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.
607 #define MSR_PENTIUM_4_MCG_MISC 0x0000018A
610 MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC
614 /// Individual bit fields
618 /// [Bit 0] DS When set, the bit indicates that a page assist or page
619 /// fault occurred during DS normal operation. The processors response is
620 /// to shut down. The bit is used as an aid for debugging DS handling
621 /// code. It is the responsibility of the user (BIOS or operating system)
622 /// to clear this bit for normal operation.
629 /// All bit fields as a 32-bit value
633 /// All bit fields as a 64-bit value
636 } MSR_PENTIUM_4_MCG_MISC_REGISTER
;
640 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG
641 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
642 state-save MSRs) exist only in Intel 64 processors. These registers contain
643 valid information only when the processor is operating in 64-bit mode at the
646 @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190)
647 @param EAX Lower 32-bits of MSR value.
648 @param EDX Upper 32-bits of MSR value.
654 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);
655 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);
657 @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.
659 #define MSR_PENTIUM_4_MCG_R8 0x00000190
663 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,
664 "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the
665 associated state-save MSRs) exist only in Intel 64 processors. These
666 registers contain valid information only when the processor is operating in
667 64-bit mode at the time of the error.
669 @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191)
670 @param EAX Lower 32-bits of MSR value.
671 @param EDX Upper 32-bits of MSR value.
677 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);
678 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);
680 @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.
682 #define MSR_PENTIUM_4_MCG_R9 0x00000191
686 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG
687 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
688 state-save MSRs) exist only in Intel 64 processors. These registers contain
689 valid information only when the processor is operating in 64-bit mode at the
692 @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192)
693 @param EAX Lower 32-bits of MSR value.
694 @param EDX Upper 32-bits of MSR value.
700 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);
701 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);
703 @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.
705 #define MSR_PENTIUM_4_MCG_R10 0x00000192
709 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG
710 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
711 state-save MSRs) exist only in Intel 64 processors. These registers contain
712 valid information only when the processor is operating in 64-bit mode at the
715 @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193)
716 @param EAX Lower 32-bits of MSR value.
717 @param EDX Upper 32-bits of MSR value.
723 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);
724 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);
726 @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.
728 #define MSR_PENTIUM_4_MCG_R11 0x00000193
732 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG
733 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
734 state-save MSRs) exist only in Intel 64 processors. These registers contain
735 valid information only when the processor is operating in 64-bit mode at the
738 @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194)
739 @param EAX Lower 32-bits of MSR value.
740 @param EDX Upper 32-bits of MSR value.
746 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);
747 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);
749 @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.
751 #define MSR_PENTIUM_4_MCG_R12 0x00000194
755 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG
756 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
757 state-save MSRs) exist only in Intel 64 processors. These registers contain
758 valid information only when the processor is operating in 64-bit mode at the
761 @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195)
762 @param EAX Lower 32-bits of MSR value.
763 @param EDX Upper 32-bits of MSR value.
769 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);
770 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);
772 @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.
774 #define MSR_PENTIUM_4_MCG_R13 0x00000195
778 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG
779 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
780 state-save MSRs) exist only in Intel 64 processors. These registers contain
781 valid information only when the processor is operating in 64-bit mode at the
784 @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196)
785 @param EAX Lower 32-bits of MSR value.
786 @param EDX Upper 32-bits of MSR value.
792 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);
793 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);
795 @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.
797 #define MSR_PENTIUM_4_MCG_R14 0x00000196
801 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG
802 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
803 state-save MSRs) exist only in Intel 64 processors. These registers contain
804 valid information only when the processor is operating in 64-bit mode at the
807 @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197)
808 @param EAX Lower 32-bits of MSR value.
809 @param EDX Upper 32-bits of MSR value.
815 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);
816 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);
818 @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.
820 #define MSR_PENTIUM_4_MCG_R15 0x00000197
824 Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:
825 When read, specifies the value of the target TM2 transition last written.
826 When set, it sets the next target value for TM2 transition. 4, 6. Shared.
827 For Family F, Model 4 and Model 6 processors: When read, specifies the value
828 of the target TM2 transition last written. Writes may cause #GP exceptions.
830 @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D)
831 @param EAX Lower 32-bits of MSR value.
832 @param EDX Upper 32-bits of MSR value.
838 Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);
839 AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);
841 @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
843 #define MSR_PENTIUM_4_THERM2_CTL 0x0000019D
847 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).
849 @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)
850 @param EAX Lower 32-bits of MSR value.
851 Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
852 @param EDX Upper 32-bits of MSR value.
853 Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
857 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr;
859 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);
860 AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);
862 @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
864 #define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0
867 MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE
871 /// Individual bit fields
875 /// [Bit 0] Fast-Strings Enable. See Table 2-2.
877 UINT32 FastStrings
:1;
880 /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.
884 /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal
885 /// Monitor," and see Table 2-2.
889 /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception
890 /// to be issued instead of a split-lock cycle. Operating systems that set
891 /// this bit must align system structures to avoid split-lock scenarios.
892 /// When the bit is clear (default), normal split-locks are issued to the
894 /// This debug feature is specific to the Pentium 4 processor.
896 UINT32 SplitLockDisable
:1;
899 /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level
900 /// cache is disabled; when clear (default) the third-level cache is
901 /// enabled. This flag is reserved for processors that do not have a
902 /// third-level cache. Note that the bit controls only the third-level
903 /// cache; and only if overall caching is enabled through the CD flag of
904 /// control register CR0, the page-level cache controls, and/or the MTRRs.
905 /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".
907 UINT32 ThirdLevelCacheDisable
:1;
909 /// [Bit 7] Performance Monitoring Available (R) See Table 2-2.
911 UINT32 PerformanceMonitoring
:1;
913 /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is
914 /// suppressed during a Split Lock access. When clear (default), LOCK is
917 UINT32 SuppressLockEnable
:1;
919 /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.
920 /// When clear (default), enables the prefetch queue.
922 UINT32 PrefetchQueueDisable
:1;
924 /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt
925 /// reporting through the FERR# pin is enabled; when clear, this interrupt
926 /// reporting function is disabled.
927 /// When this flag is set and the processor is in the stop-clock state
928 /// (STPCLK# is asserted), asserting the FERR# pin signals to the
929 /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,
930 /// SMI#, or RESET#) is pending and that the processor should return to
931 /// normal operation to handle the interrupt. This flag does not affect
932 /// the normal operation of the FERR# pin (to indicate an unmasked
933 /// floatingpoint error) when the STPCLK# pin is not asserted.
937 /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See
938 /// Table 2-2. When set, the processor does not support branch trace
939 /// storage (BTS); when clear, BTS is supported.
943 /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable
944 /// (R) See Table 2-2. When set, the processor does not support processor
945 /// event-based sampling (PEBS); when clear, PEBS is supported.
949 /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal
950 /// sensor indicates that the die temperature is at the predetermined
951 /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce
952 /// the bus to core ratio and voltage according to the value last written
953 /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the
954 /// processor does not change the VID signals or the bus to core ratio
955 /// when the processor enters a thermal managed state. If the TM2 feature
956 /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then
957 /// this feature is not supported and BIOS must not alter the contents of
958 /// this bit location. The processor is operating out of spec if both this
959 /// bit and the TM1 bit are set to disabled states.
964 /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.
968 /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,
969 /// the processor fetches the cache line of the 128-byte sector containing
970 /// currently required data. When set to 0, the processor fetches both
971 /// cache lines in the sector.
972 /// Single processor platforms should not set this bit. Server platforms
973 /// should set or clear this bit based on platform performance observed
974 /// in validation and testing. BIOS may contain a setup option that
975 /// controls the setting of this bit.
977 UINT32 AdjacentCacheLinePrefetchDisable
:1;
980 /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this
981 /// can cause unexpected behavior to software that depends on the
982 /// availability of CPUID leaves greater than 3.
984 UINT32 LimitCpuidMaxval
:1;
986 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
988 UINT32 xTPR_Message_Disable
:1;
990 /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache
991 /// is placed in shared mode; when clear (default), the cache is placed in
992 /// adaptive mode. This bit is only enabled for IA-32 processors that
993 /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data
994 /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are
995 /// identical, data in L1 is shared across logical processors. Otherwise,
996 /// L1 is not shared and cache use is competitive. If the Context ID
997 /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,
998 /// the ability to switch modes is not supported. BIOS must not alter the
999 /// contents of IA32_MISC_ENABLE[24].
1001 UINT32 L1DataCacheContextMode
:1;
1005 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
1008 UINT32 Reserved7
:29;
1011 /// All bit fields as a 64-bit value
1014 } MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
;
1018 3, 4, 6. Shared. Platform Feature Requirements (R).
1020 @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)
1021 @param EAX Lower 32-bits of MSR value.
1022 Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
1023 @param EDX Upper 32-bits of MSR value.
1024 Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
1026 <b>Example usage</b>
1028 MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr;
1030 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);
1032 @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.
1034 #define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1
1037 MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV
1041 /// Individual bit fields
1044 UINT32 Reserved1
:18;
1046 /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor
1047 /// has specific platform requirements. The details of the platform
1048 /// requirements are listed in the respective data sheets of the processor.
1051 UINT32 Reserved2
:13;
1052 UINT32 Reserved3
:32;
1055 /// All bit fields as a 32-bit value
1059 /// All bit fields as a 64-bit value
1062 } MSR_PENTIUM_4_PLATFORM_BRV_REGISTER
;
1066 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains
1067 a pointer to the last branch instruction that the processor executed prior
1068 to the last exception that was generated or the last interrupt that was
1069 handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear
1070 IP Linear address of the last branch instruction (If IA-32e mode is active).
1071 From Linear IP Linear address of the last branch instruction. Reserved.
1073 @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)
1074 @param EAX Lower 32-bits of MSR value.
1075 @param EDX Upper 32-bits of MSR value.
1077 <b>Example usage</b>
1081 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);
1083 @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
1085 #define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7
1089 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area
1090 contains a pointer to the target of the last branch instruction that the
1091 processor executed prior to the last exception that was generated or the
1092 last interrupt that was handled. See Section 17.13.3, "Last Exception
1093 Records.". Unique. From Linear IP Linear address of the target of the last
1094 branch instruction (If IA-32e mode is active). From Linear IP Linear address
1095 of the target of the last branch instruction. Reserved.
1097 @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)
1098 @param EAX Lower 32-bits of MSR value.
1099 @param EDX Upper 32-bits of MSR value.
1101 <b>Example usage</b>
1105 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);
1107 @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
1109 #define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8
1113 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug
1114 features are used. Bit definitions are discussed in the referenced section.
1115 See Section 17.13.1, "MSR_DEBUGCTLA MSR.".
1117 @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
1118 @param EAX Lower 32-bits of MSR value.
1119 @param EDX Upper 32-bits of MSR value.
1121 <b>Example usage</b>
1125 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);
1126 AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);
1128 @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.
1130 #define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9
1134 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an
1135 index (0-3 or 0-15) that points to the top of the last branch record stack
1136 (that is, that points the index of the MSR containing the most recent branch
1137 record). See Section 17.13.2, "LBR Stack for Processors Based on Intel
1138 NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.
1140 @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
1141 @param EAX Lower 32-bits of MSR value.
1142 @param EDX Upper 32-bits of MSR value.
1144 <b>Example usage</b>
1148 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);
1149 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);
1151 @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
1153 #define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA
1157 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record
1158 registers on the last branch record stack. It contains pointers to the
1159 source and destination instruction for one of the last four branches,
1160 exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through
1161 MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models
1162 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See
1163 Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
1164 for Processors based on Skylake Microarchitecture.".
1166 @param ECX MSR_PENTIUM_4_LASTBRANCH_n
1167 @param EAX Lower 32-bits of MSR value.
1168 @param EDX Upper 32-bits of MSR value.
1170 <b>Example usage</b>
1174 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
1175 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);
1177 @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
1178 MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
1179 MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
1180 MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
1183 #define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB
1184 #define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC
1185 #define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD
1186 #define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE
1191 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
1193 @param ECX MSR_PENTIUM_4_BPU_COUNTERn
1194 @param EAX Lower 32-bits of MSR value.
1195 @param EDX Upper 32-bits of MSR value.
1197 <b>Example usage</b>
1201 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
1202 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);
1204 @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM.
1205 MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM.
1206 MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM.
1207 MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.
1210 #define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300
1211 #define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301
1212 #define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302
1213 #define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303
1218 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
1220 @param ECX MSR_PENTIUM_4_MS_COUNTERn
1221 @param EAX Lower 32-bits of MSR value.
1222 @param EDX Upper 32-bits of MSR value.
1224 <b>Example usage</b>
1228 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
1229 AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);
1231 @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM.
1232 MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM.
1233 MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM.
1234 MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.
1237 #define MSR_PENTIUM_4_MS_COUNTER0 0x00000304
1238 #define MSR_PENTIUM_4_MS_COUNTER1 0x00000305
1239 #define MSR_PENTIUM_4_MS_COUNTER2 0x00000306
1240 #define MSR_PENTIUM_4_MS_COUNTER3 0x00000307
1245 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
1247 @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
1248 @param EAX Lower 32-bits of MSR value.
1249 @param EDX Upper 32-bits of MSR value.
1251 <b>Example usage</b>
1255 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
1256 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);
1258 @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM.
1259 MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM.
1260 MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM.
1261 MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.
1264 #define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308
1265 #define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309
1266 #define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A
1267 #define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B
1272 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
1274 @param ECX MSR_PENTIUM_4_IQ_COUNTERn
1275 @param EAX Lower 32-bits of MSR value.
1276 @param EDX Upper 32-bits of MSR value.
1278 <b>Example usage</b>
1282 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
1283 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);
1285 @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM.
1286 MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM.
1287 MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM.
1288 MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM.
1289 MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM.
1290 MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.
1293 #define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C
1294 #define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D
1295 #define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E
1296 #define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F
1297 #define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310
1298 #define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311
1303 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
1305 @param ECX MSR_PENTIUM_4_BPU_CCCRn
1306 @param EAX Lower 32-bits of MSR value.
1307 @param EDX Upper 32-bits of MSR value.
1309 <b>Example usage</b>
1313 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
1314 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);
1316 @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM.
1317 MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM.
1318 MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM.
1319 MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.
1322 #define MSR_PENTIUM_4_BPU_CCCR0 0x00000360
1323 #define MSR_PENTIUM_4_BPU_CCCR1 0x00000361
1324 #define MSR_PENTIUM_4_BPU_CCCR2 0x00000362
1325 #define MSR_PENTIUM_4_BPU_CCCR3 0x00000363
1330 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
1332 @param ECX MSR_PENTIUM_4_MS_CCCRn
1333 @param EAX Lower 32-bits of MSR value.
1334 @param EDX Upper 32-bits of MSR value.
1336 <b>Example usage</b>
1340 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
1341 AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);
1343 @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM.
1344 MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM.
1345 MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM.
1346 MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.
1349 #define MSR_PENTIUM_4_MS_CCCR0 0x00000364
1350 #define MSR_PENTIUM_4_MS_CCCR1 0x00000365
1351 #define MSR_PENTIUM_4_MS_CCCR2 0x00000366
1352 #define MSR_PENTIUM_4_MS_CCCR3 0x00000367
1357 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
1359 @param ECX MSR_PENTIUM_4_FLAME_CCCRn
1360 @param EAX Lower 32-bits of MSR value.
1361 @param EDX Upper 32-bits of MSR value.
1363 <b>Example usage</b>
1367 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
1368 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);
1370 @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM.
1371 MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM.
1372 MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM.
1373 MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.
1376 #define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368
1377 #define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369
1378 #define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A
1379 #define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B
1384 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
1386 @param ECX MSR_PENTIUM_4_IQ_CCCRn
1387 @param EAX Lower 32-bits of MSR value.
1388 @param EDX Upper 32-bits of MSR value.
1390 <b>Example usage</b>
1394 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
1395 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);
1397 @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM.
1398 MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM.
1399 MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM.
1400 MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM.
1401 MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM.
1402 MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.
1405 #define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C
1406 #define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D
1407 #define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E
1408 #define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F
1409 #define MSR_PENTIUM_4_IQ_CCCR4 0x00000370
1410 #define MSR_PENTIUM_4_IQ_CCCR5 0x00000371
1415 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1417 @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
1418 @param EAX Lower 32-bits of MSR value.
1419 @param EDX Upper 32-bits of MSR value.
1421 <b>Example usage</b>
1425 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);
1426 AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);
1428 @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.
1430 #define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0
1434 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1436 @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
1437 @param EAX Lower 32-bits of MSR value.
1438 @param EDX Upper 32-bits of MSR value.
1440 <b>Example usage</b>
1444 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);
1445 AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);
1447 @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.
1449 #define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1
1453 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1455 @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
1456 @param EAX Lower 32-bits of MSR value.
1457 @param EDX Upper 32-bits of MSR value.
1459 <b>Example usage</b>
1463 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);
1464 AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);
1466 @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.
1468 #define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2
1472 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1474 @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
1475 @param EAX Lower 32-bits of MSR value.
1476 @param EDX Upper 32-bits of MSR value.
1478 <b>Example usage</b>
1482 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);
1483 AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);
1485 @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.
1487 #define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3
1491 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1493 @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
1494 @param EAX Lower 32-bits of MSR value.
1495 @param EDX Upper 32-bits of MSR value.
1497 <b>Example usage</b>
1501 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);
1502 AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);
1504 @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.
1506 #define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4
1510 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1512 @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
1513 @param EAX Lower 32-bits of MSR value.
1514 @param EDX Upper 32-bits of MSR value.
1516 <b>Example usage</b>
1520 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);
1521 AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);
1523 @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.
1525 #define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5
1529 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1531 @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
1532 @param EAX Lower 32-bits of MSR value.
1533 @param EDX Upper 32-bits of MSR value.
1535 <b>Example usage</b>
1539 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);
1540 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);
1542 @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.
1544 #define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6
1548 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1550 @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
1551 @param EAX Lower 32-bits of MSR value.
1552 @param EDX Upper 32-bits of MSR value.
1554 <b>Example usage</b>
1558 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);
1559 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);
1561 @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.
1563 #define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7
1567 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1569 @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
1570 @param EAX Lower 32-bits of MSR value.
1571 @param EDX Upper 32-bits of MSR value.
1573 <b>Example usage</b>
1577 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);
1578 AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);
1580 @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.
1582 #define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8
1586 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1588 @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
1589 @param EAX Lower 32-bits of MSR value.
1590 @param EDX Upper 32-bits of MSR value.
1592 <b>Example usage</b>
1596 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);
1597 AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);
1599 @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.
1601 #define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9
1605 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1607 @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
1608 @param EAX Lower 32-bits of MSR value.
1609 @param EDX Upper 32-bits of MSR value.
1611 <b>Example usage</b>
1615 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);
1616 AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);
1618 @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.
1620 #define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA
1624 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1626 @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
1627 @param EAX Lower 32-bits of MSR value.
1628 @param EDX Upper 32-bits of MSR value.
1630 <b>Example usage</b>
1634 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);
1635 AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);
1637 @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.
1639 #define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB
1643 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1645 @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
1646 @param EAX Lower 32-bits of MSR value.
1647 @param EDX Upper 32-bits of MSR value.
1649 <b>Example usage</b>
1653 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);
1654 AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);
1656 @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.
1658 #define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC
1662 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1664 @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
1665 @param EAX Lower 32-bits of MSR value.
1666 @param EDX Upper 32-bits of MSR value.
1668 <b>Example usage</b>
1672 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);
1673 AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);
1675 @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.
1677 #define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD
1681 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1683 @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
1684 @param EAX Lower 32-bits of MSR value.
1685 @param EDX Upper 32-bits of MSR value.
1687 <b>Example usage</b>
1691 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);
1692 AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);
1694 @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.
1696 #define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE
1700 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1702 @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
1703 @param EAX Lower 32-bits of MSR value.
1704 @param EDX Upper 32-bits of MSR value.
1706 <b>Example usage</b>
1710 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);
1711 AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);
1713 @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.
1715 #define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF
1719 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1721 @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
1722 @param EAX Lower 32-bits of MSR value.
1723 @param EDX Upper 32-bits of MSR value.
1725 <b>Example usage</b>
1729 Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);
1730 AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);
1732 @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.
1734 #define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0
1738 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1740 @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
1741 @param EAX Lower 32-bits of MSR value.
1742 @param EDX Upper 32-bits of MSR value.
1744 <b>Example usage</b>
1748 Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);
1749 AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);
1751 @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.
1753 #define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1
1757 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1759 @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
1760 @param EAX Lower 32-bits of MSR value.
1761 @param EDX Upper 32-bits of MSR value.
1763 <b>Example usage</b>
1767 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);
1768 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);
1770 @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.
1772 #define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2
1776 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1778 @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
1779 @param EAX Lower 32-bits of MSR value.
1780 @param EDX Upper 32-bits of MSR value.
1782 <b>Example usage</b>
1786 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);
1787 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);
1789 @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.
1791 #define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3
1795 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1797 @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
1798 @param EAX Lower 32-bits of MSR value.
1799 @param EDX Upper 32-bits of MSR value.
1801 <b>Example usage</b>
1805 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);
1806 AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);
1808 @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.
1810 #define MSR_PENTIUM_4_IS_ESCR0 0x000003B4
1814 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1816 @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
1817 @param EAX Lower 32-bits of MSR value.
1818 @param EDX Upper 32-bits of MSR value.
1820 <b>Example usage</b>
1824 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);
1825 AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);
1827 @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.
1829 #define MSR_PENTIUM_4_IS_ESCR1 0x000003B5
1833 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1835 @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
1836 @param EAX Lower 32-bits of MSR value.
1837 @param EDX Upper 32-bits of MSR value.
1839 <b>Example usage</b>
1843 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);
1844 AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);
1846 @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.
1848 #define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6
1852 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1854 @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
1855 @param EAX Lower 32-bits of MSR value.
1856 @param EDX Upper 32-bits of MSR value.
1858 <b>Example usage</b>
1862 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);
1863 AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);
1865 @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.
1867 #define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7
1871 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1873 @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
1874 @param EAX Lower 32-bits of MSR value.
1875 @param EDX Upper 32-bits of MSR value.
1877 <b>Example usage</b>
1881 Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);
1882 AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);
1884 @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.
1886 #define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8
1890 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1892 @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
1893 @param EAX Lower 32-bits of MSR value.
1894 @param EDX Upper 32-bits of MSR value.
1896 <b>Example usage</b>
1900 Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);
1901 AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);
1903 @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.
1905 #define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9
1909 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
1910 available on later processors. It is only available on processor family 0FH,
1913 @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)
1914 @param EAX Lower 32-bits of MSR value.
1915 @param EDX Upper 32-bits of MSR value.
1917 <b>Example usage</b>
1921 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);
1922 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);
1924 @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.
1926 #define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA
1930 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
1931 available on later processors. It is only available on processor family 0FH,
1934 @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)
1935 @param EAX Lower 32-bits of MSR value.
1936 @param EDX Upper 32-bits of MSR value.
1938 <b>Example usage</b>
1942 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);
1943 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);
1945 @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.
1947 #define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB
1951 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1953 @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
1954 @param EAX Lower 32-bits of MSR value.
1955 @param EDX Upper 32-bits of MSR value.
1957 <b>Example usage</b>
1961 Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);
1962 AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);
1964 @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.
1966 #define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC
1970 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1972 @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
1973 @param EAX Lower 32-bits of MSR value.
1974 @param EDX Upper 32-bits of MSR value.
1976 <b>Example usage</b>
1980 Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);
1981 AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);
1983 @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.
1985 #define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD
1989 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1991 @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
1992 @param EAX Lower 32-bits of MSR value.
1993 @param EDX Upper 32-bits of MSR value.
1995 <b>Example usage</b>
1999 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);
2000 AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);
2002 @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.
2004 #define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE
2008 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2010 @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
2011 @param EAX Lower 32-bits of MSR value.
2012 @param EDX Upper 32-bits of MSR value.
2014 <b>Example usage</b>
2018 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);
2019 AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);
2021 @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.
2023 #define MSR_PENTIUM_4_MS_ESCR0 0x000003C0
2027 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2029 @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
2030 @param EAX Lower 32-bits of MSR value.
2031 @param EDX Upper 32-bits of MSR value.
2033 <b>Example usage</b>
2037 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);
2038 AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);
2040 @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.
2042 #define MSR_PENTIUM_4_MS_ESCR1 0x000003C1
2046 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2048 @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
2049 @param EAX Lower 32-bits of MSR value.
2050 @param EDX Upper 32-bits of MSR value.
2052 <b>Example usage</b>
2056 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);
2057 AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);
2059 @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.
2061 #define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2
2065 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2067 @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
2068 @param EAX Lower 32-bits of MSR value.
2069 @param EDX Upper 32-bits of MSR value.
2071 <b>Example usage</b>
2075 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);
2076 AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);
2078 @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.
2080 #define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3
2084 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2086 @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
2087 @param EAX Lower 32-bits of MSR value.
2088 @param EDX Upper 32-bits of MSR value.
2090 <b>Example usage</b>
2094 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);
2095 AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);
2097 @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.
2099 #define MSR_PENTIUM_4_TC_ESCR0 0x000003C4
2103 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2105 @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
2106 @param EAX Lower 32-bits of MSR value.
2107 @param EDX Upper 32-bits of MSR value.
2109 <b>Example usage</b>
2113 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);
2114 AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);
2116 @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.
2118 #define MSR_PENTIUM_4_TC_ESCR1 0x000003C5
2122 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2124 @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
2125 @param EAX Lower 32-bits of MSR value.
2126 @param EDX Upper 32-bits of MSR value.
2128 <b>Example usage</b>
2132 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);
2133 AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);
2135 @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.
2137 #define MSR_PENTIUM_4_IX_ESCR0 0x000003C8
2141 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2143 @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
2144 @param EAX Lower 32-bits of MSR value.
2145 @param EDX Upper 32-bits of MSR value.
2147 <b>Example usage</b>
2151 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);
2152 AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);
2154 @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.
2156 #define MSR_PENTIUM_4_IX_ESCR1 0x000003C9
2160 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2162 @param ECX MSR_PENTIUM_4_ALF_ESCRn
2163 @param EAX Lower 32-bits of MSR value.
2164 @param EDX Upper 32-bits of MSR value.
2166 <b>Example usage</b>
2170 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
2171 AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);
2173 @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM.
2174 MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM.
2175 MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM.
2176 MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM.
2177 MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM.
2178 MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.
2181 #define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA
2182 #define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB
2183 #define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC
2184 #define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD
2185 #define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0
2186 #define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1
2191 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2193 @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
2194 @param EAX Lower 32-bits of MSR value.
2195 @param EDX Upper 32-bits of MSR value.
2197 <b>Example usage</b>
2201 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);
2202 AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);
2204 @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.
2206 #define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0
2210 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)
2211 Controls the enabling of processor event sampling and replay tagging.
2213 @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)
2214 @param EAX Lower 32-bits of MSR value.
2215 Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
2216 @param EDX Upper 32-bits of MSR value.
2217 Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
2219 <b>Example usage</b>
2221 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr;
2223 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);
2224 AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);
2226 @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
2228 #define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1
2231 MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE
2235 /// Individual bit fields
2239 /// [Bits 12:0] See Table 19-36.
2242 UINT32 Reserved1
:11;
2244 /// [Bit 24] UOP Tag Enables replay tagging when set.
2248 /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical
2249 /// processor when set; disables PEBS when clear (default). See Section
2250 /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
2251 /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors
2252 /// that do not support Intel HyperThreading Technology.
2254 UINT32 ENABLE_PEBS_MY_THR
:1;
2256 /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical
2257 /// processor when set; disables PEBS when clear (default). See Section
2258 /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
2259 /// logical processor. This bit is reserved for IA-32 processors that do
2260 /// not support Intel Hyper-Threading Technology.
2262 UINT32 ENABLE_PEBS_OTH_THR
:1;
2264 UINT32 Reserved3
:32;
2267 /// All bit fields as a 32-bit value
2271 /// All bit fields as a 64-bit value
2274 } MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
;
2278 0, 1, 2, 3, 4, 6. Shared. See Table 19-36.
2280 @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
2281 @param EAX Lower 32-bits of MSR value.
2282 @param EDX Upper 32-bits of MSR value.
2284 <b>Example usage</b>
2288 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);
2289 AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);
2291 @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.
2293 #define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2
2297 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch
2298 record registers on the last branch record stack (680H-68FH). This part of
2299 the stack contains pointers to the source instruction for one of the last 16
2300 branches, exceptions, or interrupts taken by the processor. The MSRs at
2301 680H-68FH, 6C0H-6CfH are not available in processor releases before family
2302 0FH, model 03H. These MSRs replace MSRs previously located at
2303 1DBH-1DEH.which performed the same function for early releases. See Section
2304 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for
2305 Processors based on Skylake Microarchitecture.".
2307 @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
2308 @param EAX Lower 32-bits of MSR value.
2309 @param EDX Upper 32-bits of MSR value.
2311 <b>Example usage</b>
2315 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
2316 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);
2318 @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
2319 MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
2320 MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
2321 MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
2322 MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
2323 MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
2324 MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
2325 MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
2326 MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
2327 MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
2328 MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
2329 MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
2330 MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
2331 MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
2332 MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
2333 MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
2336 #define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680
2337 #define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681
2338 #define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682
2339 #define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683
2340 #define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684
2341 #define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685
2342 #define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686
2343 #define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687
2344 #define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688
2345 #define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689
2346 #define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A
2347 #define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B
2348 #define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C
2349 #define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D
2350 #define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E
2351 #define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F
2356 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch
2357 record registers on the last branch record stack (6C0H-6CFH). This part of
2358 the stack contains pointers to the destination instruction for one of the
2359 last 16 branches, exceptions, or interrupts that the processor took. See
2360 Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
2361 for Processors based on Skylake Microarchitecture.".
2363 @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
2364 @param EAX Lower 32-bits of MSR value.
2365 @param EDX Upper 32-bits of MSR value.
2367 <b>Example usage</b>
2371 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
2372 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);
2374 @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
2375 MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
2376 MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
2377 MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
2378 MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
2379 MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
2380 MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
2381 MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
2382 MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
2383 MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
2384 MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
2385 MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
2386 MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
2387 MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
2388 MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
2389 MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
2392 #define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0
2393 #define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1
2394 #define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2
2395 #define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3
2396 #define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4
2397 #define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5
2398 #define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6
2399 #define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7
2400 #define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8
2401 #define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9
2402 #define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA
2403 #define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB
2404 #define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC
2405 #define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD
2406 #define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE
2407 #define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF
2412 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section
2413 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
2416 @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
2417 @param EAX Lower 32-bits of MSR value.
2418 @param EDX Upper 32-bits of MSR value.
2420 <b>Example usage</b>
2424 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);
2425 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);
2427 @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.
2429 #define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC
2433 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).
2435 @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)
2436 @param EAX Lower 32-bits of MSR value.
2437 @param EDX Upper 32-bits of MSR value.
2439 <b>Example usage</b>
2443 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);
2444 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);
2446 @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.
2448 #define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD
2452 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section
2453 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
2456 @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
2457 @param EAX Lower 32-bits of MSR value.
2458 @param EDX Upper 32-bits of MSR value.
2460 <b>Example usage</b>
2464 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);
2465 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);
2467 @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.
2469 #define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE
2473 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).
2475 @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)
2476 @param EAX Lower 32-bits of MSR value.
2477 @param EDX Upper 32-bits of MSR value.
2479 <b>Example usage</b>
2483 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);
2484 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);
2486 @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.
2488 #define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF
2492 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section
2493 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
2496 @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
2497 @param EAX Lower 32-bits of MSR value.
2498 @param EDX Upper 32-bits of MSR value.
2500 <b>Example usage</b>
2504 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);
2505 AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);
2507 @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.
2509 #define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0
2513 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).
2515 @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)
2516 @param EAX Lower 32-bits of MSR value.
2517 @param EDX Upper 32-bits of MSR value.
2519 <b>Example usage</b>
2523 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);
2524 AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);
2526 @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.
2528 #define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1
2532 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,
2533 "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
2536 @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)
2537 @param EAX Lower 32-bits of MSR value.
2538 @param EDX Upper 32-bits of MSR value.
2540 <b>Example usage</b>
2544 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);
2545 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);
2547 @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.
2549 #define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2
2553 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,
2554 "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
2557 @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)
2558 @param EAX Lower 32-bits of MSR value.
2559 @param EDX Upper 32-bits of MSR value.
2561 <b>Example usage</b>
2565 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);
2566 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);
2568 @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.
2570 #define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3
2574 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section
2575 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
2578 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)
2579 @param EAX Lower 32-bits of MSR value.
2580 @param EDX Upper 32-bits of MSR value.
2582 <b>Example usage</b>
2586 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);
2587 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);
2589 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
2591 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC
2595 6. Shared. GBUSQ Event Control and Counter Register (R/W).
2597 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)
2598 @param EAX Lower 32-bits of MSR value.
2599 @param EDX Upper 32-bits of MSR value.
2601 <b>Example usage</b>
2605 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);
2606 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);
2608 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
2610 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD
2614 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
2615 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
2618 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
2619 @param EAX Lower 32-bits of MSR value.
2620 @param EDX Upper 32-bits of MSR value.
2622 <b>Example usage</b>
2626 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);
2627 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);
2629 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
2631 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE
2635 6. Shared. GSNPQ Event Control and Counter Register (R/W).
2637 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)
2638 @param EAX Lower 32-bits of MSR value.
2639 @param EDX Upper 32-bits of MSR value.
2641 <b>Example usage</b>
2645 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);
2646 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);
2648 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
2650 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF
2654 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,
2655 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte
2658 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)
2659 @param EAX Lower 32-bits of MSR value.
2660 @param EDX Upper 32-bits of MSR value.
2662 <b>Example usage</b>
2666 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);
2667 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);
2669 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
2671 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0
2675 6. Shared. FSB Event Control and Counter Register (R/W).
2677 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)
2678 @param EAX Lower 32-bits of MSR value.
2679 @param EDX Upper 32-bits of MSR value.
2681 <b>Example usage</b>
2685 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);
2686 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);
2688 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
2690 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1
2694 6. Shared. FSB Event Control and Counter Register (R/W).
2696 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)
2697 @param EAX Lower 32-bits of MSR value.
2698 @param EDX Upper 32-bits of MSR value.
2700 <b>Example usage</b>
2704 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);
2705 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);
2707 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
2709 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2
2713 6. Shared. FSB Event Control and Counter Register (R/W).
2715 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)
2716 @param EAX Lower 32-bits of MSR value.
2717 @param EDX Upper 32-bits of MSR value.
2719 <b>Example usage</b>
2723 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);
2724 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);
2726 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
2728 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3