2 MSR Definitions for Pentium M Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __PENTIUM_M_MSR_H__
25 #define __PENTIUM_M_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Pentium M Processors?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x0D \
46 See Section 2.22, "MSRs in Pentium Processors.".
48 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
49 @param EAX Lower 32-bits of MSR value.
50 @param EDX Upper 32-bits of MSR value.
56 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
57 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
59 @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
61 #define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
65 See Section 2.22, "MSRs in Pentium Processors.".
67 @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
68 @param EAX Lower 32-bits of MSR value.
69 @param EDX Upper 32-bits of MSR value.
75 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
76 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
78 @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
80 #define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
84 Processor Hard Power-On Configuration (R/W) Enables and disables processor
85 features. (R) Indicates current processor configuration.
87 @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
88 @param EAX Lower 32-bits of MSR value.
89 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
90 @param EDX Upper 32-bits of MSR value.
91 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
95 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
97 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
98 AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
100 @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
102 #define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
105 MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
109 /// Individual bit fields
114 /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
115 /// Pentium M processor.
117 UINT32 DataErrorCheckingEnable
:1;
119 /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
120 /// the Pentium M processor.
122 UINT32 ResponseErrorCheckingEnable
:1;
124 /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
127 UINT32 MCERR_DriveEnable
:1;
129 /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
132 UINT32 AddressParityEnable
:1;
135 /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
136 /// the Pentium M processor.
138 UINT32 BINIT_DriverEnable
:1;
140 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
142 UINT32 OutputTriStateEnable
:1;
144 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
146 UINT32 ExecuteBIST
:1;
148 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
149 /// Always 0 on the Pentium M processor.
151 UINT32 MCERR_ObservationEnabled
:1;
154 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
155 /// Always 0 on the Pentium M processor.
157 UINT32 BINIT_ObservationEnabled
:1;
160 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
161 /// Always 0 on the Pentium M processor.
163 UINT32 ResetVector
:1;
166 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
169 UINT32 APICClusterID
:2;
171 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
172 /// 0 on the Pentium M processor.
174 UINT32 SystemBusFrequency
:1;
177 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
180 UINT32 SymmetricArbitrationID
:2;
182 /// [Bits 26:22] Clock Frequency Ratio (R/O).
184 UINT32 ClockFrequencyRatio
:5;
189 /// All bit fields as a 32-bit value
193 /// All bit fields as a 64-bit value
196 } MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
;
200 Last Branch Record n (R/W) One of 8 last branch record registers on the last
201 branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
202 the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
203 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
206 @param ECX MSR_PENTIUM_M_LASTBRANCH_n
207 @param EAX Lower 32-bits of MSR value.
208 @param EDX Upper 32-bits of MSR value.
214 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
215 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
217 @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
218 MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
219 MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
220 MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
221 MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
222 MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
223 MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
224 MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
227 #define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
228 #define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
229 #define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
230 #define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
231 #define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
232 #define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
233 #define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
234 #define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
241 @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
242 @param EAX Lower 32-bits of MSR value.
243 @param EDX Upper 32-bits of MSR value.
249 Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
250 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
252 @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
254 #define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
260 @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
261 @param EAX Lower 32-bits of MSR value.
262 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
263 @param EDX Upper 32-bits of MSR value.
264 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
268 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
270 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
271 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
273 @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
275 #define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
278 MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
282 /// Individual bit fields
286 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
287 /// Indicates if the L2 is hardware-disabled.
289 UINT32 L2HardwareEnabled
:1;
292 /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
293 /// cache data bus. ECC is always generated on write cycles. 1. = Disabled
294 /// (default) 2. = Enabled For the Pentium M processor, ECC checking on
295 /// the cache data bus is always enabled.
297 UINT32 ECCCheckEnable
:1;
300 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
301 /// Disabled (default) Until this bit is set the processor will not
302 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
307 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
309 UINT32 L2NotPresent
:1;
314 /// All bit fields as a 32-bit value
318 /// All bit fields as a 64-bit value
321 } MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
;
327 @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
328 @param EAX Lower 32-bits of MSR value.
329 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
330 @param EDX Upper 32-bits of MSR value.
331 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
335 MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
337 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
338 AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
340 @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
342 #define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
345 MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
349 /// Individual bit fields
354 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
355 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
356 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
357 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
358 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
365 /// All bit fields as a 32-bit value
369 /// All bit fields as a 64-bit value
372 } MSR_PENTIUM_M_THERM2_CTL_REGISTER
;
376 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
377 functions to be enabled and disabled.
379 @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
380 @param EAX Lower 32-bits of MSR value.
381 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
382 @param EDX Upper 32-bits of MSR value.
383 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
387 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
389 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
390 AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
392 @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
394 #define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
397 MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
401 /// Individual bit fields
406 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
407 /// this bit enables the thermal control circuit (TCC) portion of the
408 /// Intel Thermal Monitor feature. This allows processor clocks to be
409 /// automatically modulated based on the processor's thermal sensor
410 /// operation. 0 = Disabled (default). The automatic thermal control
411 /// circuit enable bit determines if the thermal control circuit (TCC)
412 /// will be activated when the processor's internal thermal sensor
413 /// determines the processor is about to exceed its maximum operating
414 /// temperature. When the TCC is activated and TM1 is enabled, the
415 /// processors clocks will be forced to a 50% duty cycle. BIOS must enable
416 /// this feature. The bit should not be confused with the on-demand
417 /// thermal control circuit enable bit.
419 UINT32 AutomaticThermalControlCircuit
:1;
422 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
423 /// monitoring enabled 0 = Performance monitoring disabled.
425 UINT32 PerformanceMonitoring
:1;
428 /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
429 /// processor to indicate a pending break event within the processor 0 =
430 /// Indicates compatible FERR# signaling behavior This bit must be set to
431 /// 1 to support XAPIC interrupt model usage.
432 /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
433 /// support branch trace storage (BTS) 0 = BTS is supported
437 /// [Bit 11] Branch Trace Storage Unavailable (RO)
438 /// 1 = Processor doesn't support branch trace storage (BTS)
439 /// 0 = BTS is supported
443 /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
444 /// Processor does not support processor event based sampling (PEBS); 0 =
445 /// PEBS is supported. The Pentium M processor does not support PEBS.
450 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
451 /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
452 /// processor, this bit may be configured to be read-only.
457 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
458 /// disabled. xTPR messages are optional messages that allow the processor
459 /// to inform the chipset of its priority. The default is processor
462 UINT32 xTPR_Message_Disable
:1;
467 /// All bit fields as a 32-bit value
471 /// All bit fields as a 64-bit value
474 } MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER
;
478 Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
479 to the MSR containing the most recent branch record. See also: -
480 MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,
481 and Exception Recording (Pentium M Processors)".
483 @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
484 @param EAX Lower 32-bits of MSR value.
485 @param EDX Upper 32-bits of MSR value.
491 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
492 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
494 @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
496 #define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
500 Debug Control (R/W) Controls how several debug features are used. Bit
501 definitions are discussed in the referenced section. See Section 17.15,
502 "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
504 @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
505 @param EAX Lower 32-bits of MSR value.
506 @param EDX Upper 32-bits of MSR value.
512 Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
513 AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
515 @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
517 #define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
521 Last Exception Record To Linear IP (R) This area contains a pointer to the
522 target of the last branch instruction that the processor executed prior to
523 the last exception that was generated or the last interrupt that was
524 handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording
525 (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception
528 @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
529 @param EAX Lower 32-bits of MSR value.
530 @param EDX Upper 32-bits of MSR value.
536 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
538 @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
540 #define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
544 Last Exception Record From Linear IP (R) Contains a pointer to the last
545 branch instruction that the processor executed prior to the last exception
546 that was generated or the last interrupt that was handled. See Section
547 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
548 Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".
550 @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
551 @param EAX Lower 32-bits of MSR value.
552 @param EDX Upper 32-bits of MSR value.
558 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
560 @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
562 #define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
566 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
568 @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
569 @param EAX Lower 32-bits of MSR value.
570 @param EDX Upper 32-bits of MSR value.
576 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
577 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
579 @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
581 #define MSR_PENTIUM_M_MC4_CTL 0x0000040C
585 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
587 @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
588 @param EAX Lower 32-bits of MSR value.
589 @param EDX Upper 32-bits of MSR value.
595 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
596 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
598 @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
600 #define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
604 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
605 either not implemented or contains no address if the ADDRV flag in the
606 MSR_MC4_STATUS register is clear. When not implemented in the processor, all
607 reads and writes to this MSR will cause a general-protection exception.
609 @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
610 @param EAX Lower 32-bits of MSR value.
611 @param EDX Upper 32-bits of MSR value.
617 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
618 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
620 @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
622 #define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
626 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
628 @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
629 @param EAX Lower 32-bits of MSR value.
630 @param EDX Upper 32-bits of MSR value.
636 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
637 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
639 @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
641 #define MSR_PENTIUM_M_MC3_CTL 0x00000410
645 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
647 @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
648 @param EAX Lower 32-bits of MSR value.
649 @param EDX Upper 32-bits of MSR value.
655 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
656 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
658 @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
660 #define MSR_PENTIUM_M_MC3_STATUS 0x00000411
664 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
665 either not implemented or contains no address if the ADDRV flag in the
666 MSR_MC3_STATUS register is clear. When not implemented in the processor, all
667 reads and writes to this MSR will cause a general-protection exception.
669 @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
670 @param EAX Lower 32-bits of MSR value.
671 @param EDX Upper 32-bits of MSR value.
677 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
678 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
680 @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
682 #define MSR_PENTIUM_M_MC3_ADDR 0x00000412