2 MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8.
24 #ifndef __SANDY_BRIDGE_MSR_H__
25 #define __SANDY_BRIDGE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Thread. SMI Counter (R/O).
32 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
40 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
45 #define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034
48 MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
52 /// Individual bit fields
56 /// [Bits 31:0] SMI Count (R/O) Count SMIs.
62 /// All bit fields as a 32-bit value
66 /// All bit fields as a 64-bit value
69 } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER
;
73 Package. See http://biosbits.org.
75 @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
76 @param EAX Lower 32-bits of MSR value.
77 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
78 @param EDX Upper 32-bits of MSR value.
79 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
83 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
85 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
86 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
89 #define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE
92 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
96 /// Individual bit fields
101 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
102 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
105 UINT32 MaximumNonTurboRatio
:8;
108 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
109 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
110 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
111 /// Turbo mode is disabled.
115 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
116 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
117 /// and when set to 0, indicates TDP Limit for Turbo mode is not
124 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
125 /// minimum ratio (maximum efficiency) that the processor can operates, in
128 UINT32 MaximumEfficiencyRatio
:8;
132 /// All bit fields as a 64-bit value
135 } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER
;
139 Core. C-State Configuration Control (R/W) Note: C-state values are
140 processor specific C-state code names, unrelated to MWAIT extension C-state
141 parameters or ACPI CStates. See http://biosbits.org.
143 @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
144 @param EAX Lower 32-bits of MSR value.
145 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
146 @param EDX Upper 32-bits of MSR value.
147 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
151 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
153 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
154 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
157 #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
160 MSR information returned for MSR index
161 #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL
165 /// Individual bit fields
169 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
170 /// processor-specific C-state code name (consuming the least power). for
171 /// the package. The default is set as factory-configured package C-state
172 /// limit. The following C-state code name encodings are supported: 000b:
173 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
174 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
175 /// This field cannot be used to limit package C-state to C3.
180 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
181 /// IO_read instructions sent to IO register specified by
182 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
187 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
188 /// until next reset.
193 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
194 /// will conditionally demote C6/C7 requests to C3 based on uncore
195 /// auto-demote information.
197 UINT32 C3AutoDemotion
:1;
199 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
200 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
201 /// auto-demote information.
203 UINT32 C1AutoDemotion
:1;
205 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
208 UINT32 C3Undemotion
:1;
210 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
213 UINT32 C1Undemotion
:1;
218 /// All bit fields as a 32-bit value
222 /// All bit fields as a 64-bit value
225 } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
;
229 Core. Power Management IO Redirection in C-state (R/W) See
232 @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)
233 @param EAX Lower 32-bits of MSR value.
234 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
235 @param EDX Upper 32-bits of MSR value.
236 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
240 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;
242 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
243 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
246 #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4
249 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE
253 /// Individual bit fields
257 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
258 /// visible to software for IO redirection. If IO MWAIT Redirection is
259 /// enabled, reads to this address will be consumed by the power
260 /// management logic and decoded to MWAIT instructions. When IO port
261 /// address redirection is enabled, this is the IO port address reported
262 /// to the OS/software.
266 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
267 /// maximum C-State code name to be included when IO read to MWAIT
268 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
269 /// is the max C-State to include 001b - C6 is the max C-State to include
270 /// 010b - C7 is the max C-State to include.
272 UINT32 CStateRange
:3;
277 /// All bit fields as a 32-bit value
281 /// All bit fields as a 64-bit value
284 } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER
;
288 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
289 handler to handle unsuccessful read of this MSR.
291 @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)
292 @param EAX Lower 32-bits of MSR value.
293 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
294 @param EDX Upper 32-bits of MSR value.
295 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
299 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;
301 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
302 AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
305 #define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C
308 MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG
312 /// Individual bit fields
316 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
317 /// MSR, the configuration of AES instruction set availability is as
318 /// follows: 11b: AES instructions are not available until next RESET.
319 /// otherwise, AES instructions are available. Note, AES instruction set
320 /// is not available if read is unsuccessful. If the configuration is not
321 /// 01b, AES instruction can be mis-configured if a privileged agent
322 /// unintentionally writes 11b.
324 UINT32 AESConfiguration
:2;
329 /// All bit fields as a 32-bit value
333 /// All bit fields as a 64-bit value
336 } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER
;
340 Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8.
342 @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
343 @param EAX Lower 32-bits of MSR value.
344 @param EDX Upper 32-bits of MSR value.
350 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
351 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
355 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A
356 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B
357 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C
358 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D
365 @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)
366 @param EAX Lower 32-bits of MSR value.
367 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
368 @param EDX Upper 32-bits of MSR value.
369 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
373 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;
375 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
376 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
379 #define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198
382 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS
386 /// Individual bit fields
391 /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed
392 /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
394 UINT32 CoreVoltage
:16;
398 /// All bit fields as a 64-bit value
401 } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
;
405 Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was
406 originally named IA32_THERM_CONTROL MSR.
408 @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
409 @param EAX Lower 32-bits of MSR value.
410 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
411 @param EDX Upper 32-bits of MSR value.
412 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
416 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;
418 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
419 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
422 #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A
425 MSR information returned for MSR index
426 #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION
430 /// Individual bit fields
434 /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%
437 UINT32 OnDemandClockModulationDutyCycle
:4;
439 /// [Bit 4] On demand Clock Modulation Enable (R/W).
441 UINT32 OnDemandClockModulationEnable
:1;
446 /// All bit fields as a 32-bit value
450 /// All bit fields as a 64-bit value
453 } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
;
457 Enable Misc. Processor Features (R/W) Allows a variety of processor
458 functions to be enabled and disabled.
460 @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)
461 @param EAX Lower 32-bits of MSR value.
462 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
463 @param EDX Upper 32-bits of MSR value.
464 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
468 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;
470 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
471 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
474 #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0
477 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE
481 /// Individual bit fields
485 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
487 UINT32 FastStrings
:1;
490 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
492 UINT32 PerformanceMonitoring
:1;
495 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
499 /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See
505 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
511 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
516 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
518 UINT32 LimitCpuidMaxval
:1;
520 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
522 UINT32 xTPR_Message_Disable
:1;
526 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
531 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
532 /// that support Intel Turbo Boost Technology, the turbo mode feature is
533 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
534 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
535 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
536 /// the power-on default value is used by BIOS to detect hardware support
537 /// of turbo mode. If power-on default value is 1, turbo mode is available
538 /// in the processor. If power-on default value is 0, turbo mode is not
541 UINT32 TurboModeDisable
:1;
545 /// All bit fields as a 64-bit value
548 } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER
;
554 @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
555 @param EAX Lower 32-bits of MSR value.
556 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
557 @param EDX Upper 32-bits of MSR value.
558 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
562 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
564 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
565 AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
568 #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
571 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET
575 /// Individual bit fields
580 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
581 /// PROCHOT# will be asserted. The value is degree C.
583 UINT32 TemperatureTarget
:8;
588 /// All bit fields as a 32-bit value
592 /// All bit fields as a 64-bit value
595 } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER
;
599 Miscellaneous Feature Control (R/W).
601 @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)
602 @param EAX Lower 32-bits of MSR value.
603 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
604 @param EDX Upper 32-bits of MSR value.
605 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
609 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;
611 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
612 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
615 #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4
618 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL
622 /// Individual bit fields
626 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
627 /// L2 hardware prefetcher, which fetches additional lines of code or data
628 /// into the L2 cache.
630 UINT32 L2HardwarePrefetcherDisable
:1;
632 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
633 /// disables the adjacent cache line prefetcher, which fetches the cache
634 /// line that comprises a cache line pair (128 bytes).
636 UINT32 L2AdjacentCacheLinePrefetcherDisable
:1;
638 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
639 /// the L1 data cache prefetcher, which fetches the next cache line into
642 UINT32 DCUHardwarePrefetcherDisable
:1;
644 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
645 /// data cache IP prefetcher, which uses sequential load history (based on
646 /// instruction Pointer of previous loads) to determine whether to
647 /// prefetch additional lines.
649 UINT32 DCUIPPrefetcherDisable
:1;
654 /// All bit fields as a 32-bit value
658 /// All bit fields as a 64-bit value
661 } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
;
665 Thread. Offcore Response Event Select Register (R/W).
667 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)
668 @param EAX Lower 32-bits of MSR value.
669 @param EDX Upper 32-bits of MSR value.
675 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
676 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
679 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6
683 Thread. Offcore Response Event Select Register (R/W).
685 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)
686 @param EAX Lower 32-bits of MSR value.
687 @param EDX Upper 32-bits of MSR value.
693 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
694 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
697 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7
701 See http://biosbits.org.
703 @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)
704 @param EAX Lower 32-bits of MSR value.
705 @param EDX Upper 32-bits of MSR value.
711 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);
712 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);
715 #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA
719 Thread. Last Branch Record Filtering Select Register (R/W) See Section
720 17.6.2, "Filtering of Last Branch Records.".
722 @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
723 @param EAX Lower 32-bits of MSR value.
724 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
725 @param EDX Upper 32-bits of MSR value.
726 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
730 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;
732 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);
733 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);
736 #define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8
739 MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT
743 /// Individual bit fields
747 /// [Bit 0] CPL_EQ_0.
751 /// [Bit 1] CPL_NEQ_0.
759 /// [Bit 3] NEAR_REL_CALL.
761 UINT32 NEAR_REL_CALL
:1;
763 /// [Bit 4] NEAR_IND_CALL.
765 UINT32 NEAR_IND_CALL
:1;
767 /// [Bit 5] NEAR_RET.
771 /// [Bit 6] NEAR_IND_JMP.
773 UINT32 NEAR_IND_JMP
:1;
775 /// [Bit 7] NEAR_REL_JMP.
777 UINT32 NEAR_REL_JMP
:1;
779 /// [Bit 8] FAR_BRANCH.
786 /// All bit fields as a 32-bit value
790 /// All bit fields as a 64-bit value
793 } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER
;
797 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
798 that points to the MSR containing the most recent branch record. See
799 MSR_LASTBRANCH_0_FROM_IP (at 680H).
801 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)
802 @param EAX Lower 32-bits of MSR value.
803 @param EDX Upper 32-bits of MSR value.
809 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);
810 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);
813 #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9
817 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
818 last branch instruction that the processor executed prior to the last
819 exception that was generated or the last interrupt that was handled.
821 @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)
822 @param EAX Lower 32-bits of MSR value.
823 @param EDX Upper 32-bits of MSR value.
829 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);
832 #define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD
836 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
837 to the target of the last branch instruction that the processor executed
838 prior to the last exception that was generated or the last interrupt that
841 @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)
842 @param EAX Lower 32-bits of MSR value.
843 @param EDX Upper 32-bits of MSR value.
849 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);
852 #define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE
856 Core. See http://biosbits.org.
858 @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)
859 @param EAX Lower 32-bits of MSR value.
860 @param EDX Upper 32-bits of MSR value.
866 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);
867 AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);
870 #define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC
874 Package. Always 0 (CMCI not supported).
876 @param ECX MSR_SANDY_BRIDGE_MC4_CTL2 (0x00000284)
877 @param EAX Lower 32-bits of MSR value.
878 @param EDX Upper 32-bits of MSR value.
884 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2);
885 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2, Msr);
888 #define MSR_SANDY_BRIDGE_MC4_CTL2 0x00000284
892 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
894 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS (0x0000038E)
895 @param EAX Lower 32-bits of MSR value.
896 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.
897 @param EDX Upper 32-bits of MSR value.
898 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.
902 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
904 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS);
905 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
908 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS 0x0000038E
911 MSR information returned for MSR index
912 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS
916 /// Individual bit fields
920 /// [Bit 0] Thread. Ovf_PMC0.
924 /// [Bit 1] Thread. Ovf_PMC1.
928 /// [Bit 2] Thread. Ovf_PMC2.
932 /// [Bit 3] Thread. Ovf_PMC3.
936 /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
940 /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
944 /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
948 /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
953 /// [Bit 32] Thread. Ovf_FixedCtr0.
955 UINT32 Ovf_FixedCtr0
:1;
957 /// [Bit 33] Thread. Ovf_FixedCtr1.
959 UINT32 Ovf_FixedCtr1
:1;
961 /// [Bit 34] Thread. Ovf_FixedCtr2.
963 UINT32 Ovf_FixedCtr2
:1;
966 /// [Bit 61] Thread. Ovf_Uncore.
970 /// [Bit 62] Thread. Ovf_BufDSSAVE.
972 UINT32 Ovf_BufDSSAVE
:1;
974 /// [Bit 63] Thread. CondChgd.
979 /// All bit fields as a 64-bit value
982 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER
;
986 Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
989 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
990 @param EAX Lower 32-bits of MSR value.
991 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
992 @param EDX Upper 32-bits of MSR value.
993 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
997 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
999 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);
1000 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
1003 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F
1006 MSR information returned for MSR index
1007 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL
1011 /// Individual bit fields
1015 /// [Bit 0] Thread. Set 1 to enable PMC0 to count.
1019 /// [Bit 1] Thread. Set 1 to enable PMC1 to count.
1023 /// [Bit 2] Thread. Set 1 to enable PMC2 to count.
1027 /// [Bit 3] Thread. Set 1 to enable PMC3 to count.
1031 /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >
1036 /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >
1041 /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >
1046 /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >
1050 UINT32 Reserved1
:24;
1052 /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.
1054 UINT32 FIXED_CTR0
:1;
1056 /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.
1058 UINT32 FIXED_CTR1
:1;
1060 /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.
1062 UINT32 FIXED_CTR2
:1;
1063 UINT32 Reserved2
:29;
1066 /// All bit fields as a 64-bit value
1069 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
;
1073 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
1075 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
1076 @param EAX Lower 32-bits of MSR value.
1077 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1078 @param EDX Upper 32-bits of MSR value.
1079 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1081 <b>Example usage</b>
1083 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1085 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);
1086 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1089 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
1092 MSR information returned for MSR index
1093 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL
1097 /// Individual bit fields
1101 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
1105 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
1109 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
1113 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
1117 /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
1121 /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
1125 /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
1129 /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
1132 UINT32 Reserved1
:24;
1134 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
1136 UINT32 Ovf_FixedCtr0
:1;
1138 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
1140 UINT32 Ovf_FixedCtr1
:1;
1142 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
1144 UINT32 Ovf_FixedCtr2
:1;
1145 UINT32 Reserved2
:26;
1147 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
1149 UINT32 Ovf_Uncore
:1;
1151 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
1153 UINT32 Ovf_BufDSSAVE
:1;
1155 /// [Bit 63] Thread. Set 1 to clear CondChgd.
1160 /// All bit fields as a 64-bit value
1163 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1167 Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
1169 @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
1170 @param EAX Lower 32-bits of MSR value.
1171 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1172 @param EDX Upper 32-bits of MSR value.
1173 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1175 <b>Example usage</b>
1177 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
1179 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);
1180 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1183 #define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1
1186 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE
1190 /// Individual bit fields
1194 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1196 UINT32 PEBS_EN_PMC0
:1;
1198 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1200 UINT32 PEBS_EN_PMC1
:1;
1202 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1204 UINT32 PEBS_EN_PMC2
:1;
1206 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1208 UINT32 PEBS_EN_PMC3
:1;
1209 UINT32 Reserved1
:28;
1211 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1213 UINT32 LL_EN_PMC0
:1;
1215 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1217 UINT32 LL_EN_PMC1
:1;
1219 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1221 UINT32 LL_EN_PMC2
:1;
1223 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1225 UINT32 LL_EN_PMC3
:1;
1226 UINT32 Reserved2
:27;
1228 /// [Bit 63] Enable Precise Store. (R/W).
1233 /// All bit fields as a 64-bit value
1236 } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
;
1240 Thread. see See Section 18.7.1.2, "Load Latency Performance Monitoring
1243 @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
1244 @param EAX Lower 32-bits of MSR value.
1245 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1246 @param EDX Upper 32-bits of MSR value.
1247 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1249 <b>Example usage</b>
1251 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;
1253 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);
1254 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);
1257 #define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6
1260 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT
1264 /// Individual bit fields
1268 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1269 /// that will be counted. (R/W).
1271 UINT32 MinimumThreshold
:16;
1272 UINT32 Reserved1
:16;
1273 UINT32 Reserved2
:32;
1276 /// All bit fields as a 32-bit value
1280 /// All bit fields as a 64-bit value
1283 } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
;
1287 Package. Note: C-state values are processor specific C-state code names,
1288 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1289 Residency Counter. (R/O) Value since last reset that this package is in
1290 processor-specific C3 states. Count at the same frequency as the TSC.
1292 @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)
1293 @param EAX Lower 32-bits of MSR value.
1294 @param EDX Upper 32-bits of MSR value.
1296 <b>Example usage</b>
1300 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);
1301 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);
1304 #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8
1308 Package. Note: C-state values are processor specific C-state code names,
1309 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1310 Residency Counter. (R/O) Value since last reset that this package is in
1311 processor-specific C6 states. Count at the same frequency as the TSC.
1313 @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)
1314 @param EAX Lower 32-bits of MSR value.
1315 @param EDX Upper 32-bits of MSR value.
1317 <b>Example usage</b>
1321 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);
1322 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);
1325 #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9
1329 Package. Note: C-state values are processor specific C-state code names,
1330 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1331 Residency Counter. (R/O) Value since last reset that this package is in
1332 processor-specific C7 states. Count at the same frequency as the TSC.
1334 @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)
1335 @param EAX Lower 32-bits of MSR value.
1336 @param EDX Upper 32-bits of MSR value.
1338 <b>Example usage</b>
1342 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);
1343 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);
1346 #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA
1350 Core. Note: C-state values are processor specific C-state code names,
1351 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1352 Residency Counter. (R/O) Value since last reset that this core is in
1353 processor-specific C3 states. Count at the same frequency as the TSC.
1355 @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)
1356 @param EAX Lower 32-bits of MSR value.
1357 @param EDX Upper 32-bits of MSR value.
1359 <b>Example usage</b>
1363 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);
1364 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);
1367 #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC
1371 Core. Note: C-state values are processor specific C-state code names,
1372 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1373 Residency Counter. (R/O) Value since last reset that this core is in
1374 processor-specific C6 states. Count at the same frequency as the TSC.
1376 @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)
1377 @param EAX Lower 32-bits of MSR value.
1378 @param EDX Upper 32-bits of MSR value.
1380 <b>Example usage</b>
1384 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);
1385 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);
1388 #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD
1392 Core. Note: C-state values are processor specific C-state code names,
1393 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7
1394 Residency Counter. (R/O) Value since last reset that this core is in
1395 processor-specific C7 states. Count at the same frequency as the TSC.
1397 @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)
1398 @param EAX Lower 32-bits of MSR value.
1399 @param EDX Upper 32-bits of MSR value.
1401 <b>Example usage</b>
1405 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);
1406 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);
1409 #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE
1413 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1415 @param ECX MSR_SANDY_BRIDGE_MC4_CTL (0x00000410)
1416 @param EAX Lower 32-bits of MSR value.
1417 Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.
1418 @param EDX Upper 32-bits of MSR value.
1419 Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.
1421 <b>Example usage</b>
1423 MSR_SANDY_BRIDGE_MC4_CTL_REGISTER Msr;
1425 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL);
1426 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL, Msr.Uint64);
1429 #define MSR_SANDY_BRIDGE_MC4_CTL 0x00000410
1432 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MC4_CTL
1436 /// Individual bit fields
1440 /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU
1441 /// hardware detected errors.
1443 UINT32 PCUHardwareError
:1;
1445 /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU
1446 /// controller detected errors.
1448 UINT32 PCUControllerError
:1;
1450 /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU
1451 /// firmware detected errors.
1453 UINT32 PCUFirmwareError
:1;
1454 UINT32 Reserved1
:29;
1455 UINT32 Reserved2
:32;
1458 /// All bit fields as a 32-bit value
1462 /// All bit fields as a 64-bit value
1465 } MSR_SANDY_BRIDGE_MC4_CTL_REGISTER
;
1469 Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
1471 @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1472 @param EAX Lower 32-bits of MSR value.
1473 @param EDX Upper 32-bits of MSR value.
1475 <b>Example usage</b>
1479 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);
1482 #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1486 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1489 @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)
1490 @param EAX Lower 32-bits of MSR value.
1491 @param EDX Upper 32-bits of MSR value.
1493 <b>Example usage</b>
1497 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);
1500 #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606
1504 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are
1505 processor specific C-state code names, unrelated to MWAIT extension C-state
1506 parameters or ACPI CStates.
1508 @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)
1509 @param EAX Lower 32-bits of MSR value.
1510 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1511 @param EDX Upper 32-bits of MSR value.
1512 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1514 <b>Example usage</b>
1516 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;
1518 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);
1519 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);
1522 #define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A
1525 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL
1529 /// Individual bit fields
1533 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1534 /// that should be used to decide if the package should be put into a
1535 /// package C3 state.
1537 UINT32 TimeLimit
:10;
1539 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1540 /// unit of the interrupt response time limit. The following time unit
1541 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1542 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1547 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1548 /// valid and can be used by the processor for package C-sate management.
1551 UINT32 Reserved2
:16;
1552 UINT32 Reserved3
:32;
1555 /// All bit fields as a 32-bit value
1559 /// All bit fields as a 64-bit value
1562 } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER
;
1566 Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the
1567 budget allocated for the package to exit from C6 to a C0 state, where
1568 interrupt request can be delivered to the core and serviced. Additional
1569 core-exit latency amy be applicable depending on the actual C-state the core
1570 is in. Note: C-state values are processor specific C-state code names,
1571 unrelated to MWAIT extension C-state parameters or ACPI CStates.
1573 @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)
1574 @param EAX Lower 32-bits of MSR value.
1575 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1576 @param EDX Upper 32-bits of MSR value.
1577 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1579 <b>Example usage</b>
1581 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;
1583 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);
1584 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);
1587 #define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B
1590 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL
1594 /// Individual bit fields
1598 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1599 /// that should be used to decide if the package should be put into a
1600 /// package C6 state.
1602 UINT32 TimeLimit
:10;
1604 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1605 /// unit of the interrupt response time limit. The following time unit
1606 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1607 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1612 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1613 /// valid and can be used by the processor for package C-sate management.
1616 UINT32 Reserved2
:16;
1617 UINT32 Reserved3
:32;
1620 /// All bit fields as a 32-bit value
1624 /// All bit fields as a 64-bit value
1627 } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER
;
1631 Package. Note: C-state values are processor specific C-state code names,
1632 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
1633 Residency Counter. (R/O) Value since last reset that this package is in
1634 processor-specific C2 states. Count at the same frequency as the TSC.
1636 @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)
1637 @param EAX Lower 32-bits of MSR value.
1638 @param EDX Upper 32-bits of MSR value.
1640 <b>Example usage</b>
1644 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);
1645 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);
1648 #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D
1652 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1655 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)
1656 @param EAX Lower 32-bits of MSR value.
1657 @param EDX Upper 32-bits of MSR value.
1659 <b>Example usage</b>
1663 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);
1664 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);
1667 #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610
1671 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1673 @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)
1674 @param EAX Lower 32-bits of MSR value.
1675 @param EDX Upper 32-bits of MSR value.
1677 <b>Example usage</b>
1681 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);
1684 #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611
1688 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1691 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)
1692 @param EAX Lower 32-bits of MSR value.
1693 @param EDX Upper 32-bits of MSR value.
1695 <b>Example usage</b>
1699 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);
1700 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);
1703 #define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614
1707 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1710 @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)
1711 @param EAX Lower 32-bits of MSR value.
1712 @param EDX Upper 32-bits of MSR value.
1714 <b>Example usage</b>
1718 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);
1719 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);
1722 #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638
1726 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1729 @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
1730 @param EAX Lower 32-bits of MSR value.
1731 @param EDX Upper 32-bits of MSR value.
1733 <b>Example usage</b>
1737 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);
1740 #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
1744 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1745 branch record registers on the last branch record stack. This part of the
1746 stack contains pointers to the source instruction. See also: - Last Branch
1747 Record Stack TOS at 1C9H - Section 17.6.1, "LBR Stack.".
1749 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP
1750 @param EAX Lower 32-bits of MSR value.
1751 @param EDX Upper 32-bits of MSR value.
1753 <b>Example usage</b>
1757 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);
1758 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);
1762 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680
1763 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681
1764 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682
1765 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683
1766 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684
1767 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685
1768 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686
1769 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687
1770 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688
1771 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689
1772 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A
1773 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B
1774 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C
1775 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D
1776 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E
1777 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F
1782 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1783 record registers on the last branch record stack. This part of the stack
1784 contains pointers to the destination instruction.
1786 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP
1787 @param EAX Lower 32-bits of MSR value.
1788 @param EDX Upper 32-bits of MSR value.
1790 <b>Example usage</b>
1794 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);
1795 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);
1799 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0
1800 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1
1801 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2
1802 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3
1803 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4
1804 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5
1805 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6
1806 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7
1807 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8
1808 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9
1809 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA
1810 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB
1811 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC
1812 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD
1813 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE
1814 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF
1819 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1820 RW if MSR_PLATFORM_INFO.[28] = 1.
1822 @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)
1823 @param EAX Lower 32-bits of MSR value.
1824 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1825 @param EDX Upper 32-bits of MSR value.
1826 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1828 <b>Example usage</b>
1830 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;
1832 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);
1835 #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD
1838 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT
1842 /// Individual bit fields
1846 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1847 /// limit of 1 core active.
1851 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1852 /// limit of 2 core active.
1856 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1857 /// limit of 3 core active.
1861 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1862 /// limit of 4 core active.
1866 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
1867 /// limit of 5 core active.
1871 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
1872 /// limit of 6 core active.
1876 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
1877 /// limit of 7 core active.
1881 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
1882 /// limit of 8 core active.
1887 /// All bit fields as a 64-bit value
1890 } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER
;
1894 Package. Uncore PMU global control.
1896 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)
1897 @param EAX Lower 32-bits of MSR value.
1898 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1899 @param EDX Upper 32-bits of MSR value.
1900 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1902 <b>Example usage</b>
1904 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
1906 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);
1907 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
1910 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391
1913 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL
1917 /// Individual bit fields
1921 /// [Bit 0] Core 0 select.
1923 UINT32 PMI_Sel_Core0
:1;
1925 /// [Bit 1] Core 1 select.
1927 UINT32 PMI_Sel_Core1
:1;
1929 /// [Bit 2] Core 2 select.
1931 UINT32 PMI_Sel_Core2
:1;
1933 /// [Bit 3] Core 3 select.
1935 UINT32 PMI_Sel_Core3
:1;
1936 UINT32 Reserved1
:15;
1937 UINT32 Reserved2
:10;
1939 /// [Bit 29] Enable all uncore counters.
1943 /// [Bit 30] Enable wake on PMI.
1947 /// [Bit 31] Enable Freezing counter when overflow.
1950 UINT32 Reserved3
:32;
1953 /// All bit fields as a 32-bit value
1957 /// All bit fields as a 64-bit value
1960 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER
;
1964 Package. Uncore PMU main status.
1966 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)
1967 @param EAX Lower 32-bits of MSR value.
1968 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
1969 @param EDX Upper 32-bits of MSR value.
1970 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
1972 <b>Example usage</b>
1974 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
1976 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);
1977 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
1980 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392
1983 MSR information returned for MSR index
1984 #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS
1988 /// Individual bit fields
1992 /// [Bit 0] Fixed counter overflowed.
1996 /// [Bit 1] An ARB counter overflowed.
2001 /// [Bit 3] A CBox counter overflowed (on any slice).
2004 UINT32 Reserved2
:28;
2005 UINT32 Reserved3
:32;
2008 /// All bit fields as a 32-bit value
2012 /// All bit fields as a 64-bit value
2015 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER
;
2019 Package. Uncore fixed counter control (R/W).
2021 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)
2022 @param EAX Lower 32-bits of MSR value.
2023 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2024 @param EDX Upper 32-bits of MSR value.
2025 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2027 <b>Example usage</b>
2029 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
2031 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);
2032 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
2035 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394
2038 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL
2042 /// Individual bit fields
2045 UINT32 Reserved1
:20;
2047 /// [Bit 20] Enable overflow propagation.
2049 UINT32 EnableOverflow
:1;
2052 /// [Bit 22] Enable counting.
2054 UINT32 EnableCounting
:1;
2056 UINT32 Reserved4
:32;
2059 /// All bit fields as a 32-bit value
2063 /// All bit fields as a 64-bit value
2066 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER
;
2070 Package. Uncore fixed counter.
2072 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)
2073 @param EAX Lower 32-bits of MSR value.
2074 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2075 @param EDX Upper 32-bits of MSR value.
2076 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2078 <b>Example usage</b>
2080 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;
2082 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);
2083 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);
2086 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395
2089 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR
2093 /// Individual bit fields
2097 /// [Bits 31:0] Current count.
2099 UINT32 CurrentCount
:32;
2101 /// [Bits 47:32] Current count.
2103 UINT32 CurrentCountHi
:16;
2107 /// All bit fields as a 64-bit value
2110 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER
;
2114 Package. Uncore C-Box configuration information (R/O).
2116 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)
2117 @param EAX Lower 32-bits of MSR value.
2118 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2119 @param EDX Upper 32-bits of MSR value.
2120 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2122 <b>Example usage</b>
2124 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;
2126 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);
2129 #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396
2132 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG
2136 /// Individual bit fields
2140 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
2143 UINT32 Reserved1
:28;
2144 UINT32 Reserved2
:32;
2147 /// All bit fields as a 32-bit value
2151 /// All bit fields as a 64-bit value
2154 } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER
;
2158 Package. Uncore Arb unit, performance counter 0.
2160 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)
2161 @param EAX Lower 32-bits of MSR value.
2162 @param EDX Upper 32-bits of MSR value.
2164 <b>Example usage</b>
2168 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);
2169 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);
2172 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0
2176 Package. Uncore Arb unit, performance counter 1.
2178 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)
2179 @param EAX Lower 32-bits of MSR value.
2180 @param EDX Upper 32-bits of MSR value.
2182 <b>Example usage</b>
2186 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);
2187 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);
2190 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1
2194 Package. Uncore Arb unit, counter 0 event select MSR.
2196 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
2197 @param EAX Lower 32-bits of MSR value.
2198 @param EDX Upper 32-bits of MSR value.
2200 <b>Example usage</b>
2204 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);
2205 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);
2208 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2
2212 Package. Uncore Arb unit, counter 1 event select MSR.
2214 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
2215 @param EAX Lower 32-bits of MSR value.
2216 @param EDX Upper 32-bits of MSR value.
2218 <b>Example usage</b>
2222 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);
2223 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);
2226 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3
2230 Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the
2231 budget allocated for the package to exit from C7 to a C0 state, where
2232 interrupt request can be delivered to the core and serviced. Additional
2233 core-exit latency amy be applicable depending on the actual C-state the core
2234 is in. Note: C-state values are processor specific C-state code names,
2235 unrelated to MWAIT extension C-state parameters or ACPI CStates.
2237 @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)
2238 @param EAX Lower 32-bits of MSR value.
2239 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2240 @param EDX Upper 32-bits of MSR value.
2241 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2243 <b>Example usage</b>
2245 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;
2247 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);
2248 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);
2251 #define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C
2254 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL
2258 /// Individual bit fields
2262 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
2263 /// that should be used to decide if the package should be put into a
2264 /// package C7 state.
2266 UINT32 TimeLimit
:10;
2268 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
2269 /// unit of the interrupt response time limit. The following time unit
2270 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
2271 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
2276 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
2277 /// valid and can be used by the processor for package C-sate management.
2280 UINT32 Reserved2
:16;
2281 UINT32 Reserved3
:32;
2284 /// All bit fields as a 32-bit value
2288 /// All bit fields as a 64-bit value
2291 } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
;
2295 Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2298 @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)
2299 @param EAX Lower 32-bits of MSR value.
2300 @param EDX Upper 32-bits of MSR value.
2302 <b>Example usage</b>
2306 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);
2307 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);
2310 #define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A
2314 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
2317 @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)
2318 @param EAX Lower 32-bits of MSR value.
2319 @param EDX Upper 32-bits of MSR value.
2321 <b>Example usage</b>
2325 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);
2326 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);
2329 #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640
2333 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
2336 @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)
2337 @param EAX Lower 32-bits of MSR value.
2338 @param EDX Upper 32-bits of MSR value.
2340 <b>Example usage</b>
2344 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);
2347 #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641
2351 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2354 @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)
2355 @param EAX Lower 32-bits of MSR value.
2356 @param EDX Upper 32-bits of MSR value.
2358 <b>Example usage</b>
2362 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);
2363 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);
2366 #define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642
2370 Package. Uncore C-Box 0, counter 0 event select MSR.
2372 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
2373 @param EAX Lower 32-bits of MSR value.
2374 @param EDX Upper 32-bits of MSR value.
2376 <b>Example usage</b>
2380 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);
2381 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
2384 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700
2388 Package. Uncore C-Box 0, counter 1 event select MSR.
2390 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
2391 @param EAX Lower 32-bits of MSR value.
2392 @param EDX Upper 32-bits of MSR value.
2394 <b>Example usage</b>
2398 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1);
2399 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1, Msr);
2402 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701
2406 Package. Uncore C-Box 0, performance counter 0.
2408 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 (0x00000706)
2409 @param EAX Lower 32-bits of MSR value.
2410 @param EDX Upper 32-bits of MSR value.
2412 <b>Example usage</b>
2416 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);
2417 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
2420 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706
2424 Package. Uncore C-Box 0, performance counter 1.
2426 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 (0x00000707)
2427 @param EAX Lower 32-bits of MSR value.
2428 @param EDX Upper 32-bits of MSR value.
2430 <b>Example usage</b>
2434 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1);
2435 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1, Msr);
2438 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707
2442 Package. Uncore C-Box 1, counter 0 event select MSR.
2444 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
2445 @param EAX Lower 32-bits of MSR value.
2446 @param EDX Upper 32-bits of MSR value.
2448 <b>Example usage</b>
2452 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);
2453 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
2456 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710
2460 Package. Uncore C-Box 1, counter 1 event select MSR.
2462 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
2463 @param EAX Lower 32-bits of MSR value.
2464 @param EDX Upper 32-bits of MSR value.
2466 <b>Example usage</b>
2470 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1);
2471 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1, Msr);
2474 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711
2478 Package. Uncore C-Box 1, performance counter 0.
2480 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 (0x00000716)
2481 @param EAX Lower 32-bits of MSR value.
2482 @param EDX Upper 32-bits of MSR value.
2484 <b>Example usage</b>
2488 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);
2489 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
2492 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716
2496 Package. Uncore C-Box 1, performance counter 1.
2498 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 (0x00000717)
2499 @param EAX Lower 32-bits of MSR value.
2500 @param EDX Upper 32-bits of MSR value.
2502 <b>Example usage</b>
2506 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1);
2507 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1, Msr);
2510 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717
2514 Package. Uncore C-Box 2, counter 0 event select MSR.
2516 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
2517 @param EAX Lower 32-bits of MSR value.
2518 @param EDX Upper 32-bits of MSR value.
2520 <b>Example usage</b>
2524 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);
2525 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
2528 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720
2532 Package. Uncore C-Box 2, counter 1 event select MSR.
2534 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
2535 @param EAX Lower 32-bits of MSR value.
2536 @param EDX Upper 32-bits of MSR value.
2538 <b>Example usage</b>
2542 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1);
2543 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1, Msr);
2546 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2550 Package. Uncore C-Box 2, performance counter 0.
2552 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 (0x00000726)
2553 @param EAX Lower 32-bits of MSR value.
2554 @param EDX Upper 32-bits of MSR value.
2556 <b>Example usage</b>
2560 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);
2561 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
2564 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726
2568 Package. Uncore C-Box 2, performance counter 1.
2570 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 (0x00000727)
2571 @param EAX Lower 32-bits of MSR value.
2572 @param EDX Upper 32-bits of MSR value.
2574 <b>Example usage</b>
2578 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1);
2579 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1, Msr);
2582 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727
2586 Package. Uncore C-Box 3, counter 0 event select MSR.
2588 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
2589 @param EAX Lower 32-bits of MSR value.
2590 @param EDX Upper 32-bits of MSR value.
2592 <b>Example usage</b>
2596 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);
2597 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
2600 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2604 Package. Uncore C-Box 3, counter 1 event select MSR.
2606 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
2607 @param EAX Lower 32-bits of MSR value.
2608 @param EDX Upper 32-bits of MSR value.
2610 <b>Example usage</b>
2614 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1);
2615 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1, Msr);
2618 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2622 Package. Uncore C-Box 3, performance counter 0.
2624 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 (0x00000736)
2625 @param EAX Lower 32-bits of MSR value.
2626 @param EDX Upper 32-bits of MSR value.
2628 <b>Example usage</b>
2632 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
2633 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
2636 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736
2640 Package. Uncore C-Box 3, performance counter 1.
2642 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 (0x00000737)
2643 @param EAX Lower 32-bits of MSR value.
2644 @param EDX Upper 32-bits of MSR value.
2646 <b>Example usage</b>
2650 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1);
2651 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1, Msr);
2654 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737
2658 Package. MC Bank Error Configuration (R/W).
2660 @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)
2661 @param EAX Lower 32-bits of MSR value.
2662 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2663 @param EDX Upper 32-bits of MSR value.
2664 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2666 <b>Example usage</b>
2668 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
2670 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);
2671 AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
2674 #define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F
2677 MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL
2681 /// Individual bit fields
2686 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
2687 /// to log additional info in bits 36:32.
2689 UINT32 MemErrorLogEnable
:1;
2690 UINT32 Reserved2
:30;
2691 UINT32 Reserved3
:32;
2694 /// All bit fields as a 32-bit value
2698 /// All bit fields as a 64-bit value
2701 } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
;
2707 @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)
2708 @param EAX Lower 32-bits of MSR value.
2709 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2710 @param EDX Upper 32-bits of MSR value.
2711 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2713 <b>Example usage</b>
2715 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;
2717 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);
2718 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);
2721 #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C
2724 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT
2728 /// Individual bit fields
2732 /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
2733 /// counting logic for specific events requiring additional configuration,
2736 UINT32 ENABLE_PEBS_NUM_ALT
:1;
2737 UINT32 Reserved1
:31;
2738 UINT32 Reserved2
:32;
2741 /// All bit fields as a 32-bit value
2745 /// All bit fields as a 64-bit value
2748 } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
;
2752 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
2754 @param ECX MSR_SANDY_BRIDGE_MCi_CTL
2755 @param EAX Lower 32-bits of MSR value.
2756 @param EDX Upper 32-bits of MSR value.
2758 <b>Example usage</b>
2762 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_CTL);
2763 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_CTL, Msr);
2767 #define MSR_SANDY_BRIDGE_MC5_CTL 0x00000414
2768 #define MSR_SANDY_BRIDGE_MC6_CTL 0x00000418
2769 #define MSR_SANDY_BRIDGE_MC7_CTL 0x0000041C
2770 #define MSR_SANDY_BRIDGE_MC8_CTL 0x00000420
2771 #define MSR_SANDY_BRIDGE_MC9_CTL 0x00000424
2772 #define MSR_SANDY_BRIDGE_MC10_CTL 0x00000428
2773 #define MSR_SANDY_BRIDGE_MC11_CTL 0x0000042C
2774 #define MSR_SANDY_BRIDGE_MC12_CTL 0x00000430
2775 #define MSR_SANDY_BRIDGE_MC13_CTL 0x00000434
2776 #define MSR_SANDY_BRIDGE_MC14_CTL 0x00000438
2777 #define MSR_SANDY_BRIDGE_MC15_CTL 0x0000043C
2778 #define MSR_SANDY_BRIDGE_MC16_CTL 0x00000440
2779 #define MSR_SANDY_BRIDGE_MC17_CTL 0x00000444
2780 #define MSR_SANDY_BRIDGE_MC18_CTL 0x00000448
2781 #define MSR_SANDY_BRIDGE_MC19_CTL 0x0000044C
2786 Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.
2788 @param ECX MSR_SANDY_BRIDGE_MCi_STATUS
2789 @param EAX Lower 32-bits of MSR value.
2790 @param EDX Upper 32-bits of MSR value.
2792 <b>Example usage</b>
2796 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS);
2797 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS, Msr);
2801 #define MSR_SANDY_BRIDGE_MC5_STATUS 0x00000415
2802 #define MSR_SANDY_BRIDGE_MC6_STATUS 0x00000419
2803 #define MSR_SANDY_BRIDGE_MC7_STATUS 0x0000041D
2804 #define MSR_SANDY_BRIDGE_MC8_STATUS 0x00000421
2805 #define MSR_SANDY_BRIDGE_MC9_STATUS 0x00000425
2806 #define MSR_SANDY_BRIDGE_MC10_STATUS 0x00000429
2807 #define MSR_SANDY_BRIDGE_MC11_STATUS 0x0000042D
2808 #define MSR_SANDY_BRIDGE_MC12_STATUS 0x00000431
2809 #define MSR_SANDY_BRIDGE_MC13_STATUS 0x00000435
2810 #define MSR_SANDY_BRIDGE_MC14_STATUS 0x00000439
2811 #define MSR_SANDY_BRIDGE_MC15_STATUS 0x0000043D
2812 #define MSR_SANDY_BRIDGE_MC16_STATUS 0x00000441
2813 #define MSR_SANDY_BRIDGE_MC17_STATUS 0x00000445
2814 #define MSR_SANDY_BRIDGE_MC18_STATUS 0x00000449
2815 #define MSR_SANDY_BRIDGE_MC19_STATUS 0x0000044D
2820 Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
2822 @param ECX MSR_SANDY_BRIDGE_MCi_ADDR
2823 @param EAX Lower 32-bits of MSR value.
2824 @param EDX Upper 32-bits of MSR value.
2826 <b>Example usage</b>
2830 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR);
2831 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR, Msr);
2835 #define MSR_SANDY_BRIDGE_MC5_ADDR 0x00000416
2836 #define MSR_SANDY_BRIDGE_MC6_ADDR 0x0000041A
2837 #define MSR_SANDY_BRIDGE_MC7_ADDR 0x0000041E
2838 #define MSR_SANDY_BRIDGE_MC8_ADDR 0x00000422
2839 #define MSR_SANDY_BRIDGE_MC9_ADDR 0x00000426
2840 #define MSR_SANDY_BRIDGE_MC10_ADDR 0x0000042A
2841 #define MSR_SANDY_BRIDGE_MC11_ADDR 0x0000042E
2842 #define MSR_SANDY_BRIDGE_MC12_ADDR 0x00000432
2843 #define MSR_SANDY_BRIDGE_MC13_ADDR 0x00000436
2844 #define MSR_SANDY_BRIDGE_MC14_ADDR 0x0000043A
2845 #define MSR_SANDY_BRIDGE_MC15_ADDR 0x0000043E
2846 #define MSR_SANDY_BRIDGE_MC16_ADDR 0x00000442
2847 #define MSR_SANDY_BRIDGE_MC17_ADDR 0x00000446
2848 #define MSR_SANDY_BRIDGE_MC18_ADDR 0x0000044A
2849 #define MSR_SANDY_BRIDGE_MC19_ADDR 0x0000044E
2854 Package. See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".
2856 @param ECX MSR_SANDY_BRIDGE_MCi_MISC
2857 @param EAX Lower 32-bits of MSR value.
2858 @param EDX Upper 32-bits of MSR value.
2860 <b>Example usage</b>
2864 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_MISC);
2865 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_MISC, Msr);
2869 #define MSR_SANDY_BRIDGE_MC5_MISC 0x00000417
2870 #define MSR_SANDY_BRIDGE_MC6_MISC 0x0000041B
2871 #define MSR_SANDY_BRIDGE_MC7_MISC 0x0000041F
2872 #define MSR_SANDY_BRIDGE_MC8_MISC 0x00000423
2873 #define MSR_SANDY_BRIDGE_MC9_MISC 0x00000427
2874 #define MSR_SANDY_BRIDGE_MC10_MISC 0x0000042B
2875 #define MSR_SANDY_BRIDGE_MC11_MISC 0x0000042F
2876 #define MSR_SANDY_BRIDGE_MC12_MISC 0x00000433
2877 #define MSR_SANDY_BRIDGE_MC13_MISC 0x00000437
2878 #define MSR_SANDY_BRIDGE_MC14_MISC 0x0000043B
2879 #define MSR_SANDY_BRIDGE_MC15_MISC 0x0000043F
2880 #define MSR_SANDY_BRIDGE_MC16_MISC 0x00000443
2881 #define MSR_SANDY_BRIDGE_MC17_MISC 0x00000447
2882 #define MSR_SANDY_BRIDGE_MC18_MISC 0x0000044B
2883 #define MSR_SANDY_BRIDGE_MC19_MISC 0x0000044F
2888 Package. Package RAPL Perf Status (R/O).
2890 @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)
2891 @param EAX Lower 32-bits of MSR value.
2892 @param EDX Upper 32-bits of MSR value.
2894 <b>Example usage</b>
2898 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);
2901 #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613
2905 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
2908 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
2909 @param EAX Lower 32-bits of MSR value.
2910 @param EDX Upper 32-bits of MSR value.
2912 <b>Example usage</b>
2916 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);
2917 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);
2920 #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
2924 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
2926 @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
2927 @param EAX Lower 32-bits of MSR value.
2928 @param EDX Upper 32-bits of MSR value.
2930 <b>Example usage</b>
2934 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);
2937 #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
2941 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
2944 @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
2945 @param EAX Lower 32-bits of MSR value.
2946 @param EDX Upper 32-bits of MSR value.
2948 <b>Example usage</b>
2952 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);
2955 #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
2959 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
2961 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
2962 @param EAX Lower 32-bits of MSR value.
2963 @param EDX Upper 32-bits of MSR value.
2965 <b>Example usage</b>
2969 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);
2970 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);
2973 #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C
2977 Package. Uncore U-box UCLK fixed counter control.
2979 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)
2980 @param EAX Lower 32-bits of MSR value.
2981 @param EDX Upper 32-bits of MSR value.
2983 <b>Example usage</b>
2987 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);
2988 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);
2991 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08
2995 Package. Uncore U-box UCLK fixed counter.
2997 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)
2998 @param EAX Lower 32-bits of MSR value.
2999 @param EDX Upper 32-bits of MSR value.
3001 <b>Example usage</b>
3005 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);
3006 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);
3009 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09
3013 Package. Uncore U-box perfmon event select for U-box counter 0.
3015 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)
3016 @param EAX Lower 32-bits of MSR value.
3017 @param EDX Upper 32-bits of MSR value.
3019 <b>Example usage</b>
3023 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);
3024 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);
3027 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10
3031 Package. Uncore U-box perfmon event select for U-box counter 1.
3033 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)
3034 @param EAX Lower 32-bits of MSR value.
3035 @param EDX Upper 32-bits of MSR value.
3037 <b>Example usage</b>
3041 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);
3042 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);
3045 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11
3049 Package. Uncore U-box perfmon counter 0.
3051 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)
3052 @param EAX Lower 32-bits of MSR value.
3053 @param EDX Upper 32-bits of MSR value.
3055 <b>Example usage</b>
3059 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);
3060 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);
3063 #define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16
3067 Package. Uncore U-box perfmon counter 1.
3069 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)
3070 @param EAX Lower 32-bits of MSR value.
3071 @param EDX Upper 32-bits of MSR value.
3073 <b>Example usage</b>
3077 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);
3078 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);
3081 #define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17
3085 Package. Uncore PCU perfmon for PCU-box-wide control.
3087 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)
3088 @param EAX Lower 32-bits of MSR value.
3089 @param EDX Upper 32-bits of MSR value.
3091 <b>Example usage</b>
3095 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);
3096 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);
3099 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24
3103 Package. Uncore PCU perfmon event select for PCU counter 0.
3105 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)
3106 @param EAX Lower 32-bits of MSR value.
3107 @param EDX Upper 32-bits of MSR value.
3109 <b>Example usage</b>
3113 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);
3114 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);
3117 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30
3121 Package. Uncore PCU perfmon event select for PCU counter 1.
3123 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)
3124 @param EAX Lower 32-bits of MSR value.
3125 @param EDX Upper 32-bits of MSR value.
3127 <b>Example usage</b>
3131 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);
3132 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);
3135 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31
3139 Package. Uncore PCU perfmon event select for PCU counter 2.
3141 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)
3142 @param EAX Lower 32-bits of MSR value.
3143 @param EDX Upper 32-bits of MSR value.
3145 <b>Example usage</b>
3149 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);
3150 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);
3153 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32
3157 Package. Uncore PCU perfmon event select for PCU counter 3.
3159 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)
3160 @param EAX Lower 32-bits of MSR value.
3161 @param EDX Upper 32-bits of MSR value.
3163 <b>Example usage</b>
3167 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);
3168 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);
3171 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33
3175 Package. Uncore PCU perfmon box-wide filter.
3177 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)
3178 @param EAX Lower 32-bits of MSR value.
3179 @param EDX Upper 32-bits of MSR value.
3181 <b>Example usage</b>
3185 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);
3186 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);
3189 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34
3193 Package. Uncore PCU perfmon counter 0.
3195 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)
3196 @param EAX Lower 32-bits of MSR value.
3197 @param EDX Upper 32-bits of MSR value.
3199 <b>Example usage</b>
3203 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);
3204 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);
3207 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36
3211 Package. Uncore PCU perfmon counter 1.
3213 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)
3214 @param EAX Lower 32-bits of MSR value.
3215 @param EDX Upper 32-bits of MSR value.
3217 <b>Example usage</b>
3221 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);
3222 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);
3225 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37
3229 Package. Uncore PCU perfmon counter 2.
3231 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)
3232 @param EAX Lower 32-bits of MSR value.
3233 @param EDX Upper 32-bits of MSR value.
3235 <b>Example usage</b>
3239 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);
3240 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);
3243 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38
3247 Package. Uncore PCU perfmon counter 3.
3249 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)
3250 @param EAX Lower 32-bits of MSR value.
3251 @param EDX Upper 32-bits of MSR value.
3253 <b>Example usage</b>
3257 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);
3258 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);
3261 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39
3265 Package. Uncore C-box 0 perfmon local box wide control.
3267 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)
3268 @param EAX Lower 32-bits of MSR value.
3269 @param EDX Upper 32-bits of MSR value.
3271 <b>Example usage</b>
3275 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);
3276 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);
3279 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04
3283 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
3285 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)
3286 @param EAX Lower 32-bits of MSR value.
3287 @param EDX Upper 32-bits of MSR value.
3289 <b>Example usage</b>
3293 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);
3294 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);
3297 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10
3301 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
3303 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)
3304 @param EAX Lower 32-bits of MSR value.
3305 @param EDX Upper 32-bits of MSR value.
3307 <b>Example usage</b>
3311 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);
3312 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);
3315 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11
3319 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
3321 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)
3322 @param EAX Lower 32-bits of MSR value.
3323 @param EDX Upper 32-bits of MSR value.
3325 <b>Example usage</b>
3329 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);
3330 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);
3333 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12
3337 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
3339 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)
3340 @param EAX Lower 32-bits of MSR value.
3341 @param EDX Upper 32-bits of MSR value.
3343 <b>Example usage</b>
3347 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);
3348 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);
3351 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13
3355 Package. Uncore C-box 0 perfmon box wide filter.
3357 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)
3358 @param EAX Lower 32-bits of MSR value.
3359 @param EDX Upper 32-bits of MSR value.
3361 <b>Example usage</b>
3365 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);
3366 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);
3369 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14
3373 Package. Uncore C-box 0 perfmon counter 0.
3375 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)
3376 @param EAX Lower 32-bits of MSR value.
3377 @param EDX Upper 32-bits of MSR value.
3379 <b>Example usage</b>
3383 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);
3384 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);
3387 #define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16
3391 Package. Uncore C-box 0 perfmon counter 1.
3393 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)
3394 @param EAX Lower 32-bits of MSR value.
3395 @param EDX Upper 32-bits of MSR value.
3397 <b>Example usage</b>
3401 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);
3402 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);
3405 #define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17
3409 Package. Uncore C-box 0 perfmon counter 2.
3411 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)
3412 @param EAX Lower 32-bits of MSR value.
3413 @param EDX Upper 32-bits of MSR value.
3415 <b>Example usage</b>
3419 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);
3420 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);
3423 #define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18
3427 Package. Uncore C-box 0 perfmon counter 3.
3429 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)
3430 @param EAX Lower 32-bits of MSR value.
3431 @param EDX Upper 32-bits of MSR value.
3433 <b>Example usage</b>
3437 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);
3438 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);
3441 #define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19
3445 Package. Uncore C-box 1 perfmon local box wide control.
3447 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)
3448 @param EAX Lower 32-bits of MSR value.
3449 @param EDX Upper 32-bits of MSR value.
3451 <b>Example usage</b>
3455 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);
3456 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);
3459 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24
3463 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
3465 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)
3466 @param EAX Lower 32-bits of MSR value.
3467 @param EDX Upper 32-bits of MSR value.
3469 <b>Example usage</b>
3473 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);
3474 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);
3477 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30
3481 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
3483 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)
3484 @param EAX Lower 32-bits of MSR value.
3485 @param EDX Upper 32-bits of MSR value.
3487 <b>Example usage</b>
3491 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);
3492 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);
3495 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31
3499 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
3501 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)
3502 @param EAX Lower 32-bits of MSR value.
3503 @param EDX Upper 32-bits of MSR value.
3505 <b>Example usage</b>
3509 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);
3510 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);
3513 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32
3517 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
3519 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)
3520 @param EAX Lower 32-bits of MSR value.
3521 @param EDX Upper 32-bits of MSR value.
3523 <b>Example usage</b>
3527 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);
3528 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);
3531 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33
3535 Package. Uncore C-box 1 perfmon box wide filter.
3537 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)
3538 @param EAX Lower 32-bits of MSR value.
3539 @param EDX Upper 32-bits of MSR value.
3541 <b>Example usage</b>
3545 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);
3546 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);
3549 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34
3553 Package. Uncore C-box 1 perfmon counter 0.
3555 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)
3556 @param EAX Lower 32-bits of MSR value.
3557 @param EDX Upper 32-bits of MSR value.
3559 <b>Example usage</b>
3563 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);
3564 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);
3567 #define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36
3571 Package. Uncore C-box 1 perfmon counter 1.
3573 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)
3574 @param EAX Lower 32-bits of MSR value.
3575 @param EDX Upper 32-bits of MSR value.
3577 <b>Example usage</b>
3581 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);
3582 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);
3585 #define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37
3589 Package. Uncore C-box 1 perfmon counter 2.
3591 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)
3592 @param EAX Lower 32-bits of MSR value.
3593 @param EDX Upper 32-bits of MSR value.
3595 <b>Example usage</b>
3599 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);
3600 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);
3603 #define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38
3607 Package. Uncore C-box 1 perfmon counter 3.
3609 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)
3610 @param EAX Lower 32-bits of MSR value.
3611 @param EDX Upper 32-bits of MSR value.
3613 <b>Example usage</b>
3617 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);
3618 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);
3621 #define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39
3625 Package. Uncore C-box 2 perfmon local box wide control.
3627 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)
3628 @param EAX Lower 32-bits of MSR value.
3629 @param EDX Upper 32-bits of MSR value.
3631 <b>Example usage</b>
3635 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);
3636 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);
3639 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44
3643 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
3645 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)
3646 @param EAX Lower 32-bits of MSR value.
3647 @param EDX Upper 32-bits of MSR value.
3649 <b>Example usage</b>
3653 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);
3654 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);
3657 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50
3661 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
3663 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)
3664 @param EAX Lower 32-bits of MSR value.
3665 @param EDX Upper 32-bits of MSR value.
3667 <b>Example usage</b>
3671 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);
3672 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);
3675 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51
3679 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
3681 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)
3682 @param EAX Lower 32-bits of MSR value.
3683 @param EDX Upper 32-bits of MSR value.
3685 <b>Example usage</b>
3689 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);
3690 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);
3693 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52
3697 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
3699 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)
3700 @param EAX Lower 32-bits of MSR value.
3701 @param EDX Upper 32-bits of MSR value.
3703 <b>Example usage</b>
3707 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);
3708 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);
3711 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53
3715 Package. Uncore C-box 2 perfmon box wide filter.
3717 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)
3718 @param EAX Lower 32-bits of MSR value.
3719 @param EDX Upper 32-bits of MSR value.
3721 <b>Example usage</b>
3725 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);
3726 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);
3729 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54
3733 Package. Uncore C-box 2 perfmon counter 0.
3735 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)
3736 @param EAX Lower 32-bits of MSR value.
3737 @param EDX Upper 32-bits of MSR value.
3739 <b>Example usage</b>
3743 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);
3744 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);
3747 #define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56
3751 Package. Uncore C-box 2 perfmon counter 1.
3753 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)
3754 @param EAX Lower 32-bits of MSR value.
3755 @param EDX Upper 32-bits of MSR value.
3757 <b>Example usage</b>
3761 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);
3762 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);
3765 #define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57
3769 Package. Uncore C-box 2 perfmon counter 2.
3771 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)
3772 @param EAX Lower 32-bits of MSR value.
3773 @param EDX Upper 32-bits of MSR value.
3775 <b>Example usage</b>
3779 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);
3780 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);
3783 #define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58
3787 Package. Uncore C-box 2 perfmon counter 3.
3789 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)
3790 @param EAX Lower 32-bits of MSR value.
3791 @param EDX Upper 32-bits of MSR value.
3793 <b>Example usage</b>
3797 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);
3798 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);
3801 #define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59
3805 Package. Uncore C-box 3 perfmon local box wide control.
3807 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)
3808 @param EAX Lower 32-bits of MSR value.
3809 @param EDX Upper 32-bits of MSR value.
3811 <b>Example usage</b>
3815 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);
3816 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);
3819 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64
3823 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
3825 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)
3826 @param EAX Lower 32-bits of MSR value.
3827 @param EDX Upper 32-bits of MSR value.
3829 <b>Example usage</b>
3833 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);
3834 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);
3837 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70
3841 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
3843 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)
3844 @param EAX Lower 32-bits of MSR value.
3845 @param EDX Upper 32-bits of MSR value.
3847 <b>Example usage</b>
3851 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);
3852 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);
3855 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71
3859 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
3861 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)
3862 @param EAX Lower 32-bits of MSR value.
3863 @param EDX Upper 32-bits of MSR value.
3865 <b>Example usage</b>
3869 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);
3870 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);
3873 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72
3877 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
3879 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)
3880 @param EAX Lower 32-bits of MSR value.
3881 @param EDX Upper 32-bits of MSR value.
3883 <b>Example usage</b>
3887 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);
3888 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);
3891 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73
3895 Package. Uncore C-box 3 perfmon box wide filter.
3897 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)
3898 @param EAX Lower 32-bits of MSR value.
3899 @param EDX Upper 32-bits of MSR value.
3901 <b>Example usage</b>
3905 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);
3906 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);
3909 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74
3913 Package. Uncore C-box 3 perfmon counter 0.
3915 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)
3916 @param EAX Lower 32-bits of MSR value.
3917 @param EDX Upper 32-bits of MSR value.
3919 <b>Example usage</b>
3923 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);
3924 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);
3927 #define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76
3931 Package. Uncore C-box 3 perfmon counter 1.
3933 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)
3934 @param EAX Lower 32-bits of MSR value.
3935 @param EDX Upper 32-bits of MSR value.
3937 <b>Example usage</b>
3941 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);
3942 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);
3945 #define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77
3949 Package. Uncore C-box 3 perfmon counter 2.
3951 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)
3952 @param EAX Lower 32-bits of MSR value.
3953 @param EDX Upper 32-bits of MSR value.
3955 <b>Example usage</b>
3959 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);
3960 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);
3963 #define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78
3967 Package. Uncore C-box 3 perfmon counter 3.
3969 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)
3970 @param EAX Lower 32-bits of MSR value.
3971 @param EDX Upper 32-bits of MSR value.
3973 <b>Example usage</b>
3977 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);
3978 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);
3981 #define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79
3985 Package. Uncore C-box 4 perfmon local box wide control.
3987 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)
3988 @param EAX Lower 32-bits of MSR value.
3989 @param EDX Upper 32-bits of MSR value.
3991 <b>Example usage</b>
3995 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);
3996 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);
3999 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84
4003 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
4005 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)
4006 @param EAX Lower 32-bits of MSR value.
4007 @param EDX Upper 32-bits of MSR value.
4009 <b>Example usage</b>
4013 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);
4014 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);
4017 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90
4021 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
4023 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)
4024 @param EAX Lower 32-bits of MSR value.
4025 @param EDX Upper 32-bits of MSR value.
4027 <b>Example usage</b>
4031 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);
4032 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);
4035 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91
4039 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
4041 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)
4042 @param EAX Lower 32-bits of MSR value.
4043 @param EDX Upper 32-bits of MSR value.
4045 <b>Example usage</b>
4049 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);
4050 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);
4053 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92
4057 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
4059 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)
4060 @param EAX Lower 32-bits of MSR value.
4061 @param EDX Upper 32-bits of MSR value.
4063 <b>Example usage</b>
4067 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);
4068 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);
4071 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93
4075 Package. Uncore C-box 4 perfmon box wide filter.
4077 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)
4078 @param EAX Lower 32-bits of MSR value.
4079 @param EDX Upper 32-bits of MSR value.
4081 <b>Example usage</b>
4085 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);
4086 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);
4089 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94
4093 Package. Uncore C-box 4 perfmon counter 0.
4095 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)
4096 @param EAX Lower 32-bits of MSR value.
4097 @param EDX Upper 32-bits of MSR value.
4099 <b>Example usage</b>
4103 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);
4104 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);
4107 #define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96
4111 Package. Uncore C-box 4 perfmon counter 1.
4113 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)
4114 @param EAX Lower 32-bits of MSR value.
4115 @param EDX Upper 32-bits of MSR value.
4117 <b>Example usage</b>
4121 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);
4122 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);
4125 #define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97
4129 Package. Uncore C-box 4 perfmon counter 2.
4131 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)
4132 @param EAX Lower 32-bits of MSR value.
4133 @param EDX Upper 32-bits of MSR value.
4135 <b>Example usage</b>
4139 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);
4140 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);
4143 #define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98
4147 Package. Uncore C-box 4 perfmon counter 3.
4149 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)
4150 @param EAX Lower 32-bits of MSR value.
4151 @param EDX Upper 32-bits of MSR value.
4153 <b>Example usage</b>
4157 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);
4158 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);
4161 #define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99
4165 Package. Uncore C-box 5 perfmon local box wide control.
4167 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)
4168 @param EAX Lower 32-bits of MSR value.
4169 @param EDX Upper 32-bits of MSR value.
4171 <b>Example usage</b>
4175 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);
4176 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);
4179 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4
4183 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
4185 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)
4186 @param EAX Lower 32-bits of MSR value.
4187 @param EDX Upper 32-bits of MSR value.
4189 <b>Example usage</b>
4193 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);
4194 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);
4197 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0
4201 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
4203 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)
4204 @param EAX Lower 32-bits of MSR value.
4205 @param EDX Upper 32-bits of MSR value.
4207 <b>Example usage</b>
4211 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);
4212 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);
4215 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1
4219 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
4221 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)
4222 @param EAX Lower 32-bits of MSR value.
4223 @param EDX Upper 32-bits of MSR value.
4225 <b>Example usage</b>
4229 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);
4230 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);
4233 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2
4237 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
4239 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)
4240 @param EAX Lower 32-bits of MSR value.
4241 @param EDX Upper 32-bits of MSR value.
4243 <b>Example usage</b>
4247 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);
4248 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);
4251 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3
4255 Package. Uncore C-box 5 perfmon box wide filter.
4257 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)
4258 @param EAX Lower 32-bits of MSR value.
4259 @param EDX Upper 32-bits of MSR value.
4261 <b>Example usage</b>
4265 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);
4266 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);
4269 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4
4273 Package. Uncore C-box 5 perfmon counter 0.
4275 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)
4276 @param EAX Lower 32-bits of MSR value.
4277 @param EDX Upper 32-bits of MSR value.
4279 <b>Example usage</b>
4283 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);
4284 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);
4287 #define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6
4291 Package. Uncore C-box 5 perfmon counter 1.
4293 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)
4294 @param EAX Lower 32-bits of MSR value.
4295 @param EDX Upper 32-bits of MSR value.
4297 <b>Example usage</b>
4301 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);
4302 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);
4305 #define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7
4309 Package. Uncore C-box 5 perfmon counter 2.
4311 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)
4312 @param EAX Lower 32-bits of MSR value.
4313 @param EDX Upper 32-bits of MSR value.
4315 <b>Example usage</b>
4319 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);
4320 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);
4323 #define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8
4327 Package. Uncore C-box 5 perfmon counter 3.
4329 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)
4330 @param EAX Lower 32-bits of MSR value.
4331 @param EDX Upper 32-bits of MSR value.
4333 <b>Example usage</b>
4337 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);
4338 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);
4341 #define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9
4345 Package. Uncore C-box 6 perfmon local box wide control.
4347 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)
4348 @param EAX Lower 32-bits of MSR value.
4349 @param EDX Upper 32-bits of MSR value.
4351 <b>Example usage</b>
4355 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);
4356 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);
4359 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4
4363 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
4365 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)
4366 @param EAX Lower 32-bits of MSR value.
4367 @param EDX Upper 32-bits of MSR value.
4369 <b>Example usage</b>
4373 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);
4374 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);
4377 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0
4381 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
4383 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)
4384 @param EAX Lower 32-bits of MSR value.
4385 @param EDX Upper 32-bits of MSR value.
4387 <b>Example usage</b>
4391 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);
4392 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);
4395 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1
4399 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
4401 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)
4402 @param EAX Lower 32-bits of MSR value.
4403 @param EDX Upper 32-bits of MSR value.
4405 <b>Example usage</b>
4409 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);
4410 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);
4413 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2
4417 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
4419 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)
4420 @param EAX Lower 32-bits of MSR value.
4421 @param EDX Upper 32-bits of MSR value.
4423 <b>Example usage</b>
4427 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);
4428 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);
4431 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3
4435 Package. Uncore C-box 6 perfmon box wide filter.
4437 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)
4438 @param EAX Lower 32-bits of MSR value.
4439 @param EDX Upper 32-bits of MSR value.
4441 <b>Example usage</b>
4445 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);
4446 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);
4449 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4
4453 Package. Uncore C-box 6 perfmon counter 0.
4455 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)
4456 @param EAX Lower 32-bits of MSR value.
4457 @param EDX Upper 32-bits of MSR value.
4459 <b>Example usage</b>
4463 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);
4464 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);
4467 #define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6
4471 Package. Uncore C-box 6 perfmon counter 1.
4473 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)
4474 @param EAX Lower 32-bits of MSR value.
4475 @param EDX Upper 32-bits of MSR value.
4477 <b>Example usage</b>
4481 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);
4482 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);
4485 #define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7
4489 Package. Uncore C-box 6 perfmon counter 2.
4491 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)
4492 @param EAX Lower 32-bits of MSR value.
4493 @param EDX Upper 32-bits of MSR value.
4495 <b>Example usage</b>
4499 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);
4500 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);
4503 #define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8
4507 Package. Uncore C-box 6 perfmon counter 3.
4509 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)
4510 @param EAX Lower 32-bits of MSR value.
4511 @param EDX Upper 32-bits of MSR value.
4513 <b>Example usage</b>
4517 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);
4518 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);
4521 #define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9
4525 Package. Uncore C-box 7 perfmon local box wide control.
4527 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)
4528 @param EAX Lower 32-bits of MSR value.
4529 @param EDX Upper 32-bits of MSR value.
4531 <b>Example usage</b>
4535 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);
4536 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);
4539 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4
4543 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
4545 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)
4546 @param EAX Lower 32-bits of MSR value.
4547 @param EDX Upper 32-bits of MSR value.
4549 <b>Example usage</b>
4553 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);
4554 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);
4557 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0
4561 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
4563 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)
4564 @param EAX Lower 32-bits of MSR value.
4565 @param EDX Upper 32-bits of MSR value.
4567 <b>Example usage</b>
4571 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);
4572 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);
4575 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1
4579 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
4581 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)
4582 @param EAX Lower 32-bits of MSR value.
4583 @param EDX Upper 32-bits of MSR value.
4585 <b>Example usage</b>
4589 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);
4590 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);
4593 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2
4597 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
4599 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)
4600 @param EAX Lower 32-bits of MSR value.
4601 @param EDX Upper 32-bits of MSR value.
4603 <b>Example usage</b>
4607 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);
4608 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);
4611 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3
4615 Package. Uncore C-box 7 perfmon box wide filter.
4617 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)
4618 @param EAX Lower 32-bits of MSR value.
4619 @param EDX Upper 32-bits of MSR value.
4621 <b>Example usage</b>
4625 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);
4626 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);
4629 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4
4633 Package. Uncore C-box 7 perfmon counter 0.
4635 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)
4636 @param EAX Lower 32-bits of MSR value.
4637 @param EDX Upper 32-bits of MSR value.
4639 <b>Example usage</b>
4643 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);
4644 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);
4647 #define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6
4651 Package. Uncore C-box 7 perfmon counter 1.
4653 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)
4654 @param EAX Lower 32-bits of MSR value.
4655 @param EDX Upper 32-bits of MSR value.
4657 <b>Example usage</b>
4661 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);
4662 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);
4665 #define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7
4669 Package. Uncore C-box 7 perfmon counter 2.
4671 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)
4672 @param EAX Lower 32-bits of MSR value.
4673 @param EDX Upper 32-bits of MSR value.
4675 <b>Example usage</b>
4679 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);
4680 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);
4683 #define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8
4687 Package. Uncore C-box 7 perfmon counter 3.
4689 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)
4690 @param EAX Lower 32-bits of MSR value.
4691 @param EDX Upper 32-bits of MSR value.
4693 <b>Example usage</b>
4697 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);
4698 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);
4701 #define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9