2 MSR Definitions for Intel processors based on the Silvermont microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4.
24 #ifndef __SILVERMONT_MSR_H__
25 #define __SILVERMONT_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Shared. Model Specific Platform ID (R).
32 @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
40 MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
45 #define MSR_SILVERMONT_PLATFORM_ID 0x00000017
48 MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
52 /// Individual bit fields
57 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
59 UINT32 MaximumQualifiedRatio
:5;
63 /// [Bits 52:50] See Table 35-2.
69 /// All bit fields as a 64-bit value
72 } MSR_SILVERMONT_PLATFORM_ID_REGISTER
;
76 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
77 processor features; (R) indicates current processor configuration.
79 @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)
80 @param EAX Lower 32-bits of MSR value.
81 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
82 @param EDX Upper 32-bits of MSR value.
83 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
87 MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;
89 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
90 AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
93 #define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A
96 MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
100 /// Individual bit fields
105 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
108 UINT32 DataErrorCheckingEnable
:1;
110 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
113 UINT32 ResponseErrorCheckingEnable
:1;
115 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
117 UINT32 AERR_DriveEnable
:1;
119 /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
120 /// Disabled Always 0.
122 UINT32 BERR_Enable
:1;
126 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
128 UINT32 BINIT_DriverEnable
:1;
131 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
133 UINT32 ExecuteBIST
:1;
135 /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
138 UINT32 AERR_ObservationEnabled
:1;
141 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
144 UINT32 BINIT_ObservationEnabled
:1;
147 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
149 UINT32 ResetVector
:1;
152 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
154 UINT32 APICClusterID
:2;
157 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
159 UINT32 SymmetricArbitrationID
:2;
161 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
163 UINT32 IntegerBusFrequencyRatio
:5;
165 UINT32 Reserved10
:32;
168 /// All bit fields as a 32-bit value
172 /// All bit fields as a 64-bit value
175 } MSR_SILVERMONT_EBL_CR_POWERON_REGISTER
;
179 Core. SMI Counter (R/O).
181 @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034)
182 @param EAX Lower 32-bits of MSR value.
183 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
184 @param EDX Upper 32-bits of MSR value.
185 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
189 MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;
191 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
194 #define MSR_SILVERMONT_SMI_COUNT 0x00000034
197 MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT
201 /// Individual bit fields
205 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
212 /// All bit fields as a 32-bit value
216 /// All bit fields as a 64-bit value
219 } MSR_SILVERMONT_SMI_COUNT_REGISTER
;
223 Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch
224 record registers on the last branch record stack. This part of the stack
225 contains pointers to the source instruction for one of the last eight
226 branches, exceptions, or interrupts taken by the processor. See also: -
227 Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
228 Interrupt, and Exception Recording (Pentium M Processors).".
230 @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP
231 @param EAX Lower 32-bits of MSR value.
232 @param EDX Upper 32-bits of MSR value.
238 Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
239 AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
243 #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040
244 #define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041
245 #define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042
246 #define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043
247 #define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044
248 #define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045
249 #define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046
250 #define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047
255 Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch
256 record registers on the last branch record stack. This part of the stack
257 contains pointers to the destination instruction for one of the last eight
258 branches, exceptions, or interrupts taken by the processor.
260 @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP
261 @param EAX Lower 32-bits of MSR value.
262 @param EDX Upper 32-bits of MSR value.
268 Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
269 AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
273 #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060
274 #define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061
275 #define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062
276 #define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063
277 #define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064
278 #define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065
279 #define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066
280 #define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067
285 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
286 bus clock speed for processors based on Silvermont microarchitecture:.
288 @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)
289 @param EAX Lower 32-bits of MSR value.
290 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
291 @param EDX Upper 32-bits of MSR value.
292 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
296 MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;
298 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
301 #define MSR_SILVERMONT_FSB_FREQ 0x000000CD
304 MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ
308 /// Individual bit fields
312 /// [Bits 3:0] Scalable Bus Speed
314 /// Silvermont Processor Family
315 /// ---------------------------
322 /// Airmont Processor Family
323 /// ---------------------------
334 UINT32 ScalableBusSpeed
:4;
339 /// All bit fields as a 32-bit value
343 /// All bit fields as a 64-bit value
346 } MSR_SILVERMONT_FSB_FREQ_REGISTER
;
350 Shared. C-State Configuration Control (R/W) Note: C-state values are
351 processor specific C-state code names, unrelated to MWAIT extension C-state
352 parameters or ACPI CStates. See http://biosbits.org.
354 @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
355 @param EAX Lower 32-bits of MSR value.
356 Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
357 @param EDX Upper 32-bits of MSR value.
358 Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
362 MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
364 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
365 AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
368 #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2
371 MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL
375 /// Individual bit fields
379 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
380 /// processor-specific C-state code name (consuming the least power). for
381 /// the package. The default is set as factory-configured package C-state
382 /// limit. The following C-state code name encodings are supported: 000b:
383 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
384 /// 100b: C4 110b: C6 111b: C7 (Silvermont only).
389 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
390 /// IO_read instructions sent to IO register specified by
391 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
396 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
397 /// until next reset.
404 /// All bit fields as a 32-bit value
408 /// All bit fields as a 64-bit value
411 } MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER
;
415 Shared. Power Management IO Redirection in C-state (R/W) See
418 @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)
419 @param EAX Lower 32-bits of MSR value.
420 Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
421 @param EDX Upper 32-bits of MSR value.
422 Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
426 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;
428 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
429 AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
432 #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4
435 MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE
439 /// Individual bit fields
443 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
444 /// visible to software for IO redirection. If IO MWAIT Redirection is
445 /// enabled, reads to this address will be consumed by the power
446 /// management logic and decoded to MWAIT instructions. When IO port
447 /// address redirection is enabled, this is the IO port address reported
448 /// to the OS/software.
452 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
453 /// maximum C-State code name to be included when IO read to MWAIT
454 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
455 /// is the max C-State to include 110b - C6 is the max C-State to include
456 /// 111b - C7 is the max C-State to include.
458 UINT32 CStateRange
:3;
463 /// All bit fields as a 32-bit value
467 /// All bit fields as a 64-bit value
470 } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER
;
476 @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)
477 @param EAX Lower 32-bits of MSR value.
478 Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
479 @param EDX Upper 32-bits of MSR value.
480 Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
484 MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;
486 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
487 AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
490 #define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E
493 MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3
497 /// Individual bit fields
501 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
502 /// Indicates if the L2 is hardware-disabled.
504 UINT32 L2HardwareEnabled
:1;
507 /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
508 /// Disabled (default) Until this bit is set the processor will not
509 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
514 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
516 UINT32 L2NotPresent
:1;
521 /// All bit fields as a 32-bit value
525 /// All bit fields as a 64-bit value
528 } MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
;
532 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
533 handler to handle unsuccessful read of this MSR.
535 @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)
536 @param EAX Lower 32-bits of MSR value.
537 Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
538 @param EDX Upper 32-bits of MSR value.
539 Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
543 MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;
545 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
546 AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
549 #define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C
552 MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG
556 /// Individual bit fields
560 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
561 /// MSR, the configuration of AES instruction set availability is as
562 /// follows: 11b: AES instructions are not available until next RESET.
563 /// otherwise, AES instructions are available. Note, AES instruction set
564 /// is not available if read is unsuccessful. If the configuration is not
565 /// 01b, AES instruction can be mis-configured if a privileged agent
566 /// unintentionally writes 11b.
568 UINT32 AESConfiguration
:2;
573 /// All bit fields as a 32-bit value
577 /// All bit fields as a 64-bit value
580 } MSR_SILVERMONT_FEATURE_CONFIG_REGISTER
;
584 Enable Misc. Processor Features (R/W) Allows a variety of processor
585 functions to be enabled and disabled.
587 @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)
588 @param EAX Lower 32-bits of MSR value.
589 Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
590 @param EDX Upper 32-bits of MSR value.
591 Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
595 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;
597 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);
598 AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);
601 #define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0
604 MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE
608 /// Individual bit fields
612 /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.
614 UINT32 FastStrings
:1;
617 /// [Bit 3] Shared. Automatic Thermal Control Circuit Enable (R/W) See
620 UINT32 AutomaticThermalControlCircuit
:1;
623 /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.
625 UINT32 PerformanceMonitoring
:1;
628 /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.
632 /// [Bit 12] Core. Precise Event Based Sampling Unavailable (RO) See Table
638 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
644 /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.
649 /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.
651 UINT32 LimitCpuidMaxval
:1;
653 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
655 UINT32 xTPR_Message_Disable
:1;
659 /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.
664 /// [Bit 38] Shared. Turbo Mode Disable (R/W) When set to 1 on processors
665 /// that support Intel Turbo Boost Technology, the turbo mode feature is
666 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
667 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
668 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
669 /// the power-on default value is used by BIOS to detect hardware support
670 /// of turbo mode. If power-on default value is 1, turbo mode is available
671 /// in the processor. If power-on default value is 0, turbo mode is not
674 UINT32 TurboModeDisable
:1;
675 UINT32 Reserved10
:25;
678 /// All bit fields as a 64-bit value
681 } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER
;
687 @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)
688 @param EAX Lower 32-bits of MSR value.
689 Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
690 @param EDX Upper 32-bits of MSR value.
691 Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
695 MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;
697 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);
698 AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);
701 #define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2
704 MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET
708 /// Individual bit fields
713 /// [Bits 23:16] Temperature Target (R) The default thermal throttling or
714 /// PROCHOT# activation temperature in degree C, The effective temperature
715 /// for thermal throttling or PROCHOT# activation is "Temperature Target"
716 /// + "Target Offset".
718 UINT32 TemperatureTarget
:8;
720 /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to
721 /// adjust the throttling and PROCHOT# activation temperature from the
722 /// default target specified in TEMPERATURE_TARGET (bits 23:16).
724 UINT32 TargetOffset
:6;
729 /// All bit fields as a 32-bit value
733 /// All bit fields as a 64-bit value
736 } MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER
;
740 Shared. Offcore Response Event Select Register (R/W).
742 @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)
743 @param EAX Lower 32-bits of MSR value.
744 @param EDX Upper 32-bits of MSR value.
750 Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);
751 AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);
754 #define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6
758 Shared. Offcore Response Event Select Register (R/W).
760 @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)
761 @param EAX Lower 32-bits of MSR value.
762 @param EDX Upper 32-bits of MSR value.
768 Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);
769 AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);
772 #define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7
776 Package. Maximum Ratio Limit of Turbo Mode (RW).
778 @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)
779 @param EAX Lower 32-bits of MSR value.
780 Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
781 @param EDX Upper 32-bits of MSR value.
782 Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
786 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;
788 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);
789 AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
792 #define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD
795 MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT
799 /// Individual bit fields
803 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
804 /// limit of 1 core active.
808 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
809 /// limit of 2 core active.
813 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
814 /// limit of 3 core active.
818 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
819 /// limit of 4 core active.
823 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
824 /// limit of 5 core active.
828 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
829 /// limit of 6 core active.
833 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
834 /// limit of 7 core active.
838 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
839 /// limit of 8 core active.
844 /// All bit fields as a 64-bit value
847 } MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER
;
851 Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that
852 points to the MSR containing the most recent branch record. See
853 MSR_LASTBRANCH_0_FROM_IP (at 40H).
855 @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)
856 @param EAX Lower 32-bits of MSR value.
857 @param EDX Upper 32-bits of MSR value.
863 Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);
864 AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);
867 #define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9
871 Core. Last Exception Record From Linear IP (R) Contains a pointer to the
872 last branch instruction that the processor executed prior to the last
873 exception that was generated or the last interrupt that was handled.
875 @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)
876 @param EAX Lower 32-bits of MSR value.
877 @param EDX Upper 32-bits of MSR value.
883 Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);
886 #define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD
890 Core. Last Exception Record To Linear IP (R) This area contains a pointer
891 to the target of the last branch instruction that the processor executed
892 prior to the last exception that was generated or the last interrupt that
895 @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE)
896 @param EAX Lower 32-bits of MSR value.
897 @param EDX Upper 32-bits of MSR value.
903 Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);
906 #define MSR_SILVERMONT_LER_TO_LIP 0x000001DE
910 Core. See Table 35-2. See Section 18.4.2, "Global Counter Control
913 @param ECX MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS (0x0000038E)
914 @param EAX Lower 32-bits of MSR value.
915 @param EDX Upper 32-bits of MSR value.
921 Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS);
922 AsmWriteMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS, Msr);
925 #define MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS 0x0000038E
929 Core. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
932 @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
933 @param EAX Lower 32-bits of MSR value.
934 Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
935 @param EDX Upper 32-bits of MSR value.
936 Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
940 MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;
942 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);
943 AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);
946 #define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1
949 MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE
953 /// Individual bit fields
957 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
964 /// All bit fields as a 32-bit value
968 /// All bit fields as a 64-bit value
971 } MSR_SILVERMONT_PEBS_ENABLE_REGISTER
;
975 Package. Note: C-state values are processor specific C-state code names,
976 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
977 Residency Counter. (R/O) Value since last reset that this package is in
978 processor-specific C6 states. Counts at the TSC Frequency.
980 @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)
981 @param EAX Lower 32-bits of MSR value.
982 @param EDX Upper 32-bits of MSR value.
988 Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);
989 AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);
992 #define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA
996 Core. Note: C-state values are processor specific C-state code names,
997 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
998 Residency Counter. (R/O) Value since last reset that this core is in
999 processor-specific C6 states. Counts at the TSC Frequency.
1001 @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)
1002 @param EAX Lower 32-bits of MSR value.
1003 @param EDX Upper 32-bits of MSR value.
1005 <b>Example usage</b>
1009 Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);
1010 AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);
1013 #define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD
1017 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1019 @param ECX MSR_SILVERMONT_MCi_CTL
1020 @param EAX Lower 32-bits of MSR value.
1021 @param EDX Upper 32-bits of MSR value.
1023 <b>Example usage</b>
1027 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_CTL);
1028 AsmWriteMsr64 (MSR_SILVERMONT_MC3_CTL, Msr);
1032 #define MSR_SILVERMONT_MC3_CTL 0x0000040C
1033 #define MSR_SILVERMONT_MC4_CTL 0x00000410
1034 #define MSR_SILVERMONT_MC5_CTL 0x00000414
1039 Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
1041 @param ECX MSR_SILVERMONT_MCi_STATUS
1042 @param EAX Lower 32-bits of MSR value.
1043 @param EDX Upper 32-bits of MSR value.
1045 <b>Example usage</b>
1049 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_STATUS);
1050 AsmWriteMsr64 (MSR_SILVERMONT_MC3_STATUS, Msr);
1054 #define MSR_SILVERMONT_MC3_STATUS 0x0000040D
1055 #define MSR_SILVERMONT_MC4_STATUS 0x00000411
1056 #define MSR_SILVERMONT_MC5_STATUS 0x00000415
1061 Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MCi_ADDR register
1062 is either not implemented or contains no address if the ADDRV flag in the
1063 MSR_MCi_STATUS register is clear. When not implemented in the processor, all
1064 reads and writes to this MSR will cause a general-protection exception.
1066 @param ECX MSR_SILVERMONT_MCi_ADDR
1067 @param EAX Lower 32-bits of MSR value.
1068 @param EDX Upper 32-bits of MSR value.
1070 <b>Example usage</b>
1074 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_ADDR);
1075 AsmWriteMsr64 (MSR_SILVERMONT_MC3_ADDR, Msr);
1079 #define MSR_SILVERMONT_MC3_ADDR 0x0000040E
1080 #define MSR_SILVERMONT_MC4_ADDR 0x00000412
1081 #define MSR_SILVERMONT_MC5_ADDR 0x00000416
1086 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
1088 @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1089 @param EAX Lower 32-bits of MSR value.
1090 @param EDX Upper 32-bits of MSR value.
1092 <b>Example usage</b>
1096 Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);
1099 #define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1103 Core. Capability Reporting Register of VM-function Controls (R/O) See Table
1106 @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
1107 @param EAX Lower 32-bits of MSR value.
1108 @param EDX Upper 32-bits of MSR value.
1110 <b>Example usage</b>
1114 Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);
1117 #define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491
1121 Core. Note: C-state values are processor specific C-state code names,
1122 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1
1123 Residency Counter. (R/O) Value since last reset that this core is in
1124 processor-specific C1 states. Counts at the TSC frequency.
1126 @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)
1127 @param EAX Lower 32-bits of MSR value.
1128 @param EDX Upper 32-bits of MSR value.
1130 <b>Example usage</b>
1134 Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);
1135 AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);
1138 #define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660
1142 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1145 @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)
1146 @param EAX Lower 32-bits of MSR value.
1147 Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1148 @param EDX Upper 32-bits of MSR value.
1149 Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1151 <b>Example usage</b>
1153 MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;
1155 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);
1158 #define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606
1161 MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT
1165 /// Individual bit fields
1169 /// [Bits 3:0] Power Units. Power related information (in milliWatts) is
1170 /// based on the multiplier, 2^PU; where PU is an unsigned integer
1171 /// represented by bits 3:0. Default value is 0101b, indicating power unit
1172 /// is in 32 milliWatts increment.
1174 UINT32 PowerUnits
:4;
1177 /// [Bits 12:8] Energy Status Units. Energy related information (in
1178 /// microJoules) is based on the multiplier, 2^ESU; where ESU is an
1179 /// unsigned integer represented by bits 12:8. Default value is 00101b,
1180 /// indicating energy unit is in 32 microJoules increment.
1182 UINT32 EnergyStatusUnits
:5;
1185 /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in
1189 UINT32 Reserved3
:12;
1190 UINT32 Reserved4
:32;
1193 /// All bit fields as a 32-bit value
1197 /// All bit fields as a 64-bit value
1200 } MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER
;
1204 Package. PKG RAPL Power Limit Control (R/W).
1206 @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)
1207 @param EAX Lower 32-bits of MSR value.
1208 Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1209 @param EDX Upper 32-bits of MSR value.
1210 Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1212 <b>Example usage</b>
1214 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;
1216 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);
1217 AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);
1220 #define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610
1223 MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT
1227 /// Individual bit fields
1231 /// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package
1232 /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-7.
1236 /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package
1241 /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,
1242 /// "Package RAPL Domain.".
1244 UINT32 ClampingLimit
:1;
1246 /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.
1247 /// If 0 is specified in bits [23:17], defaults to 1 second window.
1251 UINT32 Reserved2
:32;
1254 /// All bit fields as a 32-bit value
1258 /// All bit fields as a 64-bit value
1261 } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER
;
1265 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
1266 and MSR_RAPL_POWER_UNIT in Table 35-7.
1268 @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
1269 @param EAX Lower 32-bits of MSR value.
1270 @param EDX Upper 32-bits of MSR value.
1272 <b>Example usage</b>
1276 Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);
1279 #define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611
1283 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1284 Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.
1286 @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
1287 @param EAX Lower 32-bits of MSR value.
1288 @param EDX Upper 32-bits of MSR value.
1290 <b>Example usage</b>
1294 Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);
1297 #define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639
1301 Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion
1302 policy. Writing a value of 0 disables core level HW demotion policy.
1304 @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)
1305 @param EAX Lower 32-bits of MSR value.
1306 @param EDX Upper 32-bits of MSR value.
1308 <b>Example usage</b>
1312 Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);
1313 AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);
1316 #define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
1320 Package. Module C6 demotion policy config MSR. Controls module (i.e. two
1321 cores sharing the second-level cache) C6 demotion policy. Writing a value of
1322 0 disables module level HW demotion policy.
1324 @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)
1325 @param EAX Lower 32-bits of MSR value.
1326 @param EDX Upper 32-bits of MSR value.
1328 <b>Example usage</b>
1332 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);
1333 AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);
1336 #define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
1340 Module. Module C6 Residency Counter (R/0) Note: C-state values are processor
1341 specific C-state code names, unrelated to MWAIT extension C-state parameters
1342 or ACPI CStates. Time that this module is in module-specific C6 states since
1343 last reset. Counts at 1 Mhz frequency.
1345 @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)
1346 @param EAX Lower 32-bits of MSR value.
1347 @param EDX Upper 32-bits of MSR value.
1349 <b>Example usage</b>
1353 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);
1356 #define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664
1360 Package. PKG RAPL Parameter (R/0).
1362 @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)
1363 @param EAX Lower 32-bits of MSR value.
1364 Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1365 @param EDX Upper 32-bits of MSR value.
1366 Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1368 <b>Example usage</b>
1370 MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;
1372 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);
1375 #define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E
1378 MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO
1382 /// Individual bit fields
1386 /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is
1387 /// the equivalent of thermal specification power of the package domain.
1388 /// The unit of this field is specified by the "Power Units" field of
1389 /// MSR_RAPL_POWER_UNIT.
1391 UINT32 ThermalSpecPower
:15;
1392 UINT32 Reserved1
:17;
1393 UINT32 Reserved2
:32;
1396 /// All bit fields as a 32-bit value
1400 /// All bit fields as a 64-bit value
1403 } MSR_SILVERMONT_PKG_POWER_INFO_REGISTER
;
1407 Package. PP0 RAPL Power Limit Control (R/W).
1409 @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)
1410 @param EAX Lower 32-bits of MSR value.
1411 Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1412 @param EDX Upper 32-bits of MSR value.
1413 Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1415 <b>Example usage</b>
1417 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;
1419 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);
1420 AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);
1423 #define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638
1426 MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT
1430 /// Individual bit fields
1434 /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1435 /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.
1439 /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1445 /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time
1446 /// duration over which the average power must remain below
1447 /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time
1448 /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time
1449 /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.
1450 /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35
1451 /// second time duration. 0x8: 40 second time duration. 0x9: 45 second
1452 /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.
1456 UINT32 Reserved3
:32;
1459 /// All bit fields as a 32-bit value
1463 /// All bit fields as a 64-bit value
1466 } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER
;