2 MSR Definitions for Intel processors based on the Skylake microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14.
24 #ifndef __SKYLAKE_MSR_H__
25 #define __SKYLAKE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
31 RW if MSR_PLATFORM_INFO.[28] = 1.
33 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)
34 @param EAX Lower 32-bits of MSR value.
35 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
36 @param EDX Upper 32-bits of MSR value.
37 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
41 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;
43 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
46 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD
49 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT
53 /// Individual bit fields
57 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
58 /// limit of 1 core active.
62 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
63 /// limit of 2 core active.
67 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
68 /// limit of 3 core active.
72 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
73 /// limit of 4 core active.
79 /// All bit fields as a 32-bit value
83 /// All bit fields as a 64-bit value
86 } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER
;
90 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)
91 that points to the MSR containing the most recent branch record.
93 @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)
94 @param EAX Lower 32-bits of MSR value.
95 @param EDX Upper 32-bits of MSR value.
101 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
102 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
105 #define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9
109 Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
110 an 128-bit external entropy value for key derivation of an enclave.
112 @param ECX MSR_SKYLAKE_SGXOWNER0 (0x00000300)
113 @param EAX Lower 32-bits of MSR value.
114 @param EDX Upper 32-bits of MSR value.
120 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
123 #define MSR_SKYLAKE_SGXOWNER0 0x00000300
127 Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
128 an 128-bit external entropy value for key derivation of an enclave.
130 @param ECX MSR_SKYLAKE_SGXOWNER1 (0x00000301)
131 @param EAX Lower 32-bits of MSR value.
132 @param EDX Upper 32-bits of MSR value.
138 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
141 #define MSR_SKYLAKE_SGXOWNER1 0x00000301
145 See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
148 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS (0x0000038E)
149 @param EAX Lower 32-bits of MSR value.
150 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER.
151 @param EDX Upper 32-bits of MSR value.
152 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER.
156 MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
158 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS);
159 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
162 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS 0x0000038E
165 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS
169 /// Individual bit fields
173 /// [Bit 0] Thread. Ovf_PMC0.
177 /// [Bit 1] Thread. Ovf_PMC1.
181 /// [Bit 2] Thread. Ovf_PMC2.
185 /// [Bit 3] Thread. Ovf_PMC3.
189 /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
193 /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
197 /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
201 /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
206 /// [Bit 32] Thread. Ovf_FixedCtr0.
208 UINT32 Ovf_FixedCtr0
:1;
210 /// [Bit 33] Thread. Ovf_FixedCtr1.
212 UINT32 Ovf_FixedCtr1
:1;
214 /// [Bit 34] Thread. Ovf_FixedCtr2.
216 UINT32 Ovf_FixedCtr2
:1;
219 /// [Bit 55] Thread. Trace_ToPA_PMI.
221 UINT32 Trace_ToPA_PMI
:1;
224 /// [Bit 58] Thread. LBR_Frz.
228 /// [Bit 59] Thread. CTR_Frz.
232 /// [Bit 60] Thread. ASCI.
236 /// [Bit 61] Thread. Ovf_Uncore.
240 /// [Bit 62] Thread. Ovf_BufDSSAVE.
242 UINT32 Ovf_BufDSSAVE
:1;
244 /// [Bit 63] Thread. CondChgd.
249 /// All bit fields as a 64-bit value
252 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER
;
256 See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
259 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
260 @param EAX Lower 32-bits of MSR value.
261 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
262 @param EDX Upper 32-bits of MSR value.
263 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
267 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
269 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
270 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
273 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
276 MSR information returned for MSR index
277 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET
281 /// Individual bit fields
285 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
289 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
293 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
297 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
301 /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
305 /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
309 /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
313 /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
318 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
320 UINT32 Ovf_FixedCtr0
:1;
322 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
324 UINT32 Ovf_FixedCtr1
:1;
326 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
328 UINT32 Ovf_FixedCtr2
:1;
331 /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.
333 UINT32 Trace_ToPA_PMI
:1;
336 /// [Bit 58] Thread. Set 1 to clear LBR_Frz.
340 /// [Bit 59] Thread. Set 1 to clear CTR_Frz.
344 /// [Bit 60] Thread. Set 1 to clear ASCI.
348 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
352 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
354 UINT32 Ovf_BufDSSAVE
:1;
356 /// [Bit 63] Thread. Set 1 to clear CondChgd.
361 /// All bit fields as a 64-bit value
364 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
368 See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
371 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
372 @param EAX Lower 32-bits of MSR value.
373 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
374 @param EDX Upper 32-bits of MSR value.
375 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
379 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
381 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
382 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
385 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
388 MSR information returned for MSR index
389 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET
393 /// Individual bit fields
397 /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.
401 /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.
405 /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.
409 /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.
413 /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).
417 /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).
421 /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).
425 /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).
430 /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.
432 UINT32 Ovf_FixedCtr0
:1;
434 /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.
436 UINT32 Ovf_FixedCtr1
:1;
438 /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.
440 UINT32 Ovf_FixedCtr2
:1;
443 /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.
445 UINT32 Trace_ToPA_PMI
:1;
448 /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.
452 /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.
456 /// [Bit 60] Thread. Set 1 to cause ASCI = 1.
460 /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.
464 /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.
466 UINT32 Ovf_BufDSSAVE
:1;
470 /// All bit fields as a 64-bit value
473 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
477 Thread. FrontEnd Precise Event Condition Select (R/W).
479 @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)
480 @param EAX Lower 32-bits of MSR value.
481 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
482 @param EDX Upper 32-bits of MSR value.
483 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
487 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;
489 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
490 AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
493 #define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7
496 MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND
500 /// Individual bit fields
504 /// [Bits 2:0] Event Code Select.
506 UINT32 EventCodeSelect
:3;
509 /// [Bit 4] Event Code Select High.
511 UINT32 EventCodeSelectHigh
:1;
514 /// [Bits 19:8] IDQ_Bubble_Length Specifier.
516 UINT32 IDQ_Bubble_Length
:12;
518 /// [Bits 22:20] IDQ_Bubble_Width Specifier.
520 UINT32 IDQ_Bubble_Width
:3;
525 /// All bit fields as a 32-bit value
529 /// All bit fields as a 64-bit value
532 } MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
;
536 Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both
537 platform vendor hardware implementation and BIOS enablement support it. This
538 MSR will read 0 if not valid.
540 @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)
541 @param EAX Lower 32-bits of MSR value.
542 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
543 @param EDX Upper 32-bits of MSR value.
544 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
548 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;
550 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
553 #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D
556 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER
560 /// Individual bit fields
564 /// [Bits 31:0] Total energy consumed by all devices in the platform that
565 /// receive power from integrated power delivery mechanism, Included
566 /// platform devices are processor cores, SOC, memory, add-on or
567 /// peripheral devices that get powered directly from the platform power
568 /// delivery means. The energy units are specified in the
569 /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
571 UINT32 TotalEnergy
:32;
575 /// All bit fields as a 32-bit value
579 /// All bit fields as a 64-bit value
582 } MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
;
586 Thread. Productive Performance Count. (R/O). Hardware's view of workload
587 scalability. See Section 14.4.5.1.
589 @param ECX MSR_SKYLAKE_PPERF (0x0000064E)
590 @param EAX Lower 32-bits of MSR value.
591 @param EDX Upper 32-bits of MSR value.
597 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
600 #define MSR_SKYLAKE_PPERF 0x0000064E
604 Package. HDC Configuration (R/W)..
606 @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)
607 @param EAX Lower 32-bits of MSR value.
608 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
609 @param EDX Upper 32-bits of MSR value.
610 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
614 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;
616 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
617 AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
620 #define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652
623 MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG
627 /// Individual bit fields
631 /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for
632 /// MSR_PKG_HDC_DEEP_RESIDENCY.
634 UINT32 PKG_Cx_Monitor
:3;
639 /// All bit fields as a 32-bit value
643 /// All bit fields as a 64-bit value
646 } MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
;
650 Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.
652 @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)
653 @param EAX Lower 32-bits of MSR value.
654 @param EDX Upper 32-bits of MSR value.
660 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
663 #define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653
667 Package. Accumulate the cycles the package was in C2 state and at least one
668 logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.
670 @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)
671 @param EAX Lower 32-bits of MSR value.
672 @param EDX Upper 32-bits of MSR value.
678 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
681 #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655
685 Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.
687 @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)
688 @param EAX Lower 32-bits of MSR value.
689 @param EDX Upper 32-bits of MSR value.
695 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
698 #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656
702 Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate
703 as the TSC. The increment each cycle is weighted by the number of processor
704 cores in the package that reside in C0. If N cores are simultaneously in C0,
705 then each cycle the counter increments by N.
707 @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)
708 @param EAX Lower 32-bits of MSR value.
709 @param EDX Upper 32-bits of MSR value.
715 Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
718 #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658
722 Package. Any Core C0 Residency. (R/O). Increment at the same rate as the
723 TSC. The increment each cycle is one if any processor core in the package is
726 @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)
727 @param EAX Lower 32-bits of MSR value.
728 @param EDX Upper 32-bits of MSR value.
734 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
737 #define MSR_SKYLAKE_ANY_CORE_C0 0x00000659
741 Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate
742 as the TSC. The increment each cycle is one if any processor graphic
743 device's compute engines are in C0.
745 @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)
746 @param EAX Lower 32-bits of MSR value.
747 @param EDX Upper 32-bits of MSR value.
753 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);
756 #define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A
760 Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment
761 at the same rate as the TSC. The increment each cycle is one if at least one
762 compute engine of the processor graphics is in C0 and at least one processor
763 core in the package is also in C0.
765 @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)
766 @param EAX Lower 32-bits of MSR value.
767 @param EDX Upper 32-bits of MSR value.
773 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);
776 #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B
780 Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to
781 limit power consumption of the platform devices to the specified values. The
782 Long Duration power consumption is specified via Platform_Power_Limit_1 and
783 Platform_Power_Limit_1_Time. The Short Duration power consumption limit is
784 specified via the Platform_Power_Limit_2 with duration chosen by the
785 processor. The processor implements an exponential-weighted algorithm in the
786 placement of the time windows.
788 @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)
789 @param EAX Lower 32-bits of MSR value.
790 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
791 @param EDX Upper 32-bits of MSR value.
792 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
796 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;
798 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
799 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);
802 #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C
805 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT
809 /// Individual bit fields
813 /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which
814 /// the platform must not exceed over a time window as specified by
815 /// Power_Limit_1_TIME field. The default value is the Thermal Design
816 /// Power (TDP) and varies with product skus. The unit is specified in
817 /// MSR_RAPLPOWER_UNIT.
819 UINT32 PlatformPowerLimit1
:15;
821 /// [Bit 15] Enable Platform Power Limit #1. When set, enables the
822 /// processor to apply control policy such that the platform power does
823 /// not exceed Platform Power limit #1 over the time window specified by
824 /// Power Limit #1 Time Window.
826 UINT32 EnablePlatformPowerLimit1
:1;
828 /// [Bit 16] Platform Clamping Limitation #1. When set, allows the
829 /// processor to go below the OS requested P states in order to maintain
830 /// the power below specified Platform Power Limit #1 value. This bit is
831 /// writeable only when CPUID (EAX=6):EAX[4] is set.
833 UINT32 PlatformClampingLimitation1
:1;
835 /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the
836 /// duration of the time window over which Platform Power Limit 1 value
837 /// should be maintained for sustained long duration. This field is made
838 /// up of two numbers from the following equation: Time Window = (float)
839 /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =
840 /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is
841 /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,
842 /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].
847 /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which
848 /// the platform must not exceed over the Short Duration time window
849 /// chosen by the processor. The recommended default value is 1.25 times
850 /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).
852 UINT32 PlatformPowerLimit2
:15;
854 /// [Bit 47] Enable Platform Power Limit #2. When set, enables the
855 /// processor to apply control policy such that the platform power does
856 /// not exceed Platform Power limit #2 over the Short Duration time window.
858 UINT32 EnablePlatformPowerLimit2
:1;
860 /// [Bit 48] Platform Clamping Limitation #2. When set, allows the
861 /// processor to go below the OS requested P states in order to maintain
862 /// the power below specified Platform Power Limit #2 value.
864 UINT32 PlatformClampingLimitation2
:1;
867 /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR
868 /// until system RESET.
873 /// All bit fields as a 64-bit value
876 } MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
;
880 Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last
881 branch record registers on the last branch record stack. This part of the
882 stack contains pointers to the source instruction. See also: - Last Branch
883 Record Stack TOS at 1C9H - Section 17.9.
885 @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP
886 @param EAX Lower 32-bits of MSR value.
887 @param EDX Upper 32-bits of MSR value.
893 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
894 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);
898 #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690
899 #define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691
900 #define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692
901 #define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693
902 #define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694
903 #define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695
904 #define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696
905 #define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697
906 #define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698
907 #define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699
908 #define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A
909 #define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B
910 #define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C
911 #define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D
912 #define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E
913 #define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F
917 Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch
918 record registers on the last branch record stack. This part of the stack
919 contains pointers to the destination instruction. See also: - Last Branch
920 Record Stack TOS at 1C9H - Section 17.9.
922 @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP
923 @param EAX Lower 32-bits of MSR value.
924 @param EDX Upper 32-bits of MSR value.
930 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
931 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);
935 #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0
936 #define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1
937 #define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2
938 #define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3
939 #define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4
940 #define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5
941 #define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6
942 #define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7
943 #define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8
944 #define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9
945 #define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA
946 #define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB
947 #define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC
948 #define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD
949 #define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE
950 #define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF
955 Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet
956 of last branch record registers on the last branch record stack. This part
957 of the stack contains flag, TSX-related and elapsed cycle information. See
958 also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR
961 @param ECX MSR_SKYLAKE_LBR_INFO_n
962 @param EAX Lower 32-bits of MSR value.
963 @param EDX Upper 32-bits of MSR value.
969 Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
970 AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);
974 #define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0
975 #define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1
976 #define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2
977 #define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3
978 #define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4
979 #define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5
980 #define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6
981 #define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7
982 #define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8
983 #define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9
984 #define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA
985 #define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB
986 #define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC
987 #define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD
988 #define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE
989 #define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF
990 #define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0
991 #define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1
992 #define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2
993 #define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3
994 #define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4
995 #define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5
996 #define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6
997 #define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7
998 #define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8
999 #define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9
1000 #define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA
1001 #define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB
1002 #define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC
1003 #define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD
1004 #define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE
1005 #define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF