UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __XEON_5600_MSR_H__
  19 #define __XEON_5600_MSR_H__
  20
  21 #include <Register/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel(R) Xeon(R) Processor Series 5600?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x25 || \
  36     DisplayModel == 0x2C    \
  37     )                       \
  38    )
  39
  40 /**
  41   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
  42   handler to handle unsuccessful read of this MSR.
  43
  44   @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
  45   @param  EAX  Lower 32-bits of MSR value.
  46                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  47   @param  EDX  Upper 32-bits of MSR value.
  48                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  49
  50   <b>Example usage</b>
  51   @code
  52   MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;
  53
  54   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
  55   AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
  56   @endcode
  57   @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
  58 **/
  59 #define MSR_XEON_5600_FEATURE_CONFIG             0x0000013C
  60
  61 /**
  62   MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
  63 **/
  64 typedef union {
  65   ///
  66   /// Individual bit fields
  67   ///
  68   struct {
  69     ///
  70     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
  71     /// MSR, the configuration of AES instruction set availability is as
  72     /// follows: 11b: AES instructions are not available until next RESET.
  73     /// otherwise, AES instructions are available. Note, AES instruction set
  74     /// is not available if read is unsuccessful. If the configuration is not
  75     /// 01b, AES instruction can be mis-configured if a privileged agent
  76     /// unintentionally writes 11b.
  77     ///
  78     UINT32  AESConfiguration:2;
  79     UINT32  Reserved1:30;
  80     UINT32  Reserved2:32;
  81   } Bits;
  82   ///
  83   /// All bit fields as a 32-bit value
  84   ///
  85   UINT32  Uint32;
  86   ///
  87   /// All bit fields as a 64-bit value
  88   ///
  89   UINT64  Uint64;
  90 } MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
  91
  92
  93 /**
  94   Thread. Offcore Response Event Select Register (R/W).
  95
  96   @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
  97   @param  EAX  Lower 32-bits of MSR value.
  98   @param  EDX  Upper 32-bits of MSR value.
  99
 100   <b>Example usage</b>
 101   @code
 102   UINT64  Msr;
 103
 104   Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
 105   AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
 106   @endcode
 107   @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 108 **/
 109 #define MSR_XEON_5600_OFFCORE_RSP_1              0x000001A7
 110
 111
 112 /**
 113   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 114   RW if MSR_PLATFORM_INFO.[28] = 1.
 115
 116   @param  ECX  MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
 117   @param  EAX  Lower 32-bits of MSR value.
 118                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 119   @param  EDX  Upper 32-bits of MSR value.
 120                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 121
 122   <b>Example usage</b>
 123   @code
 124   MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;
 125
 126   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
 127   @endcode
 128   @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 129 **/
 130 #define MSR_XEON_5600_TURBO_RATIO_LIMIT          0x000001AD
 131
 132 /**
 133   MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
 134 **/
 135 typedef union {
 136   ///
 137   /// Individual bit fields
 138   ///
 139   struct {
 140     ///
 141     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 142     /// limit of 1 core active.
 143     ///
 144     UINT32  Maximum1C:8;
 145     ///
 146     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 147     /// limit of 2 core active.
 148     ///
 149     UINT32  Maximum2C:8;
 150     ///
 151     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 152     /// limit of 3 core active.
 153     ///
 154     UINT32  Maximum3C:8;
 155     ///
 156     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 157     /// limit of 4 core active.
 158     ///
 159     UINT32  Maximum4C:8;
 160     ///
 161     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 162     /// limit of 5 core active.
 163     ///
 164     UINT32  Maximum5C:8;
 165     ///
 166     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 167     /// limit of 6 core active.
 168     ///
 169     UINT32  Maximum6C:8;
 170     UINT32  Reserved:16;
 171   } Bits;
 172   ///
 173   /// All bit fields as a 64-bit value
 174   ///
 175   UINT64  Uint64;
 176 } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
 177
 178
 179 /**
 180   Package. See Table 2-2.
 181
 182   @param  ECX  MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
 183   @param  EAX  Lower 32-bits of MSR value.
 184   @param  EDX  Upper 32-bits of MSR value.
 185
 186   <b>Example usage</b>
 187   @code
 188   UINT64  Msr;
 189
 190   Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
 191   AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
 192   @endcode
 193   @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
 194 **/
 195 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS      0x000001B0
 196
 197 #endif