2 MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15.
24 #ifndef __XEON_PHI_MSR_H__
25 #define __XEON_PHI_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Thread. SMI Counter (R/O).
32 @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
40 MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
44 @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
46 #define MSR_XEON_PHI_SMI_COUNT 0x00000034
49 MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
53 /// Individual bit fields
57 /// [Bits 31:0] SMI Count (R/O).
63 /// All bit fields as a 32-bit value
67 /// All bit fields as a 64-bit value
70 } MSR_XEON_PHI_SMI_COUNT_REGISTER
;
74 Package. See http://biosbits.org.
76 @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
77 @param EAX Lower 32-bits of MSR value.
78 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
79 @param EDX Upper 32-bits of MSR value.
80 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
84 MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;
86 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
87 AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
89 @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
91 #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
94 MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
98 /// Individual bit fields
103 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
104 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
107 UINT32 MaximumNonTurboRatio
:8;
110 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
111 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
112 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
113 /// Turbo mode is disabled.
117 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
118 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
119 /// and when set to 0, indicates TDP Limit for Turbo mode is not
126 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
127 /// minimum ratio (maximum efficiency) that the processor can operates, in
130 UINT32 MaximumEfficiencyRatio
:8;
134 /// All bit fields as a 64-bit value
137 } MSR_XEON_PHI_PLATFORM_INFO_REGISTER
;
141 Module. C-State Configuration Control (R/W).
143 @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
144 @param EAX Lower 32-bits of MSR value.
145 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
146 @param EDX Upper 32-bits of MSR value.
147 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
151 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
153 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
154 AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
156 @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
158 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
161 MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
165 /// Individual bit fields
169 /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code
170 /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
171 /// Retention 011b: C6 Retention 111b: No limit.
176 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
181 /// [Bit 15] CFG Lock (R/WO).
188 /// All bit fields as a 32-bit value
192 /// All bit fields as a 64-bit value
195 } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
;
199 Module. Power Management IO Redirection in C-state (R/W).
201 @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
202 @param EAX Lower 32-bits of MSR value.
203 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
204 @param EDX Upper 32-bits of MSR value.
205 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
209 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;
211 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
212 AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
214 @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
216 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
219 MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
223 /// Individual bit fields
227 /// [Bits 15:0] LVL_2 Base Address (R/W).
231 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
232 /// maximum C-State code name to be included when IO read to MWAIT
233 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
234 /// is the max C-State to include 110b - C6 is the max C-State to include.
236 UINT32 CStateRange
:3;
241 /// All bit fields as a 32-bit value
245 /// All bit fields as a 64-bit value
248 } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
;
252 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
253 handler to handle unsuccessful read of this MSR.
255 @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
256 @param EAX Lower 32-bits of MSR value.
257 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
258 @param EDX Upper 32-bits of MSR value.
259 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
263 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;
265 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
266 AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
268 @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
270 #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
273 MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
277 /// Individual bit fields
281 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
282 /// MSR, the configuration of AES instruction set availability is as
283 /// follows: 11b: AES instructions are not available until next RESET.
284 /// otherwise, AES instructions are available. Note, AES instruction set
285 /// is not available if read is unsuccessful. If the configuration is not
286 /// 01b, AES instruction can be mis-configured if a privileged agent
287 /// unintentionally writes 11b.
289 UINT32 AESConfiguration
:2;
294 /// All bit fields as a 32-bit value
298 /// All bit fields as a 64-bit value
301 } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
;
305 Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
306 functions to be enabled and disabled.
308 @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
309 @param EAX Lower 32-bits of MSR value.
310 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
311 @param EDX Upper 32-bits of MSR value.
312 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
316 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;
318 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
319 AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
321 @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
323 #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
326 MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
330 /// Individual bit fields
334 /// [Bit 0] Fast-Strings Enable.
336 UINT32 FastStrings
:1;
339 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W).
341 UINT32 AutomaticThermalControlCircuit
:1;
344 /// [Bit 7] Performance Monitoring Available (R).
346 UINT32 PerformanceMonitoring
:1;
349 /// [Bit 11] Branch Trace Storage Unavailable (RO).
353 /// [Bit 12] Precise Event Based Sampling Unavailable (RO).
358 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
363 /// [Bit 18] ENABLE MONITOR FSM (R/W).
368 /// [Bit 22] Limit CPUID Maxval (R/W).
370 UINT32 LimitCpuidMaxval
:1;
372 /// [Bit 23] xTPR Message Disable (R/W).
374 UINT32 xTPR_Message_Disable
:1;
378 /// [Bit 34] XD Bit Disable (R/W).
383 /// [Bit 38] Turbo Mode Disable (R/W).
385 UINT32 TurboModeDisable
:1;
386 UINT32 Reserved10
:25;
389 /// All bit fields as a 64-bit value
392 } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
;
398 @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
399 @param EAX Lower 32-bits of MSR value.
400 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
401 @param EDX Upper 32-bits of MSR value.
402 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
406 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;
408 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
409 AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
411 @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
413 #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
416 MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
420 /// Individual bit fields
425 /// [Bits 23:16] Temperature Target (R).
427 UINT32 TemperatureTarget
:8;
429 /// [Bits 29:24] Target Offset (R/W).
431 UINT32 TargetOffset
:6;
436 /// All bit fields as a 32-bit value
440 /// All bit fields as a 64-bit value
443 } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
;
447 Shared. Offcore Response Event Select Register (R/W).
449 @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
450 @param EAX Lower 32-bits of MSR value.
451 @param EDX Upper 32-bits of MSR value.
457 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
458 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
460 @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
462 #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
466 Shared. Offcore Response Event Select Register (R/W).
468 @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
469 @param EAX Lower 32-bits of MSR value.
470 @param EDX Upper 32-bits of MSR value.
476 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
477 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
479 @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
481 #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
485 Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
487 @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
488 @param EAX Lower 32-bits of MSR value.
489 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
490 @param EDX Upper 32-bits of MSR value.
491 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
495 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;
497 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
498 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
500 @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
502 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
505 MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
509 /// Individual bit fields
514 /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
515 /// processor cores which operates under the maximum ratio limit for group
518 UINT32 MaxCoresGroup0
:7;
520 /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
521 /// ratio limit when the number of active cores are not more than the
522 /// group 0 maximum core count.
524 UINT32 MaxRatioLimitGroup0
:8;
526 /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
527 /// Group 1, which includes the specified number of additional cores plus
528 /// the cores in group 0, operates under the group 1 turbo max ratio limit
529 /// = "group 0 Max ratio limit" - "group ratio delta for group 1".
531 UINT32 MaxIncrementalCoresGroup1
:5;
533 /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
534 /// integer specifying the ratio decrement relative to the Max ratio limit
537 UINT32 DeltaRatioGroup1
:3;
539 /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
540 /// Group 2, which includes the specified number of additional cores plus
541 /// all the cores in group 1, operates under the group 2 turbo max ratio
542 /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
544 UINT32 MaxIncrementalCoresGroup2
:5;
546 /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
547 /// integer specifying the ratio decrement relative to the Max ratio limit
550 UINT32 DeltaRatioGroup2
:3;
552 /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
553 /// Group 3, which includes the specified number of additional cores plus
554 /// all the cores in group 2, operates under the group 3 turbo max ratio
555 /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
557 UINT32 MaxIncrementalCoresGroup3
:5;
559 /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
560 /// integer specifying the ratio decrement relative to the Max ratio limit
563 UINT32 DeltaRatioGroup3
:3;
565 /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
566 /// Group 4, which includes the specified number of additional cores plus
567 /// all the cores in group 3, operates under the group 4 turbo max ratio
568 /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
570 UINT32 MaxIncrementalCoresGroup4
:5;
572 /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
573 /// integer specifying the ratio decrement relative to the Max ratio limit
576 UINT32 DeltaRatioGroup4
:3;
578 /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
579 /// Group 5, which includes the specified number of additional cores plus
580 /// all the cores in group 4, operates under the group 5 turbo max ratio
581 /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
583 UINT32 MaxIncrementalCoresGroup5
:5;
585 /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
586 /// integer specifying the ratio decrement relative to the Max ratio limit
589 UINT32 DeltaRatioGroup5
:3;
591 /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
592 /// Group 6, which includes the specified number of additional cores plus
593 /// all the cores in group 5, operates under the group 6 turbo max ratio
594 /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
596 UINT32 MaxIncrementalCoresGroup6
:5;
598 /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
599 /// integer specifying the ratio decrement relative to the Max ratio limit
602 UINT32 DeltaRatioGroup6
:3;
605 /// All bit fields as a 64-bit value
608 } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
;
612 Thread. Last Branch Record Filtering Select Register (R/W).
614 @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)
615 @param EAX Lower 32-bits of MSR value.
616 @param EDX Upper 32-bits of MSR value.
622 Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
623 AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
625 @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
627 #define MSR_XEON_PHI_LBR_SELECT 0x000001C8
631 Thread. Last Branch Record Stack TOS (R/W).
633 @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
634 @param EAX Lower 32-bits of MSR value.
635 @param EDX Upper 32-bits of MSR value.
641 Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
642 AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
644 @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
646 #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
650 Thread. Last Exception Record From Linear IP (R).
652 @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
653 @param EAX Lower 32-bits of MSR value.
654 @param EDX Upper 32-bits of MSR value.
660 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
662 @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
664 #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
668 Thread. Last Exception Record To Linear IP (R).
670 @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
671 @param EAX Lower 32-bits of MSR value.
672 @param EDX Upper 32-bits of MSR value.
678 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
680 @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
682 #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
686 Thread. See Table 35-2.
688 @param ECX MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS (0x0000038E)
689 @param EAX Lower 32-bits of MSR value.
690 @param EDX Upper 32-bits of MSR value.
696 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);
697 AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);
699 @note MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
701 #define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS 0x0000038E
705 Thread. See Table 35-2.
707 @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
708 @param EAX Lower 32-bits of MSR value.
709 @param EDX Upper 32-bits of MSR value.
715 Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
716 AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
718 @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
720 #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
724 Package. Note: C-state values are processor specific C-state code names,
725 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
726 Residency Counter. (R/O).
728 @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
729 @param EAX Lower 32-bits of MSR value.
730 @param EDX Upper 32-bits of MSR value.
736 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
737 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
739 @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
741 #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
745 Package. Package C6 Residency Counter. (R/O).
747 @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
748 @param EAX Lower 32-bits of MSR value.
749 @param EDX Upper 32-bits of MSR value.
755 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
756 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
758 @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
760 #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
764 Package. Package C7 Residency Counter. (R/O).
766 @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
767 @param EAX Lower 32-bits of MSR value.
768 @param EDX Upper 32-bits of MSR value.
774 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
775 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
777 @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
779 #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
783 Module. Note: C-state values are processor specific C-state code names,
784 unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
785 Residency Counter. (R/O).
787 @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
788 @param EAX Lower 32-bits of MSR value.
789 @param EDX Upper 32-bits of MSR value.
795 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
796 AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
798 @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
800 #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
804 Module. Module C6 Residency Counter. (R/O).
806 @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
807 @param EAX Lower 32-bits of MSR value.
808 @param EDX Upper 32-bits of MSR value.
814 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
815 AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
817 @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
819 #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
823 Core. Note: C-state values are processor specific C-state code names,
824 unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
825 Residency Counter. (R/O).
827 @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
828 @param EAX Lower 32-bits of MSR value.
829 @param EDX Upper 32-bits of MSR value.
835 Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
836 AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
838 @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
840 #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
844 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
846 @param ECX MSR_XEON_PHI_MC3_CTL (0x0000040C)
847 @param EAX Lower 32-bits of MSR value.
848 @param EDX Upper 32-bits of MSR value.
854 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);
855 AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);
857 @note MSR_XEON_PHI_MC3_CTL is defined as MSR_MC3_CTL in SDM.
859 #define MSR_XEON_PHI_MC3_CTL 0x0000040C
863 Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
865 @param ECX MSR_XEON_PHI_MC3_STATUS (0x0000040D)
866 @param EAX Lower 32-bits of MSR value.
867 @param EDX Upper 32-bits of MSR value.
873 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);
874 AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);
876 @note MSR_XEON_PHI_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
878 #define MSR_XEON_PHI_MC3_STATUS 0x0000040D
882 Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
884 @param ECX MSR_XEON_PHI_MC3_ADDR (0x0000040E)
885 @param EAX Lower 32-bits of MSR value.
886 @param EDX Upper 32-bits of MSR value.
892 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);
893 AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);
895 @note MSR_XEON_PHI_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
897 #define MSR_XEON_PHI_MC3_ADDR 0x0000040E
901 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
903 @param ECX MSR_XEON_PHI_MC4_CTL (0x00000410)
904 @param EAX Lower 32-bits of MSR value.
905 @param EDX Upper 32-bits of MSR value.
911 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);
912 AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);
914 @note MSR_XEON_PHI_MC4_CTL is defined as MSR_MC4_CTL in SDM.
916 #define MSR_XEON_PHI_MC4_CTL 0x00000410
920 Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
922 @param ECX MSR_XEON_PHI_MC4_STATUS (0x00000411)
923 @param EAX Lower 32-bits of MSR value.
924 @param EDX Upper 32-bits of MSR value.
930 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);
931 AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);
933 @note MSR_XEON_PHI_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
935 #define MSR_XEON_PHI_MC4_STATUS 0x00000411
939 Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register
940 is either not implemented or contains no address if the ADDRV flag in the
941 MSR_MC4_STATUS register is clear. When not implemented in the processor, all
942 reads and writes to this MSR will cause a general-protection exception.
944 @param ECX MSR_XEON_PHI_MC4_ADDR (0x00000412)
945 @param EAX Lower 32-bits of MSR value.
946 @param EDX Upper 32-bits of MSR value.
952 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);
953 AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);
955 @note MSR_XEON_PHI_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
957 #define MSR_XEON_PHI_MC4_ADDR 0x00000412
961 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
963 @param ECX MSR_XEON_PHI_MC5_CTL (0x00000414)
964 @param EAX Lower 32-bits of MSR value.
965 @param EDX Upper 32-bits of MSR value.
971 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);
972 AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);
974 @note MSR_XEON_PHI_MC5_CTL is defined as MSR_MC5_CTL in SDM.
976 #define MSR_XEON_PHI_MC5_CTL 0x00000414
980 Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
982 @param ECX MSR_XEON_PHI_MC5_STATUS (0x00000415)
983 @param EAX Lower 32-bits of MSR value.
984 @param EDX Upper 32-bits of MSR value.
990 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);
991 AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);
993 @note MSR_XEON_PHI_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
995 #define MSR_XEON_PHI_MC5_STATUS 0x00000415
999 Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
1001 @param ECX MSR_XEON_PHI_MC5_ADDR (0x00000416)
1002 @param EAX Lower 32-bits of MSR value.
1003 @param EDX Upper 32-bits of MSR value.
1005 <b>Example usage</b>
1009 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);
1010 AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);
1012 @note MSR_XEON_PHI_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
1014 #define MSR_XEON_PHI_MC5_ADDR 0x00000416
1018 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
1020 @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1021 @param EAX Lower 32-bits of MSR value.
1022 @param EDX Upper 32-bits of MSR value.
1024 <b>Example usage</b>
1028 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
1030 @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1032 #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1036 Core. Capability Reporting Register of VM-function Controls (R/O) See Table
1039 @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
1040 @param EAX Lower 32-bits of MSR value.
1041 @param EDX Upper 32-bits of MSR value.
1043 <b>Example usage</b>
1047 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
1049 @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
1051 #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
1055 Package. Unit Multipliers used in RAPL Interfaces (R/O).
1057 @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
1058 @param EAX Lower 32-bits of MSR value.
1059 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1060 @param EDX Upper 32-bits of MSR value.
1061 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1063 <b>Example usage</b>
1065 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;
1067 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
1069 @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1071 #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
1074 MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
1078 /// Individual bit fields
1082 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1084 UINT32 PowerUnits
:4;
1087 /// [Bits 12:8] Package. Energy Status Units Energy related information
1088 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1089 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1092 UINT32 EnergyStatusUnits
:5;
1095 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1099 UINT32 Reserved3
:12;
1100 UINT32 Reserved4
:32;
1103 /// All bit fields as a 32-bit value
1107 /// All bit fields as a 64-bit value
1110 } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
;
1114 Package. Note: C-state values are processor specific C-state code names,
1115 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
1116 Residency Counter. (R/O).
1118 @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
1119 @param EAX Lower 32-bits of MSR value.
1120 @param EDX Upper 32-bits of MSR value.
1122 <b>Example usage</b>
1126 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
1127 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
1129 @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1131 #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
1135 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1138 @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
1139 @param EAX Lower 32-bits of MSR value.
1140 @param EDX Upper 32-bits of MSR value.
1142 <b>Example usage</b>
1146 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
1147 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
1149 @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1151 #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
1155 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1157 @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
1158 @param EAX Lower 32-bits of MSR value.
1159 @param EDX Upper 32-bits of MSR value.
1161 <b>Example usage</b>
1165 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
1167 @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1169 #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
1173 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1175 @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
1176 @param EAX Lower 32-bits of MSR value.
1177 @param EDX Upper 32-bits of MSR value.
1179 <b>Example usage</b>
1183 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
1185 @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1187 #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
1191 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1194 @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
1195 @param EAX Lower 32-bits of MSR value.
1196 @param EDX Upper 32-bits of MSR value.
1198 <b>Example usage</b>
1202 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
1203 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
1205 @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1207 #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
1211 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1214 @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
1215 @param EAX Lower 32-bits of MSR value.
1216 @param EDX Upper 32-bits of MSR value.
1218 <b>Example usage</b>
1222 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
1223 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
1225 @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1227 #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
1231 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1233 @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
1234 @param EAX Lower 32-bits of MSR value.
1235 @param EDX Upper 32-bits of MSR value.
1237 <b>Example usage</b>
1241 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
1243 @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1245 #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
1249 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1252 @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
1253 @param EAX Lower 32-bits of MSR value.
1254 @param EDX Upper 32-bits of MSR value.
1256 <b>Example usage</b>
1260 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
1262 @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1264 #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
1268 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1270 @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
1271 @param EAX Lower 32-bits of MSR value.
1272 @param EDX Upper 32-bits of MSR value.
1274 <b>Example usage</b>
1278 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
1279 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
1281 @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1283 #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
1287 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1290 @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
1291 @param EAX Lower 32-bits of MSR value.
1292 @param EDX Upper 32-bits of MSR value.
1294 <b>Example usage</b>
1298 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
1299 AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
1301 @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1303 #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
1307 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1310 @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
1311 @param EAX Lower 32-bits of MSR value.
1312 @param EDX Upper 32-bits of MSR value.
1314 <b>Example usage</b>
1318 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
1320 @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1322 #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
1326 Package. Base TDP Ratio (R/O) See Table 35-20.
1328 @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
1329 @param EAX Lower 32-bits of MSR value.
1330 @param EDX Upper 32-bits of MSR value.
1332 <b>Example usage</b>
1336 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
1338 @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
1340 #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
1344 Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-20.
1346 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
1347 @param EAX Lower 32-bits of MSR value.
1348 @param EDX Upper 32-bits of MSR value.
1350 <b>Example usage</b>
1354 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
1356 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
1358 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
1362 Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-20.
1364 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
1365 @param EAX Lower 32-bits of MSR value.
1366 @param EDX Upper 32-bits of MSR value.
1368 <b>Example usage</b>
1372 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
1374 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
1376 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
1380 Package. ConfigTDP Control (R/W) See Table 35-20.
1382 @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
1383 @param EAX Lower 32-bits of MSR value.
1384 @param EDX Upper 32-bits of MSR value.
1386 <b>Example usage</b>
1390 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
1391 AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
1393 @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
1395 #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
1399 Package. ConfigTDP Control (R/W) See Table 35-20.
1401 @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
1402 @param EAX Lower 32-bits of MSR value.
1403 @param EDX Upper 32-bits of MSR value.
1405 <b>Example usage</b>
1409 Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
1410 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
1412 @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
1414 #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
1418 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1419 refers to processor core frequency).
1421 @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
1422 @param EAX Lower 32-bits of MSR value.
1423 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1424 @param EDX Upper 32-bits of MSR value.
1425 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1427 <b>Example usage</b>
1429 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1431 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
1432 AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1434 @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1436 #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
1439 MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
1443 /// Individual bit fields
1447 /// [Bit 0] PROCHOT Status (R0).
1449 UINT32 PROCHOT_Status
:1;
1451 /// [Bit 1] Thermal Status (R0).
1453 UINT32 ThermalStatus
:1;
1456 /// [Bit 6] VR Therm Alert Status (R0).
1458 UINT32 VRThermAlertStatus
:1;
1461 /// [Bit 8] Electrical Design Point Status (R0).
1463 UINT32 ElectricalDesignPointStatus
:1;
1464 UINT32 Reserved3
:23;
1465 UINT32 Reserved4
:32;
1468 /// All bit fields as a 32-bit value
1472 /// All bit fields as a 64-bit value
1475 } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
;