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[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicX2ApicLib / BaseXApicX2ApicLib.c
1 /** @file
2 Local APIC Library.
3
4 This local APIC library instance supports x2APIC capable processors
5 which have xAPIC and x2APIC modes.
6
7 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include <Register/LocalApic.h>
19
20 #include <Library/BaseLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/LocalApicLib.h>
23 #include <Library/IoLib.h>
24 #include <Library/TimerLib.h>
25 #include <Library/PcdLib.h>
26
27 //
28 // Library internal functions
29 //
30
31 /**
32 Determine if the CPU supports the Local APIC Base Address MSR.
33
34 @retval TRUE The CPU supports the Local APIC Base Address MSR.
35 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
36
37 **/
38 BOOLEAN
39 LocalApicBaseAddressMsrSupported (
40 VOID
41 )
42 {
43 UINT32 RegEax;
44 UINTN FamilyId;
45
46 AsmCpuid (1, &RegEax, NULL, NULL, NULL);
47 FamilyId = BitFieldRead32 (RegEax, 8, 11);
48 if (FamilyId == 0x04 || FamilyId == 0x05) {
49 //
50 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
51 // Local APIC Base Address MSR
52 //
53 return FALSE;
54 }
55 return TRUE;
56 }
57
58 /**
59 Retrieve the base address of local APIC.
60
61 @return The base address of local APIC.
62
63 **/
64 UINTN
65 EFIAPI
66 GetLocalApicBaseAddress (
67 VOID
68 )
69 {
70 MSR_IA32_APIC_BASE ApicBaseMsr;
71
72 if (!LocalApicBaseAddressMsrSupported ()) {
73 //
74 // If CPU does not support Local APIC Base Address MSR, then retrieve
75 // Local APIC Base Address from PCD
76 //
77 return PcdGet32 (PcdCpuLocalApicBaseAddress);
78 }
79
80 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
81
82 return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
83 (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
84 }
85
86 /**
87 Set the base address of local APIC.
88
89 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
90
91 @param[in] BaseAddress Local APIC base address to be set.
92
93 **/
94 VOID
95 EFIAPI
96 SetLocalApicBaseAddress (
97 IN UINTN BaseAddress
98 )
99 {
100 MSR_IA32_APIC_BASE ApicBaseMsr;
101
102 ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
103
104 if (!LocalApicBaseAddressMsrSupported ()) {
105 //
106 // Ignore set request of the CPU does not support APIC Base Address MSR
107 //
108 return;
109 }
110
111 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
112
113 ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);
114 ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
115
116 AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
117 }
118
119 /**
120 Read from a local APIC register.
121
122 This function reads from a local APIC register either in xAPIC or x2APIC mode.
123 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
124 accessed using multiple 32-bit loads or stores, so this function only performs
125 32-bit read.
126
127 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
128 It must be 16-byte aligned.
129
130 @return 32-bit Value read from the register.
131 **/
132 UINT32
133 EFIAPI
134 ReadLocalApicReg (
135 IN UINTN MmioOffset
136 )
137 {
138 UINT32 MsrIndex;
139
140 ASSERT ((MmioOffset & 0xf) == 0);
141
142 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
143 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
144 } else {
145 //
146 // DFR is not supported in x2APIC mode.
147 //
148 ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
149 //
150 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
151 // is not supported in this function for simplicity.
152 //
153 ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
154
155 MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
156 return AsmReadMsr32 (MsrIndex);
157 }
158 }
159
160 /**
161 Write to a local APIC register.
162
163 This function writes to a local APIC register either in xAPIC or x2APIC mode.
164 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
165 accessed using multiple 32-bit loads or stores, so this function only performs
166 32-bit write.
167
168 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
169
170 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
171 It must be 16-byte aligned.
172 @param Value Value to be written to the register.
173 **/
174 VOID
175 EFIAPI
176 WriteLocalApicReg (
177 IN UINTN MmioOffset,
178 IN UINT32 Value
179 )
180 {
181 UINT32 MsrIndex;
182
183 ASSERT ((MmioOffset & 0xf) == 0);
184
185 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
186 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
187 } else {
188 //
189 // DFR is not supported in x2APIC mode.
190 //
191 ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
192 //
193 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
194 // is not supported in this function for simplicity.
195 //
196 ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
197 ASSERT (MmioOffset != XAPIC_ICR_LOW_OFFSET);
198
199 MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
200 //
201 // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.
202 // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.
203 //
204 MemoryFence ();
205 AsmWriteMsr32 (MsrIndex, Value);
206 }
207 }
208
209 /**
210 Send an IPI by writing to ICR.
211
212 This function returns after the IPI has been accepted by the target processor.
213
214 @param IcrLow 32-bit value to be written to the low half of ICR.
215 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
216 **/
217 VOID
218 SendIpi (
219 IN UINT32 IcrLow,
220 IN UINT32 ApicId
221 )
222 {
223 UINT64 MsrValue;
224 LOCAL_APIC_ICR_LOW IcrLowReg;
225 UINTN LocalApciBaseAddress;
226 UINT32 IcrHigh;
227 BOOLEAN InterruptState;
228
229 //
230 // Legacy APIC or X2APIC?
231 //
232 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
233 ASSERT (ApicId <= 0xff);
234
235 InterruptState = SaveAndDisableInterrupts ();
236
237 //
238 // Get base address of this LAPIC
239 //
240 LocalApciBaseAddress = GetLocalApicBaseAddress();
241
242 //
243 // Save existing contents of ICR high 32 bits
244 //
245 IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);
246
247 //
248 // Wait for DeliveryStatus clear in case a previous IPI
249 // is still being sent
250 //
251 do {
252 IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
253 } while (IcrLowReg.Bits.DeliveryStatus != 0);
254
255 //
256 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
257 //
258 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
259 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);
260
261 //
262 // Wait for DeliveryStatus clear again
263 //
264 do {
265 IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
266 } while (IcrLowReg.Bits.DeliveryStatus != 0);
267
268 //
269 // And restore old contents of ICR high
270 //
271 MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
272
273 SetInterruptState (InterruptState);
274
275 } else {
276 //
277 // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
278 // interrupt in x2APIC mode.
279 //
280 MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
281 AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
282 }
283 }
284
285 //
286 // Library API implementation functions
287 //
288
289 /**
290 Get the current local APIC mode.
291
292 If local APIC is disabled, then ASSERT.
293
294 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
295 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
296 **/
297 UINTN
298 EFIAPI
299 GetApicMode (
300 VOID
301 )
302 {
303 MSR_IA32_APIC_BASE ApicBaseMsr;
304
305 if (!LocalApicBaseAddressMsrSupported ()) {
306 //
307 // If CPU does not support APIC Base Address MSR, then return XAPIC mode
308 //
309 return LOCAL_APIC_MODE_XAPIC;
310 }
311
312 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
313 //
314 // Local APIC should have been enabled
315 //
316 ASSERT (ApicBaseMsr.Bits.En != 0);
317 if (ApicBaseMsr.Bits.Extd != 0) {
318 return LOCAL_APIC_MODE_X2APIC;
319 } else {
320 return LOCAL_APIC_MODE_XAPIC;
321 }
322 }
323
324 /**
325 Set the current local APIC mode.
326
327 If the specified local APIC mode is not valid, then ASSERT.
328 If the specified local APIC mode can't be set as current, then ASSERT.
329
330 @param ApicMode APIC mode to be set.
331
332 @note This API must not be called from an interrupt handler or SMI handler.
333 It may result in unpredictable behavior.
334 **/
335 VOID
336 EFIAPI
337 SetApicMode (
338 IN UINTN ApicMode
339 )
340 {
341 UINTN CurrentMode;
342 MSR_IA32_APIC_BASE ApicBaseMsr;
343
344 if (!LocalApicBaseAddressMsrSupported ()) {
345 //
346 // Ignore set request if the CPU does not support APIC Base Address MSR
347 //
348 return;
349 }
350
351 CurrentMode = GetApicMode ();
352 if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {
353 switch (ApicMode) {
354 case LOCAL_APIC_MODE_XAPIC:
355 break;
356 case LOCAL_APIC_MODE_X2APIC:
357 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
358 ApicBaseMsr.Bits.Extd = 1;
359 AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
360 break;
361 default:
362 ASSERT (FALSE);
363 }
364 } else {
365 switch (ApicMode) {
366 case LOCAL_APIC_MODE_XAPIC:
367 //
368 // Transition from x2APIC mode to xAPIC mode is a two-step process:
369 // x2APIC -> Local APIC disabled -> xAPIC
370 //
371 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
372 ApicBaseMsr.Bits.Extd = 0;
373 ApicBaseMsr.Bits.En = 0;
374 AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
375 ApicBaseMsr.Bits.En = 1;
376 AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
377 break;
378 case LOCAL_APIC_MODE_X2APIC:
379 break;
380 default:
381 ASSERT (FALSE);
382 }
383 }
384 }
385
386 /**
387 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
388
389 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
390 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
391 the 32-bit local APIC ID is returned as initial APIC ID.
392
393 @return 32-bit initial local APIC ID of the executing processor.
394 **/
395 UINT32
396 EFIAPI
397 GetInitialApicId (
398 VOID
399 )
400 {
401 UINT32 ApicId;
402 UINT32 MaxCpuIdIndex;
403 UINT32 RegEbx;
404
405 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
406 //
407 // Get the max index of basic CPUID
408 //
409 AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
410 //
411 // If CPUID Leaf B is supported,
412 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
413 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
414 //
415 if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
416 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);
417 return ApicId;
418 }
419 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
420 return RegEbx >> 24;
421 } else {
422 return GetApicId ();
423 }
424 }
425
426 /**
427 Get the local APIC ID of the executing processor.
428
429 @return 32-bit local APIC ID of the executing processor.
430 **/
431 UINT32
432 EFIAPI
433 GetApicId (
434 VOID
435 )
436 {
437 UINT32 ApicId;
438 UINT32 InitApicId;
439
440 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
441 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
442 ApicId = ((InitApicId = GetInitialApicId ()) < 0x100) ? (ApicId >> 24) : InitApicId;
443 }
444
445 return ApicId;
446 }
447
448 /**
449 Get the value of the local APIC version register.
450
451 @return the value of the local APIC version register.
452 **/
453 UINT32
454 EFIAPI
455 GetApicVersion (
456 VOID
457 )
458 {
459 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
460 }
461
462 /**
463 Send a Fixed IPI to a specified target processor.
464
465 This function returns after the IPI has been accepted by the target processor.
466
467 @param ApicId The local APIC ID of the target processor.
468 @param Vector The vector number of the interrupt being sent.
469 **/
470 VOID
471 EFIAPI
472 SendFixedIpi (
473 IN UINT32 ApicId,
474 IN UINT8 Vector
475 )
476 {
477 LOCAL_APIC_ICR_LOW IcrLow;
478
479 IcrLow.Uint32 = 0;
480 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
481 IcrLow.Bits.Level = 1;
482 IcrLow.Bits.Vector = Vector;
483 SendIpi (IcrLow.Uint32, ApicId);
484 }
485
486 /**
487 Send a Fixed IPI to all processors excluding self.
488
489 This function returns after the IPI has been accepted by the target processors.
490
491 @param Vector The vector number of the interrupt being sent.
492 **/
493 VOID
494 EFIAPI
495 SendFixedIpiAllExcludingSelf (
496 IN UINT8 Vector
497 )
498 {
499 LOCAL_APIC_ICR_LOW IcrLow;
500
501 IcrLow.Uint32 = 0;
502 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
503 IcrLow.Bits.Level = 1;
504 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
505 IcrLow.Bits.Vector = Vector;
506 SendIpi (IcrLow.Uint32, 0);
507 }
508
509 /**
510 Send a SMI IPI to a specified target processor.
511
512 This function returns after the IPI has been accepted by the target processor.
513
514 @param ApicId Specify the local APIC ID of the target processor.
515 **/
516 VOID
517 EFIAPI
518 SendSmiIpi (
519 IN UINT32 ApicId
520 )
521 {
522 LOCAL_APIC_ICR_LOW IcrLow;
523
524 IcrLow.Uint32 = 0;
525 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
526 IcrLow.Bits.Level = 1;
527 SendIpi (IcrLow.Uint32, ApicId);
528 }
529
530 /**
531 Send a SMI IPI to all processors excluding self.
532
533 This function returns after the IPI has been accepted by the target processors.
534 **/
535 VOID
536 EFIAPI
537 SendSmiIpiAllExcludingSelf (
538 VOID
539 )
540 {
541 LOCAL_APIC_ICR_LOW IcrLow;
542
543 IcrLow.Uint32 = 0;
544 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
545 IcrLow.Bits.Level = 1;
546 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
547 SendIpi (IcrLow.Uint32, 0);
548 }
549
550 /**
551 Send an INIT IPI to a specified target processor.
552
553 This function returns after the IPI has been accepted by the target processor.
554
555 @param ApicId Specify the local APIC ID of the target processor.
556 **/
557 VOID
558 EFIAPI
559 SendInitIpi (
560 IN UINT32 ApicId
561 )
562 {
563 LOCAL_APIC_ICR_LOW IcrLow;
564
565 IcrLow.Uint32 = 0;
566 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
567 IcrLow.Bits.Level = 1;
568 SendIpi (IcrLow.Uint32, ApicId);
569 }
570
571 /**
572 Send an INIT IPI to all processors excluding self.
573
574 This function returns after the IPI has been accepted by the target processors.
575 **/
576 VOID
577 EFIAPI
578 SendInitIpiAllExcludingSelf (
579 VOID
580 )
581 {
582 LOCAL_APIC_ICR_LOW IcrLow;
583
584 IcrLow.Uint32 = 0;
585 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
586 IcrLow.Bits.Level = 1;
587 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
588 SendIpi (IcrLow.Uint32, 0);
589 }
590
591 /**
592 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
593
594 This function returns after the IPI has been accepted by the target processor.
595
596 if StartupRoutine >= 1M, then ASSERT.
597 if StartupRoutine is not multiple of 4K, then ASSERT.
598
599 @param ApicId Specify the local APIC ID of the target processor.
600 @param StartupRoutine Points to a start-up routine which is below 1M physical
601 address and 4K aligned.
602 **/
603 VOID
604 EFIAPI
605 SendInitSipiSipi (
606 IN UINT32 ApicId,
607 IN UINT32 StartupRoutine
608 )
609 {
610 LOCAL_APIC_ICR_LOW IcrLow;
611
612 ASSERT (StartupRoutine < 0x100000);
613 ASSERT ((StartupRoutine & 0xfff) == 0);
614
615 SendInitIpi (ApicId);
616 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
617 IcrLow.Uint32 = 0;
618 IcrLow.Bits.Vector = (StartupRoutine >> 12);
619 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
620 IcrLow.Bits.Level = 1;
621 SendIpi (IcrLow.Uint32, ApicId);
622 MicroSecondDelay (200);
623 SendIpi (IcrLow.Uint32, ApicId);
624 }
625
626 /**
627 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
628
629 This function returns after the IPI has been accepted by the target processors.
630
631 if StartupRoutine >= 1M, then ASSERT.
632 if StartupRoutine is not multiple of 4K, then ASSERT.
633
634 @param StartupRoutine Points to a start-up routine which is below 1M physical
635 address and 4K aligned.
636 **/
637 VOID
638 EFIAPI
639 SendInitSipiSipiAllExcludingSelf (
640 IN UINT32 StartupRoutine
641 )
642 {
643 LOCAL_APIC_ICR_LOW IcrLow;
644
645 ASSERT (StartupRoutine < 0x100000);
646 ASSERT ((StartupRoutine & 0xfff) == 0);
647
648 SendInitIpiAllExcludingSelf ();
649 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
650 IcrLow.Uint32 = 0;
651 IcrLow.Bits.Vector = (StartupRoutine >> 12);
652 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
653 IcrLow.Bits.Level = 1;
654 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
655 SendIpi (IcrLow.Uint32, 0);
656 MicroSecondDelay (200);
657 SendIpi (IcrLow.Uint32, 0);
658 }
659
660 /**
661 Programming Virtual Wire Mode.
662
663 This function programs the local APIC for virtual wire mode following
664 the example described in chapter A.3 of the MP 1.4 spec.
665
666 IOxAPIC is not involved in this type of virtual wire mode.
667 **/
668 VOID
669 EFIAPI
670 ProgramVirtualWireMode (
671 VOID
672 )
673 {
674 LOCAL_APIC_SVR Svr;
675 LOCAL_APIC_LVT_LINT Lint;
676
677 //
678 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
679 //
680 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
681 Svr.Bits.SpuriousVector = 0xf;
682 Svr.Bits.SoftwareEnable = 1;
683 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
684
685 //
686 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
687 //
688 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
689 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
690 Lint.Bits.InputPinPolarity = 0;
691 Lint.Bits.TriggerMode = 0;
692 Lint.Bits.Mask = 0;
693 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
694
695 //
696 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
697 //
698 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
699 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
700 Lint.Bits.InputPinPolarity = 0;
701 Lint.Bits.TriggerMode = 0;
702 Lint.Bits.Mask = 0;
703 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
704 }
705
706 /**
707 Disable LINT0 & LINT1 interrupts.
708
709 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
710 **/
711 VOID
712 EFIAPI
713 DisableLvtInterrupts (
714 VOID
715 )
716 {
717 LOCAL_APIC_LVT_LINT LvtLint;
718
719 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
720 LvtLint.Bits.Mask = 1;
721 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
722
723 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
724 LvtLint.Bits.Mask = 1;
725 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
726 }
727
728 /**
729 Read the initial count value from the init-count register.
730
731 @return The initial count value read from the init-count register.
732 **/
733 UINT32
734 EFIAPI
735 GetApicTimerInitCount (
736 VOID
737 )
738 {
739 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
740 }
741
742 /**
743 Read the current count value from the current-count register.
744
745 @return The current count value read from the current-count register.
746 **/
747 UINT32
748 EFIAPI
749 GetApicTimerCurrentCount (
750 VOID
751 )
752 {
753 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
754 }
755
756 /**
757 Initialize the local APIC timer.
758
759 The local APIC timer is initialized and enabled.
760
761 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
762 If it is 0, then use the current divide value in the DCR.
763 @param InitCount The initial count value.
764 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
765 @param Vector The timer interrupt vector number.
766 **/
767 VOID
768 EFIAPI
769 InitializeApicTimer (
770 IN UINTN DivideValue,
771 IN UINT32 InitCount,
772 IN BOOLEAN PeriodicMode,
773 IN UINT8 Vector
774 )
775 {
776 LOCAL_APIC_SVR Svr;
777 LOCAL_APIC_DCR Dcr;
778 LOCAL_APIC_LVT_TIMER LvtTimer;
779 UINT32 Divisor;
780
781 //
782 // Ensure local APIC is in software-enabled state.
783 //
784 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
785 Svr.Bits.SoftwareEnable = 1;
786 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
787
788 //
789 // Program init-count register.
790 //
791 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
792
793 if (DivideValue != 0) {
794 ASSERT (DivideValue <= 128);
795 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
796 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
797
798 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
799 Dcr.Bits.DivideValue1 = (Divisor & 0x3);
800 Dcr.Bits.DivideValue2 = (Divisor >> 2);
801 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
802 }
803
804 //
805 // Enable APIC timer interrupt with specified timer mode.
806 //
807 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
808 if (PeriodicMode) {
809 LvtTimer.Bits.TimerMode = 1;
810 } else {
811 LvtTimer.Bits.TimerMode = 0;
812 }
813 LvtTimer.Bits.Mask = 0;
814 LvtTimer.Bits.Vector = Vector;
815 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
816 }
817
818 /**
819 Get the state of the local APIC timer.
820
821 This function will ASSERT if the local APIC is not software enabled.
822
823 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
824 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
825 @param Vector Return the timer interrupt vector number.
826 **/
827 VOID
828 EFIAPI
829 GetApicTimerState (
830 OUT UINTN *DivideValue OPTIONAL,
831 OUT BOOLEAN *PeriodicMode OPTIONAL,
832 OUT UINT8 *Vector OPTIONAL
833 )
834 {
835 UINT32 Divisor;
836 LOCAL_APIC_DCR Dcr;
837 LOCAL_APIC_LVT_TIMER LvtTimer;
838
839 //
840 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
841 // Vector Register.
842 // This bit will be 1, if local APIC is software enabled.
843 //
844 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
845
846 if (DivideValue != NULL) {
847 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
848 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
849 Divisor = (Divisor + 1) & 0x7;
850 *DivideValue = ((UINTN)1) << Divisor;
851 }
852
853 if (PeriodicMode != NULL || Vector != NULL) {
854 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
855 if (PeriodicMode != NULL) {
856 if (LvtTimer.Bits.TimerMode == 1) {
857 *PeriodicMode = TRUE;
858 } else {
859 *PeriodicMode = FALSE;
860 }
861 }
862 if (Vector != NULL) {
863 *Vector = (UINT8) LvtTimer.Bits.Vector;
864 }
865 }
866 }
867
868 /**
869 Enable the local APIC timer interrupt.
870 **/
871 VOID
872 EFIAPI
873 EnableApicTimerInterrupt (
874 VOID
875 )
876 {
877 LOCAL_APIC_LVT_TIMER LvtTimer;
878
879 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
880 LvtTimer.Bits.Mask = 0;
881 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
882 }
883
884 /**
885 Disable the local APIC timer interrupt.
886 **/
887 VOID
888 EFIAPI
889 DisableApicTimerInterrupt (
890 VOID
891 )
892 {
893 LOCAL_APIC_LVT_TIMER LvtTimer;
894
895 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
896 LvtTimer.Bits.Mask = 1;
897 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
898 }
899
900 /**
901 Get the local APIC timer interrupt state.
902
903 @retval TRUE The local APIC timer interrupt is enabled.
904 @retval FALSE The local APIC timer interrupt is disabled.
905 **/
906 BOOLEAN
907 EFIAPI
908 GetApicTimerInterruptState (
909 VOID
910 )
911 {
912 LOCAL_APIC_LVT_TIMER LvtTimer;
913
914 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
915 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
916 }
917
918 /**
919 Send EOI to the local APIC.
920 **/
921 VOID
922 EFIAPI
923 SendApicEoi (
924 VOID
925 )
926 {
927 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
928 }
929
930 /**
931 Get the 32-bit address that a device should use to send a Message Signaled
932 Interrupt (MSI) to the Local APIC of the currently executing processor.
933
934 @return 32-bit address used to send an MSI to the Local APIC.
935 **/
936 UINT32
937 EFIAPI
938 GetApicMsiAddress (
939 VOID
940 )
941 {
942 LOCAL_APIC_MSI_ADDRESS MsiAddress;
943
944 //
945 // Return address for an MSI interrupt to be delivered only to the APIC ID
946 // of the currently executing processor.
947 //
948 MsiAddress.Uint32 = 0;
949 MsiAddress.Bits.BaseAddress = 0xFEE;
950 MsiAddress.Bits.DestinationId = GetApicId ();
951 return MsiAddress.Uint32;
952 }
953
954 /**
955 Get the 64-bit data value that a device should use to send a Message Signaled
956 Interrupt (MSI) to the Local APIC of the currently executing processor.
957
958 If Vector is not in range 0x10..0xFE, then ASSERT().
959 If DeliveryMode is not supported, then ASSERT().
960
961 @param Vector The 8-bit interrupt vector associated with the MSI.
962 Must be in the range 0x10..0xFE
963 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
964 is handled. The only supported values are:
965 0: LOCAL_APIC_DELIVERY_MODE_FIXED
966 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
967 2: LOCAL_APIC_DELIVERY_MODE_SMI
968 4: LOCAL_APIC_DELIVERY_MODE_NMI
969 5: LOCAL_APIC_DELIVERY_MODE_INIT
970 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
971
972 @param LevelTriggered TRUE specifies a level triggered interrupt.
973 FALSE specifies an edge triggered interrupt.
974 @param AssertionLevel Ignored if LevelTriggered is FALSE.
975 TRUE specifies a level triggered interrupt that active
976 when the interrupt line is asserted.
977 FALSE specifies a level triggered interrupt that active
978 when the interrupt line is deasserted.
979
980 @return 64-bit data value used to send an MSI to the Local APIC.
981 **/
982 UINT64
983 EFIAPI
984 GetApicMsiValue (
985 IN UINT8 Vector,
986 IN UINTN DeliveryMode,
987 IN BOOLEAN LevelTriggered,
988 IN BOOLEAN AssertionLevel
989 )
990 {
991 LOCAL_APIC_MSI_DATA MsiData;
992
993 ASSERT (Vector >= 0x10 && Vector <= 0xFE);
994 ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
995
996 MsiData.Uint64 = 0;
997 MsiData.Bits.Vector = Vector;
998 MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
999 if (LevelTriggered) {
1000 MsiData.Bits.TriggerMode = 1;
1001 if (AssertionLevel) {
1002 MsiData.Bits.Level = 1;
1003 }
1004 }
1005 return MsiData.Uint64;
1006 }
EFI Development Kit II mirror for PVE