4 This local APIC library instance supports x2APIC capable processors
5 which have xAPIC and x2APIC modes.
7 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
8 Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 #include <Register/Cpuid.h>
21 #include <Register/Amd/Cpuid.h>
22 #include <Register/Msr.h>
23 #include <Register/LocalApic.h>
25 #include <Library/BaseLib.h>
26 #include <Library/DebugLib.h>
27 #include <Library/LocalApicLib.h>
28 #include <Library/IoLib.h>
29 #include <Library/TimerLib.h>
30 #include <Library/PcdLib.h>
33 // Library internal functions
37 Determine if the standard CPU signature is "AuthenticAMD".
39 @retval TRUE The CPU signature matches.
40 @retval FALSE The CPU signature does not match.
44 StandardSignatureIsAuthenticAMD (
52 AsmCpuid (CPUID_SIGNATURE
, NULL
, &RegEbx
, &RegEcx
, &RegEdx
);
53 return (RegEbx
== CPUID_SIGNATURE_AUTHENTIC_AMD_EBX
&&
54 RegEcx
== CPUID_SIGNATURE_AUTHENTIC_AMD_ECX
&&
55 RegEdx
== CPUID_SIGNATURE_AUTHENTIC_AMD_EDX
);
59 Determine if the CPU supports the Local APIC Base Address MSR.
61 @retval TRUE The CPU supports the Local APIC Base Address MSR.
62 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
66 LocalApicBaseAddressMsrSupported (
73 AsmCpuid (1, &RegEax
, NULL
, NULL
, NULL
);
74 FamilyId
= BitFieldRead32 (RegEax
, 8, 11);
75 if (FamilyId
== 0x04 || FamilyId
== 0x05) {
77 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
78 // Local APIC Base Address MSR
86 Retrieve the base address of local APIC.
88 @return The base address of local APIC.
93 GetLocalApicBaseAddress (
97 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
99 if (!LocalApicBaseAddressMsrSupported ()) {
101 // If CPU does not support Local APIC Base Address MSR, then retrieve
102 // Local APIC Base Address from PCD
104 return PcdGet32 (PcdCpuLocalApicBaseAddress
);
107 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
109 return (UINTN
)(LShiftU64 ((UINT64
) ApicBaseMsr
.Bits
.ApicBaseHi
, 32)) +
110 (((UINTN
)ApicBaseMsr
.Bits
.ApicBase
) << 12);
114 Set the base address of local APIC.
116 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
118 @param[in] BaseAddress Local APIC base address to be set.
123 SetLocalApicBaseAddress (
127 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
129 ASSERT ((BaseAddress
& (SIZE_4KB
- 1)) == 0);
131 if (!LocalApicBaseAddressMsrSupported ()) {
133 // Ignore set request of the CPU does not support APIC Base Address MSR
138 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
140 ApicBaseMsr
.Bits
.ApicBase
= (UINT32
) (BaseAddress
>> 12);
141 ApicBaseMsr
.Bits
.ApicBaseHi
= (UINT32
) (RShiftU64((UINT64
) BaseAddress
, 32));
143 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
147 Read from a local APIC register.
149 This function reads from a local APIC register either in xAPIC or x2APIC mode.
150 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
151 accessed using multiple 32-bit loads or stores, so this function only performs
154 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
155 It must be 16-byte aligned.
157 @return 32-bit Value read from the register.
167 ASSERT ((MmioOffset
& 0xf) == 0);
169 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
170 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset
);
173 // DFR is not supported in x2APIC mode.
175 ASSERT (MmioOffset
!= XAPIC_ICR_DFR_OFFSET
);
177 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
178 // is not supported in this function for simplicity.
180 ASSERT (MmioOffset
!= XAPIC_ICR_HIGH_OFFSET
);
182 MsrIndex
= (UINT32
)(MmioOffset
>> 4) + X2APIC_MSR_BASE_ADDRESS
;
183 return AsmReadMsr32 (MsrIndex
);
188 Write to a local APIC register.
190 This function writes to a local APIC register either in xAPIC or x2APIC mode.
191 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
192 accessed using multiple 32-bit loads or stores, so this function only performs
195 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
197 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
198 It must be 16-byte aligned.
199 @param Value Value to be written to the register.
210 ASSERT ((MmioOffset
& 0xf) == 0);
212 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
213 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset
, Value
);
216 // DFR is not supported in x2APIC mode.
218 ASSERT (MmioOffset
!= XAPIC_ICR_DFR_OFFSET
);
220 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
221 // is not supported in this function for simplicity.
223 ASSERT (MmioOffset
!= XAPIC_ICR_HIGH_OFFSET
);
224 ASSERT (MmioOffset
!= XAPIC_ICR_LOW_OFFSET
);
226 MsrIndex
= (UINT32
)(MmioOffset
>> 4) + X2APIC_MSR_BASE_ADDRESS
;
228 // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.
229 // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.
232 AsmWriteMsr32 (MsrIndex
, Value
);
237 Send an IPI by writing to ICR.
239 This function returns after the IPI has been accepted by the target processor.
241 @param IcrLow 32-bit value to be written to the low half of ICR.
242 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
251 LOCAL_APIC_ICR_LOW IcrLowReg
;
252 UINTN LocalApciBaseAddress
;
254 BOOLEAN InterruptState
;
257 // Legacy APIC or X2APIC?
259 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
260 ASSERT (ApicId
<= 0xff);
262 InterruptState
= SaveAndDisableInterrupts ();
265 // Get base address of this LAPIC
267 LocalApciBaseAddress
= GetLocalApicBaseAddress();
270 // Save existing contents of ICR high 32 bits
272 IcrHigh
= MmioRead32 (LocalApciBaseAddress
+ XAPIC_ICR_HIGH_OFFSET
);
275 // Wait for DeliveryStatus clear in case a previous IPI
276 // is still being sent
279 IcrLowReg
.Uint32
= MmioRead32 (LocalApciBaseAddress
+ XAPIC_ICR_LOW_OFFSET
);
280 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
283 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
285 MmioWrite32 (LocalApciBaseAddress
+ XAPIC_ICR_HIGH_OFFSET
, ApicId
<< 24);
286 MmioWrite32 (LocalApciBaseAddress
+ XAPIC_ICR_LOW_OFFSET
, IcrLow
);
289 // Wait for DeliveryStatus clear again
292 IcrLowReg
.Uint32
= MmioRead32 (LocalApciBaseAddress
+ XAPIC_ICR_LOW_OFFSET
);
293 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
296 // And restore old contents of ICR high
298 MmioWrite32 (LocalApciBaseAddress
+ XAPIC_ICR_HIGH_OFFSET
, IcrHigh
);
300 SetInterruptState (InterruptState
);
304 // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
305 // interrupt in x2APIC mode.
307 MsrValue
= LShiftU64 ((UINT64
) ApicId
, 32) | IcrLow
;
308 AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS
, MsrValue
);
313 // Library API implementation functions
317 Get the current local APIC mode.
319 If local APIC is disabled, then ASSERT.
321 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
322 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
330 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
332 if (!LocalApicBaseAddressMsrSupported ()) {
334 // If CPU does not support APIC Base Address MSR, then return XAPIC mode
336 return LOCAL_APIC_MODE_XAPIC
;
339 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
341 // Local APIC should have been enabled
343 ASSERT (ApicBaseMsr
.Bits
.EN
!= 0);
344 if (ApicBaseMsr
.Bits
.EXTD
!= 0) {
345 return LOCAL_APIC_MODE_X2APIC
;
347 return LOCAL_APIC_MODE_XAPIC
;
352 Set the current local APIC mode.
354 If the specified local APIC mode is not valid, then ASSERT.
355 If the specified local APIC mode can't be set as current, then ASSERT.
357 @param ApicMode APIC mode to be set.
359 @note This API must not be called from an interrupt handler or SMI handler.
360 It may result in unpredictable behavior.
369 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
371 if (!LocalApicBaseAddressMsrSupported ()) {
373 // Ignore set request if the CPU does not support APIC Base Address MSR
378 CurrentMode
= GetApicMode ();
379 if (CurrentMode
== LOCAL_APIC_MODE_XAPIC
) {
381 case LOCAL_APIC_MODE_XAPIC
:
383 case LOCAL_APIC_MODE_X2APIC
:
384 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
385 ApicBaseMsr
.Bits
.EXTD
= 1;
386 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
393 case LOCAL_APIC_MODE_XAPIC
:
395 // Transition from x2APIC mode to xAPIC mode is a two-step process:
396 // x2APIC -> Local APIC disabled -> xAPIC
398 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
399 ApicBaseMsr
.Bits
.EXTD
= 0;
400 ApicBaseMsr
.Bits
.EN
= 0;
401 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
402 ApicBaseMsr
.Bits
.EN
= 1;
403 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
405 case LOCAL_APIC_MODE_X2APIC
:
414 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
416 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
417 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
418 the 32-bit local APIC ID is returned as initial APIC ID.
420 @return 32-bit initial local APIC ID of the executing processor.
429 UINT32 MaxCpuIdIndex
;
432 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
434 // Get the max index of basic CPUID
436 AsmCpuid (CPUID_SIGNATURE
, &MaxCpuIdIndex
, NULL
, NULL
, NULL
);
438 // If CPUID Leaf B is supported,
439 // And CPUID.0BH:EBX[15:0] reports a non-zero value,
440 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
441 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
443 if (MaxCpuIdIndex
>= CPUID_EXTENDED_TOPOLOGY
) {
444 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY
, 0, NULL
, &RegEbx
, NULL
, &ApicId
);
445 if ((RegEbx
& (BIT16
- 1)) != 0) {
449 AsmCpuid (CPUID_VERSION_INFO
, NULL
, &RegEbx
, NULL
, NULL
);
457 Get the local APIC ID of the executing processor.
459 @return 32-bit local APIC ID of the executing processor.
470 ApicId
= ReadLocalApicReg (XAPIC_ID_OFFSET
);
471 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
472 ApicId
= ((InitApicId
= GetInitialApicId ()) < 0x100) ? (ApicId
>> 24) : InitApicId
;
479 Get the value of the local APIC version register.
481 @return the value of the local APIC version register.
489 return ReadLocalApicReg (XAPIC_VERSION_OFFSET
);
493 Send a Fixed IPI to a specified target processor.
495 This function returns after the IPI has been accepted by the target processor.
497 @param ApicId The local APIC ID of the target processor.
498 @param Vector The vector number of the interrupt being sent.
507 LOCAL_APIC_ICR_LOW IcrLow
;
510 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
511 IcrLow
.Bits
.Level
= 1;
512 IcrLow
.Bits
.Vector
= Vector
;
513 SendIpi (IcrLow
.Uint32
, ApicId
);
517 Send a Fixed IPI to all processors excluding self.
519 This function returns after the IPI has been accepted by the target processors.
521 @param Vector The vector number of the interrupt being sent.
525 SendFixedIpiAllExcludingSelf (
529 LOCAL_APIC_ICR_LOW IcrLow
;
532 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
533 IcrLow
.Bits
.Level
= 1;
534 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
535 IcrLow
.Bits
.Vector
= Vector
;
536 SendIpi (IcrLow
.Uint32
, 0);
540 Send a SMI IPI to a specified target processor.
542 This function returns after the IPI has been accepted by the target processor.
544 @param ApicId Specify the local APIC ID of the target processor.
552 LOCAL_APIC_ICR_LOW IcrLow
;
555 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
556 IcrLow
.Bits
.Level
= 1;
557 SendIpi (IcrLow
.Uint32
, ApicId
);
561 Send a SMI IPI to all processors excluding self.
563 This function returns after the IPI has been accepted by the target processors.
567 SendSmiIpiAllExcludingSelf (
571 LOCAL_APIC_ICR_LOW IcrLow
;
574 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
575 IcrLow
.Bits
.Level
= 1;
576 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
577 SendIpi (IcrLow
.Uint32
, 0);
581 Send an INIT IPI to a specified target processor.
583 This function returns after the IPI has been accepted by the target processor.
585 @param ApicId Specify the local APIC ID of the target processor.
593 LOCAL_APIC_ICR_LOW IcrLow
;
596 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
597 IcrLow
.Bits
.Level
= 1;
598 SendIpi (IcrLow
.Uint32
, ApicId
);
602 Send an INIT IPI to all processors excluding self.
604 This function returns after the IPI has been accepted by the target processors.
608 SendInitIpiAllExcludingSelf (
612 LOCAL_APIC_ICR_LOW IcrLow
;
615 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
616 IcrLow
.Bits
.Level
= 1;
617 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
618 SendIpi (IcrLow
.Uint32
, 0);
622 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
624 This function returns after the IPI has been accepted by the target processor.
626 if StartupRoutine >= 1M, then ASSERT.
627 if StartupRoutine is not multiple of 4K, then ASSERT.
629 @param ApicId Specify the local APIC ID of the target processor.
630 @param StartupRoutine Points to a start-up routine which is below 1M physical
631 address and 4K aligned.
637 IN UINT32 StartupRoutine
640 LOCAL_APIC_ICR_LOW IcrLow
;
642 ASSERT (StartupRoutine
< 0x100000);
643 ASSERT ((StartupRoutine
& 0xfff) == 0);
645 SendInitIpi (ApicId
);
646 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
648 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
649 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
650 IcrLow
.Bits
.Level
= 1;
651 SendIpi (IcrLow
.Uint32
, ApicId
);
652 if (!StandardSignatureIsAuthenticAMD ()) {
653 MicroSecondDelay (200);
654 SendIpi (IcrLow
.Uint32
, ApicId
);
659 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
661 This function returns after the IPI has been accepted by the target processors.
663 if StartupRoutine >= 1M, then ASSERT.
664 if StartupRoutine is not multiple of 4K, then ASSERT.
666 @param StartupRoutine Points to a start-up routine which is below 1M physical
667 address and 4K aligned.
671 SendInitSipiSipiAllExcludingSelf (
672 IN UINT32 StartupRoutine
675 LOCAL_APIC_ICR_LOW IcrLow
;
677 ASSERT (StartupRoutine
< 0x100000);
678 ASSERT ((StartupRoutine
& 0xfff) == 0);
680 SendInitIpiAllExcludingSelf ();
681 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
683 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
684 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
685 IcrLow
.Bits
.Level
= 1;
686 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
687 SendIpi (IcrLow
.Uint32
, 0);
688 if (!StandardSignatureIsAuthenticAMD ()) {
689 MicroSecondDelay (200);
690 SendIpi (IcrLow
.Uint32
, 0);
695 Initialize the state of the SoftwareEnable bit in the Local APIC
696 Spurious Interrupt Vector register.
698 @param Enable If TRUE, then set SoftwareEnable to 1
699 If FALSE, then set SoftwareEnable to 0.
704 InitializeLocalApicSoftwareEnable (
711 // Set local APIC software-enabled bit.
713 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
715 if (Svr
.Bits
.SoftwareEnable
== 0) {
716 Svr
.Bits
.SoftwareEnable
= 1;
717 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
720 if (Svr
.Bits
.SoftwareEnable
== 1) {
721 Svr
.Bits
.SoftwareEnable
= 0;
722 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
728 Programming Virtual Wire Mode.
730 This function programs the local APIC for virtual wire mode following
731 the example described in chapter A.3 of the MP 1.4 spec.
733 IOxAPIC is not involved in this type of virtual wire mode.
737 ProgramVirtualWireMode (
742 LOCAL_APIC_LVT_LINT Lint
;
745 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
747 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
748 Svr
.Bits
.SpuriousVector
= 0xf;
749 Svr
.Bits
.SoftwareEnable
= 1;
750 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
753 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
755 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
756 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_EXTINT
;
757 Lint
.Bits
.InputPinPolarity
= 0;
758 Lint
.Bits
.TriggerMode
= 0;
760 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, Lint
.Uint32
);
763 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
765 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
766 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_NMI
;
767 Lint
.Bits
.InputPinPolarity
= 0;
768 Lint
.Bits
.TriggerMode
= 0;
770 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, Lint
.Uint32
);
774 Disable LINT0 & LINT1 interrupts.
776 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
780 DisableLvtInterrupts (
784 LOCAL_APIC_LVT_LINT LvtLint
;
786 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
787 LvtLint
.Bits
.Mask
= 1;
788 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, LvtLint
.Uint32
);
790 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
791 LvtLint
.Bits
.Mask
= 1;
792 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, LvtLint
.Uint32
);
796 Read the initial count value from the init-count register.
798 @return The initial count value read from the init-count register.
802 GetApicTimerInitCount (
806 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
);
810 Read the current count value from the current-count register.
812 @return The current count value read from the current-count register.
816 GetApicTimerCurrentCount (
820 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET
);
824 Initialize the local APIC timer.
826 The local APIC timer is initialized and enabled.
828 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
829 If it is 0, then use the current divide value in the DCR.
830 @param InitCount The initial count value.
831 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
832 @param Vector The timer interrupt vector number.
836 InitializeApicTimer (
837 IN UINTN DivideValue
,
839 IN BOOLEAN PeriodicMode
,
844 LOCAL_APIC_LVT_TIMER LvtTimer
;
848 // Ensure local APIC is in software-enabled state.
850 InitializeLocalApicSoftwareEnable (TRUE
);
853 // Program init-count register.
855 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
, InitCount
);
857 if (DivideValue
!= 0) {
858 ASSERT (DivideValue
<= 128);
859 ASSERT (DivideValue
== GetPowerOfTwo32((UINT32
)DivideValue
));
860 Divisor
= (UINT32
)((HighBitSet32 ((UINT32
)DivideValue
) - 1) & 0x7);
862 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
863 Dcr
.Bits
.DivideValue1
= (Divisor
& 0x3);
864 Dcr
.Bits
.DivideValue2
= (Divisor
>> 2);
865 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
, Dcr
.Uint32
);
869 // Enable APIC timer interrupt with specified timer mode.
871 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
873 LvtTimer
.Bits
.TimerMode
= 1;
875 LvtTimer
.Bits
.TimerMode
= 0;
877 LvtTimer
.Bits
.Mask
= 0;
878 LvtTimer
.Bits
.Vector
= Vector
;
879 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
883 Get the state of the local APIC timer.
885 This function will ASSERT if the local APIC is not software enabled.
887 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
888 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
889 @param Vector Return the timer interrupt vector number.
894 OUT UINTN
*DivideValue OPTIONAL
,
895 OUT BOOLEAN
*PeriodicMode OPTIONAL
,
896 OUT UINT8
*Vector OPTIONAL
901 LOCAL_APIC_LVT_TIMER LvtTimer
;
904 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
906 // This bit will be 1, if local APIC is software enabled.
908 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET
) & BIT8
) != 0);
910 if (DivideValue
!= NULL
) {
911 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
912 Divisor
= Dcr
.Bits
.DivideValue1
| (Dcr
.Bits
.DivideValue2
<< 2);
913 Divisor
= (Divisor
+ 1) & 0x7;
914 *DivideValue
= ((UINTN
)1) << Divisor
;
917 if (PeriodicMode
!= NULL
|| Vector
!= NULL
) {
918 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
919 if (PeriodicMode
!= NULL
) {
920 if (LvtTimer
.Bits
.TimerMode
== 1) {
921 *PeriodicMode
= TRUE
;
923 *PeriodicMode
= FALSE
;
926 if (Vector
!= NULL
) {
927 *Vector
= (UINT8
) LvtTimer
.Bits
.Vector
;
933 Enable the local APIC timer interrupt.
937 EnableApicTimerInterrupt (
941 LOCAL_APIC_LVT_TIMER LvtTimer
;
943 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
944 LvtTimer
.Bits
.Mask
= 0;
945 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
949 Disable the local APIC timer interrupt.
953 DisableApicTimerInterrupt (
957 LOCAL_APIC_LVT_TIMER LvtTimer
;
959 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
960 LvtTimer
.Bits
.Mask
= 1;
961 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
965 Get the local APIC timer interrupt state.
967 @retval TRUE The local APIC timer interrupt is enabled.
968 @retval FALSE The local APIC timer interrupt is disabled.
972 GetApicTimerInterruptState (
976 LOCAL_APIC_LVT_TIMER LvtTimer
;
978 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
979 return (BOOLEAN
)(LvtTimer
.Bits
.Mask
== 0);
983 Send EOI to the local APIC.
991 WriteLocalApicReg (XAPIC_EOI_OFFSET
, 0);
995 Get the 32-bit address that a device should use to send a Message Signaled
996 Interrupt (MSI) to the Local APIC of the currently executing processor.
998 @return 32-bit address used to send an MSI to the Local APIC.
1006 LOCAL_APIC_MSI_ADDRESS MsiAddress
;
1009 // Return address for an MSI interrupt to be delivered only to the APIC ID
1010 // of the currently executing processor.
1012 MsiAddress
.Uint32
= 0;
1013 MsiAddress
.Bits
.BaseAddress
= 0xFEE;
1014 MsiAddress
.Bits
.DestinationId
= GetApicId ();
1015 return MsiAddress
.Uint32
;
1019 Get the 64-bit data value that a device should use to send a Message Signaled
1020 Interrupt (MSI) to the Local APIC of the currently executing processor.
1022 If Vector is not in range 0x10..0xFE, then ASSERT().
1023 If DeliveryMode is not supported, then ASSERT().
1025 @param Vector The 8-bit interrupt vector associated with the MSI.
1026 Must be in the range 0x10..0xFE
1027 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
1028 is handled. The only supported values are:
1029 0: LOCAL_APIC_DELIVERY_MODE_FIXED
1030 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
1031 2: LOCAL_APIC_DELIVERY_MODE_SMI
1032 4: LOCAL_APIC_DELIVERY_MODE_NMI
1033 5: LOCAL_APIC_DELIVERY_MODE_INIT
1034 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
1036 @param LevelTriggered TRUE specifies a level triggered interrupt.
1037 FALSE specifies an edge triggered interrupt.
1038 @param AssertionLevel Ignored if LevelTriggered is FALSE.
1039 TRUE specifies a level triggered interrupt that active
1040 when the interrupt line is asserted.
1041 FALSE specifies a level triggered interrupt that active
1042 when the interrupt line is deasserted.
1044 @return 64-bit data value used to send an MSI to the Local APIC.
1050 IN UINTN DeliveryMode
,
1051 IN BOOLEAN LevelTriggered
,
1052 IN BOOLEAN AssertionLevel
1055 LOCAL_APIC_MSI_DATA MsiData
;
1057 ASSERT (Vector
>= 0x10 && Vector
<= 0xFE);
1058 ASSERT (DeliveryMode
< 8 && DeliveryMode
!= 6 && DeliveryMode
!= 3);
1061 MsiData
.Bits
.Vector
= Vector
;
1062 MsiData
.Bits
.DeliveryMode
= (UINT32
)DeliveryMode
;
1063 if (LevelTriggered
) {
1064 MsiData
.Bits
.TriggerMode
= 1;
1065 if (AssertionLevel
) {
1066 MsiData
.Bits
.Level
= 1;
1069 return MsiData
.Uint64
;
1073 Get Package ID/Core ID/Thread ID of a processor.
1075 The algorithm assumes the target system has symmetry across physical
1076 package boundaries with respect to the number of logical processors
1077 per package, number of cores per package.
1079 @param[in] InitialApicId Initial APIC ID of the target logical processor.
1080 @param[out] Package Returns the processor package ID.
1081 @param[out] Core Returns the processor core ID.
1082 @param[out] Thread Returns the processor thread ID.
1086 GetProcessorLocationByApicId (
1087 IN UINT32 InitialApicId
,
1088 OUT UINT32
*Package OPTIONAL
,
1089 OUT UINT32
*Core OPTIONAL
,
1090 OUT UINT32
*Thread OPTIONAL
1093 BOOLEAN TopologyLeafSupported
;
1094 CPUID_VERSION_INFO_EBX VersionInfoEbx
;
1095 CPUID_VERSION_INFO_EDX VersionInfoEdx
;
1096 CPUID_CACHE_PARAMS_EAX CacheParamsEax
;
1097 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax
;
1098 CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx
;
1099 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx
;
1100 CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx
;
1101 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx
;
1102 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx
;
1103 UINT32 MaxStandardCpuIdIndex
;
1104 UINT32 MaxExtendedCpuIdIndex
;
1107 UINT32 MaxLogicProcessorsPerPackage
;
1108 UINT32 MaxCoresPerPackage
;
1113 // Check if the processor is capable of supporting more than one logical processor.
1115 AsmCpuid (CPUID_VERSION_INFO
, NULL
, NULL
, NULL
, &VersionInfoEdx
.Uint32
);
1116 if (VersionInfoEdx
.Bits
.HTT
== 0) {
1117 if (Thread
!= NULL
) {
1123 if (Package
!= NULL
) {
1130 // Assume three-level mapping of APIC ID: Package|Core|Thread.
1136 // Get max index of CPUID
1138 AsmCpuid (CPUID_SIGNATURE
, &MaxStandardCpuIdIndex
, NULL
, NULL
, NULL
);
1139 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &MaxExtendedCpuIdIndex
, NULL
, NULL
, NULL
);
1142 // If the extended topology enumeration leaf is available, it
1143 // is the preferred mechanism for enumerating topology.
1145 TopologyLeafSupported
= FALSE
;
1146 if (MaxStandardCpuIdIndex
>= CPUID_EXTENDED_TOPOLOGY
) {
1148 CPUID_EXTENDED_TOPOLOGY
,
1150 &ExtendedTopologyEax
.Uint32
,
1151 &ExtendedTopologyEbx
.Uint32
,
1152 &ExtendedTopologyEcx
.Uint32
,
1156 // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
1157 // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
1158 // supported on that processor.
1160 if (ExtendedTopologyEbx
.Uint32
!= 0) {
1161 TopologyLeafSupported
= TRUE
;
1164 // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
1165 // the SMT sub-field of x2APIC ID.
1167 LevelType
= ExtendedTopologyEcx
.Bits
.LevelType
;
1168 ASSERT (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
);
1169 ThreadBits
= ExtendedTopologyEax
.Bits
.ApicIdShift
;
1172 // Software must not assume any "level type" encoding
1173 // value to be related to any sub-leaf index, except sub-leaf 0.
1178 CPUID_EXTENDED_TOPOLOGY
,
1180 &ExtendedTopologyEax
.Uint32
,
1182 &ExtendedTopologyEcx
.Uint32
,
1185 LevelType
= ExtendedTopologyEcx
.Bits
.LevelType
;
1186 if (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE
) {
1187 CoreBits
= ExtendedTopologyEax
.Bits
.ApicIdShift
- ThreadBits
;
1191 } while (LevelType
!= CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID
);
1195 if (!TopologyLeafSupported
) {
1197 // Get logical processor count
1199 AsmCpuid (CPUID_VERSION_INFO
, NULL
, &VersionInfoEbx
.Uint32
, NULL
, NULL
);
1200 MaxLogicProcessorsPerPackage
= VersionInfoEbx
.Bits
.MaximumAddressableIdsForLogicalProcessors
;
1203 // Assume single-core processor
1205 MaxCoresPerPackage
= 1;
1208 // Check for topology extensions on AMD processor
1210 if (StandardSignatureIsAuthenticAMD()) {
1211 if (MaxExtendedCpuIdIndex
>= CPUID_AMD_PROCESSOR_TOPOLOGY
) {
1212 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, &AmdExtendedCpuSigEcx
.Uint32
, NULL
);
1213 if (AmdExtendedCpuSigEcx
.Bits
.TopologyExtensions
!= 0) {
1215 // Account for max possible thread count to decode ApicId
1217 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE
, NULL
, NULL
, &AmdVirPhyAddressSizeEcx
.Uint32
, NULL
);
1218 MaxLogicProcessorsPerPackage
= 1 << AmdVirPhyAddressSizeEcx
.Bits
.ApicIdCoreIdSize
;
1221 // Get cores per processor package
1223 AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY
, NULL
, &AmdProcessorTopologyEbx
.Uint32
, NULL
, NULL
);
1224 MaxCoresPerPackage
= MaxLogicProcessorsPerPackage
/ (AmdProcessorTopologyEbx
.Bits
.ThreadsPerCore
+ 1);
1230 // Extract core count based on CACHE information
1232 if (MaxStandardCpuIdIndex
>= CPUID_CACHE_PARAMS
) {
1233 AsmCpuidEx (CPUID_CACHE_PARAMS
, 0, &CacheParamsEax
.Uint32
, NULL
, NULL
, NULL
);
1234 if (CacheParamsEax
.Uint32
!= 0) {
1235 MaxCoresPerPackage
= CacheParamsEax
.Bits
.MaximumAddressableIdsForLogicalProcessors
+ 1;
1240 ThreadBits
= (UINTN
)(HighBitSet32(MaxLogicProcessorsPerPackage
/ MaxCoresPerPackage
- 1) + 1);
1241 CoreBits
= (UINTN
)(HighBitSet32(MaxCoresPerPackage
- 1) + 1);
1244 if (Thread
!= NULL
) {
1245 *Thread
= InitialApicId
& ((1 << ThreadBits
) - 1);
1248 *Core
= (InitialApicId
>> ThreadBits
) & ((1 << CoreBits
) - 1);
1250 if (Package
!= NULL
) {
1251 *Package
= (InitialApicId
>> (ThreadBits
+ CoreBits
));