4 This local APIC library instance supports x2APIC capable processors
5 which have xAPIC and x2APIC modes.
7 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Register/Cpuid.h>
19 #include <Register/Msr.h>
20 #include <Register/LocalApic.h>
22 #include <Library/BaseLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/LocalApicLib.h>
25 #include <Library/IoLib.h>
26 #include <Library/TimerLib.h>
27 #include <Library/PcdLib.h>
30 // Library internal functions
34 Determine if the CPU supports the Local APIC Base Address MSR.
36 @retval TRUE The CPU supports the Local APIC Base Address MSR.
37 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
41 LocalApicBaseAddressMsrSupported (
48 AsmCpuid (1, &RegEax
, NULL
, NULL
, NULL
);
49 FamilyId
= BitFieldRead32 (RegEax
, 8, 11);
50 if (FamilyId
== 0x04 || FamilyId
== 0x05) {
52 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
53 // Local APIC Base Address MSR
61 Retrieve the base address of local APIC.
63 @return The base address of local APIC.
68 GetLocalApicBaseAddress (
72 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
74 if (!LocalApicBaseAddressMsrSupported ()) {
76 // If CPU does not support Local APIC Base Address MSR, then retrieve
77 // Local APIC Base Address from PCD
79 return PcdGet32 (PcdCpuLocalApicBaseAddress
);
82 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
84 return (UINTN
)(LShiftU64 ((UINT64
) ApicBaseMsr
.Bits
.ApicBaseHi
, 32)) +
85 (((UINTN
)ApicBaseMsr
.Bits
.ApicBase
) << 12);
89 Set the base address of local APIC.
91 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
93 @param[in] BaseAddress Local APIC base address to be set.
98 SetLocalApicBaseAddress (
102 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
104 ASSERT ((BaseAddress
& (SIZE_4KB
- 1)) == 0);
106 if (!LocalApicBaseAddressMsrSupported ()) {
108 // Ignore set request of the CPU does not support APIC Base Address MSR
113 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
115 ApicBaseMsr
.Bits
.ApicBase
= (UINT32
) (BaseAddress
>> 12);
116 ApicBaseMsr
.Bits
.ApicBaseHi
= (UINT32
) (RShiftU64((UINT64
) BaseAddress
, 32));
118 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
122 Read from a local APIC register.
124 This function reads from a local APIC register either in xAPIC or x2APIC mode.
125 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
126 accessed using multiple 32-bit loads or stores, so this function only performs
129 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
130 It must be 16-byte aligned.
132 @return 32-bit Value read from the register.
142 ASSERT ((MmioOffset
& 0xf) == 0);
144 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
145 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset
);
148 // DFR is not supported in x2APIC mode.
150 ASSERT (MmioOffset
!= XAPIC_ICR_DFR_OFFSET
);
152 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
153 // is not supported in this function for simplicity.
155 ASSERT (MmioOffset
!= XAPIC_ICR_HIGH_OFFSET
);
157 MsrIndex
= (UINT32
)(MmioOffset
>> 4) + X2APIC_MSR_BASE_ADDRESS
;
158 return AsmReadMsr32 (MsrIndex
);
163 Write to a local APIC register.
165 This function writes to a local APIC register either in xAPIC or x2APIC mode.
166 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
167 accessed using multiple 32-bit loads or stores, so this function only performs
170 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
172 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
173 It must be 16-byte aligned.
174 @param Value Value to be written to the register.
185 ASSERT ((MmioOffset
& 0xf) == 0);
187 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
188 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset
, Value
);
191 // DFR is not supported in x2APIC mode.
193 ASSERT (MmioOffset
!= XAPIC_ICR_DFR_OFFSET
);
195 // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
196 // is not supported in this function for simplicity.
198 ASSERT (MmioOffset
!= XAPIC_ICR_HIGH_OFFSET
);
199 ASSERT (MmioOffset
!= XAPIC_ICR_LOW_OFFSET
);
201 MsrIndex
= (UINT32
)(MmioOffset
>> 4) + X2APIC_MSR_BASE_ADDRESS
;
203 // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.
204 // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.
207 AsmWriteMsr32 (MsrIndex
, Value
);
212 Send an IPI by writing to ICR.
214 This function returns after the IPI has been accepted by the target processor.
216 @param IcrLow 32-bit value to be written to the low half of ICR.
217 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
226 LOCAL_APIC_ICR_LOW IcrLowReg
;
227 UINTN LocalApciBaseAddress
;
229 BOOLEAN InterruptState
;
232 // Legacy APIC or X2APIC?
234 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
235 ASSERT (ApicId
<= 0xff);
237 InterruptState
= SaveAndDisableInterrupts ();
240 // Get base address of this LAPIC
242 LocalApciBaseAddress
= GetLocalApicBaseAddress();
245 // Save existing contents of ICR high 32 bits
247 IcrHigh
= MmioRead32 (LocalApciBaseAddress
+ XAPIC_ICR_HIGH_OFFSET
);
250 // Wait for DeliveryStatus clear in case a previous IPI
251 // is still being sent
254 IcrLowReg
.Uint32
= MmioRead32 (LocalApciBaseAddress
+ XAPIC_ICR_LOW_OFFSET
);
255 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
258 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
260 MmioWrite32 (LocalApciBaseAddress
+ XAPIC_ICR_HIGH_OFFSET
, ApicId
<< 24);
261 MmioWrite32 (LocalApciBaseAddress
+ XAPIC_ICR_LOW_OFFSET
, IcrLow
);
264 // Wait for DeliveryStatus clear again
267 IcrLowReg
.Uint32
= MmioRead32 (LocalApciBaseAddress
+ XAPIC_ICR_LOW_OFFSET
);
268 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
271 // And restore old contents of ICR high
273 MmioWrite32 (LocalApciBaseAddress
+ XAPIC_ICR_HIGH_OFFSET
, IcrHigh
);
275 SetInterruptState (InterruptState
);
279 // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
280 // interrupt in x2APIC mode.
282 MsrValue
= LShiftU64 ((UINT64
) ApicId
, 32) | IcrLow
;
283 AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS
, MsrValue
);
288 // Library API implementation functions
292 Get the current local APIC mode.
294 If local APIC is disabled, then ASSERT.
296 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
297 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
305 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
307 if (!LocalApicBaseAddressMsrSupported ()) {
309 // If CPU does not support APIC Base Address MSR, then return XAPIC mode
311 return LOCAL_APIC_MODE_XAPIC
;
314 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
316 // Local APIC should have been enabled
318 ASSERT (ApicBaseMsr
.Bits
.EN
!= 0);
319 if (ApicBaseMsr
.Bits
.EXTD
!= 0) {
320 return LOCAL_APIC_MODE_X2APIC
;
322 return LOCAL_APIC_MODE_XAPIC
;
327 Set the current local APIC mode.
329 If the specified local APIC mode is not valid, then ASSERT.
330 If the specified local APIC mode can't be set as current, then ASSERT.
332 @param ApicMode APIC mode to be set.
334 @note This API must not be called from an interrupt handler or SMI handler.
335 It may result in unpredictable behavior.
344 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
346 if (!LocalApicBaseAddressMsrSupported ()) {
348 // Ignore set request if the CPU does not support APIC Base Address MSR
353 CurrentMode
= GetApicMode ();
354 if (CurrentMode
== LOCAL_APIC_MODE_XAPIC
) {
356 case LOCAL_APIC_MODE_XAPIC
:
358 case LOCAL_APIC_MODE_X2APIC
:
359 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
360 ApicBaseMsr
.Bits
.EXTD
= 1;
361 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
368 case LOCAL_APIC_MODE_XAPIC
:
370 // Transition from x2APIC mode to xAPIC mode is a two-step process:
371 // x2APIC -> Local APIC disabled -> xAPIC
373 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
374 ApicBaseMsr
.Bits
.EXTD
= 0;
375 ApicBaseMsr
.Bits
.EN
= 0;
376 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
377 ApicBaseMsr
.Bits
.EN
= 1;
378 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
380 case LOCAL_APIC_MODE_X2APIC
:
389 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
391 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
392 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
393 the 32-bit local APIC ID is returned as initial APIC ID.
395 @return 32-bit initial local APIC ID of the executing processor.
404 UINT32 MaxCpuIdIndex
;
407 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
409 // Get the max index of basic CPUID
411 AsmCpuid (CPUID_SIGNATURE
, &MaxCpuIdIndex
, NULL
, NULL
, NULL
);
413 // If CPUID Leaf B is supported,
414 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
415 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
417 if (MaxCpuIdIndex
>= CPUID_EXTENDED_TOPOLOGY
) {
418 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY
, 0, NULL
, NULL
, NULL
, &ApicId
);
421 AsmCpuid (CPUID_VERSION_INFO
, NULL
, &RegEbx
, NULL
, NULL
);
429 Get the local APIC ID of the executing processor.
431 @return 32-bit local APIC ID of the executing processor.
442 ApicId
= ReadLocalApicReg (XAPIC_ID_OFFSET
);
443 if (GetApicMode () == LOCAL_APIC_MODE_XAPIC
) {
444 ApicId
= ((InitApicId
= GetInitialApicId ()) < 0x100) ? (ApicId
>> 24) : InitApicId
;
451 Get the value of the local APIC version register.
453 @return the value of the local APIC version register.
461 return ReadLocalApicReg (XAPIC_VERSION_OFFSET
);
465 Send a Fixed IPI to a specified target processor.
467 This function returns after the IPI has been accepted by the target processor.
469 @param ApicId The local APIC ID of the target processor.
470 @param Vector The vector number of the interrupt being sent.
479 LOCAL_APIC_ICR_LOW IcrLow
;
482 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
483 IcrLow
.Bits
.Level
= 1;
484 IcrLow
.Bits
.Vector
= Vector
;
485 SendIpi (IcrLow
.Uint32
, ApicId
);
489 Send a Fixed IPI to all processors excluding self.
491 This function returns after the IPI has been accepted by the target processors.
493 @param Vector The vector number of the interrupt being sent.
497 SendFixedIpiAllExcludingSelf (
501 LOCAL_APIC_ICR_LOW IcrLow
;
504 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
505 IcrLow
.Bits
.Level
= 1;
506 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
507 IcrLow
.Bits
.Vector
= Vector
;
508 SendIpi (IcrLow
.Uint32
, 0);
512 Send a SMI IPI to a specified target processor.
514 This function returns after the IPI has been accepted by the target processor.
516 @param ApicId Specify the local APIC ID of the target processor.
524 LOCAL_APIC_ICR_LOW IcrLow
;
527 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
528 IcrLow
.Bits
.Level
= 1;
529 SendIpi (IcrLow
.Uint32
, ApicId
);
533 Send a SMI IPI to all processors excluding self.
535 This function returns after the IPI has been accepted by the target processors.
539 SendSmiIpiAllExcludingSelf (
543 LOCAL_APIC_ICR_LOW IcrLow
;
546 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
547 IcrLow
.Bits
.Level
= 1;
548 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
549 SendIpi (IcrLow
.Uint32
, 0);
553 Send an INIT IPI to a specified target processor.
555 This function returns after the IPI has been accepted by the target processor.
557 @param ApicId Specify the local APIC ID of the target processor.
565 LOCAL_APIC_ICR_LOW IcrLow
;
568 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
569 IcrLow
.Bits
.Level
= 1;
570 SendIpi (IcrLow
.Uint32
, ApicId
);
574 Send an INIT IPI to all processors excluding self.
576 This function returns after the IPI has been accepted by the target processors.
580 SendInitIpiAllExcludingSelf (
584 LOCAL_APIC_ICR_LOW IcrLow
;
587 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
588 IcrLow
.Bits
.Level
= 1;
589 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
590 SendIpi (IcrLow
.Uint32
, 0);
594 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
596 This function returns after the IPI has been accepted by the target processor.
598 if StartupRoutine >= 1M, then ASSERT.
599 if StartupRoutine is not multiple of 4K, then ASSERT.
601 @param ApicId Specify the local APIC ID of the target processor.
602 @param StartupRoutine Points to a start-up routine which is below 1M physical
603 address and 4K aligned.
609 IN UINT32 StartupRoutine
612 LOCAL_APIC_ICR_LOW IcrLow
;
614 ASSERT (StartupRoutine
< 0x100000);
615 ASSERT ((StartupRoutine
& 0xfff) == 0);
617 SendInitIpi (ApicId
);
618 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
620 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
621 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
622 IcrLow
.Bits
.Level
= 1;
623 SendIpi (IcrLow
.Uint32
, ApicId
);
624 MicroSecondDelay (200);
625 SendIpi (IcrLow
.Uint32
, ApicId
);
629 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
631 This function returns after the IPI has been accepted by the target processors.
633 if StartupRoutine >= 1M, then ASSERT.
634 if StartupRoutine is not multiple of 4K, then ASSERT.
636 @param StartupRoutine Points to a start-up routine which is below 1M physical
637 address and 4K aligned.
641 SendInitSipiSipiAllExcludingSelf (
642 IN UINT32 StartupRoutine
645 LOCAL_APIC_ICR_LOW IcrLow
;
647 ASSERT (StartupRoutine
< 0x100000);
648 ASSERT ((StartupRoutine
& 0xfff) == 0);
650 SendInitIpiAllExcludingSelf ();
651 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
653 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
654 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
655 IcrLow
.Bits
.Level
= 1;
656 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
657 SendIpi (IcrLow
.Uint32
, 0);
658 MicroSecondDelay (200);
659 SendIpi (IcrLow
.Uint32
, 0);
663 Initialize the state of the SoftwareEnable bit in the Local APIC
664 Spurious Interrupt Vector register.
666 @param Enable If TRUE, then set SoftwareEnable to 1
667 If FALSE, then set SoftwareEnable to 0.
672 InitializeLocalApicSoftwareEnable (
679 // Set local APIC software-enabled bit.
681 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
683 if (Svr
.Bits
.SoftwareEnable
== 0) {
684 Svr
.Bits
.SoftwareEnable
= 1;
685 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
688 if (Svr
.Bits
.SoftwareEnable
== 1) {
689 Svr
.Bits
.SoftwareEnable
= 0;
690 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
696 Programming Virtual Wire Mode.
698 This function programs the local APIC for virtual wire mode following
699 the example described in chapter A.3 of the MP 1.4 spec.
701 IOxAPIC is not involved in this type of virtual wire mode.
705 ProgramVirtualWireMode (
710 LOCAL_APIC_LVT_LINT Lint
;
713 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
715 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
716 Svr
.Bits
.SpuriousVector
= 0xf;
717 Svr
.Bits
.SoftwareEnable
= 1;
718 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
721 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
723 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
724 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_EXTINT
;
725 Lint
.Bits
.InputPinPolarity
= 0;
726 Lint
.Bits
.TriggerMode
= 0;
728 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, Lint
.Uint32
);
731 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
733 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
734 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_NMI
;
735 Lint
.Bits
.InputPinPolarity
= 0;
736 Lint
.Bits
.TriggerMode
= 0;
738 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, Lint
.Uint32
);
742 Disable LINT0 & LINT1 interrupts.
744 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
748 DisableLvtInterrupts (
752 LOCAL_APIC_LVT_LINT LvtLint
;
754 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
755 LvtLint
.Bits
.Mask
= 1;
756 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, LvtLint
.Uint32
);
758 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
759 LvtLint
.Bits
.Mask
= 1;
760 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, LvtLint
.Uint32
);
764 Read the initial count value from the init-count register.
766 @return The initial count value read from the init-count register.
770 GetApicTimerInitCount (
774 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
);
778 Read the current count value from the current-count register.
780 @return The current count value read from the current-count register.
784 GetApicTimerCurrentCount (
788 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET
);
792 Initialize the local APIC timer.
794 The local APIC timer is initialized and enabled.
796 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
797 If it is 0, then use the current divide value in the DCR.
798 @param InitCount The initial count value.
799 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
800 @param Vector The timer interrupt vector number.
804 InitializeApicTimer (
805 IN UINTN DivideValue
,
807 IN BOOLEAN PeriodicMode
,
812 LOCAL_APIC_LVT_TIMER LvtTimer
;
816 // Ensure local APIC is in software-enabled state.
818 InitializeLocalApicSoftwareEnable (TRUE
);
821 // Program init-count register.
823 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
, InitCount
);
825 if (DivideValue
!= 0) {
826 ASSERT (DivideValue
<= 128);
827 ASSERT (DivideValue
== GetPowerOfTwo32((UINT32
)DivideValue
));
828 Divisor
= (UINT32
)((HighBitSet32 ((UINT32
)DivideValue
) - 1) & 0x7);
830 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
831 Dcr
.Bits
.DivideValue1
= (Divisor
& 0x3);
832 Dcr
.Bits
.DivideValue2
= (Divisor
>> 2);
833 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
, Dcr
.Uint32
);
837 // Enable APIC timer interrupt with specified timer mode.
839 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
841 LvtTimer
.Bits
.TimerMode
= 1;
843 LvtTimer
.Bits
.TimerMode
= 0;
845 LvtTimer
.Bits
.Mask
= 0;
846 LvtTimer
.Bits
.Vector
= Vector
;
847 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
851 Get the state of the local APIC timer.
853 This function will ASSERT if the local APIC is not software enabled.
855 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
856 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
857 @param Vector Return the timer interrupt vector number.
862 OUT UINTN
*DivideValue OPTIONAL
,
863 OUT BOOLEAN
*PeriodicMode OPTIONAL
,
864 OUT UINT8
*Vector OPTIONAL
869 LOCAL_APIC_LVT_TIMER LvtTimer
;
872 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
874 // This bit will be 1, if local APIC is software enabled.
876 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET
) & BIT8
) != 0);
878 if (DivideValue
!= NULL
) {
879 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
880 Divisor
= Dcr
.Bits
.DivideValue1
| (Dcr
.Bits
.DivideValue2
<< 2);
881 Divisor
= (Divisor
+ 1) & 0x7;
882 *DivideValue
= ((UINTN
)1) << Divisor
;
885 if (PeriodicMode
!= NULL
|| Vector
!= NULL
) {
886 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
887 if (PeriodicMode
!= NULL
) {
888 if (LvtTimer
.Bits
.TimerMode
== 1) {
889 *PeriodicMode
= TRUE
;
891 *PeriodicMode
= FALSE
;
894 if (Vector
!= NULL
) {
895 *Vector
= (UINT8
) LvtTimer
.Bits
.Vector
;
901 Enable the local APIC timer interrupt.
905 EnableApicTimerInterrupt (
909 LOCAL_APIC_LVT_TIMER LvtTimer
;
911 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
912 LvtTimer
.Bits
.Mask
= 0;
913 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
917 Disable the local APIC timer interrupt.
921 DisableApicTimerInterrupt (
925 LOCAL_APIC_LVT_TIMER LvtTimer
;
927 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
928 LvtTimer
.Bits
.Mask
= 1;
929 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
933 Get the local APIC timer interrupt state.
935 @retval TRUE The local APIC timer interrupt is enabled.
936 @retval FALSE The local APIC timer interrupt is disabled.
940 GetApicTimerInterruptState (
944 LOCAL_APIC_LVT_TIMER LvtTimer
;
946 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
947 return (BOOLEAN
)(LvtTimer
.Bits
.Mask
== 0);
951 Send EOI to the local APIC.
959 WriteLocalApicReg (XAPIC_EOI_OFFSET
, 0);
963 Get the 32-bit address that a device should use to send a Message Signaled
964 Interrupt (MSI) to the Local APIC of the currently executing processor.
966 @return 32-bit address used to send an MSI to the Local APIC.
974 LOCAL_APIC_MSI_ADDRESS MsiAddress
;
977 // Return address for an MSI interrupt to be delivered only to the APIC ID
978 // of the currently executing processor.
980 MsiAddress
.Uint32
= 0;
981 MsiAddress
.Bits
.BaseAddress
= 0xFEE;
982 MsiAddress
.Bits
.DestinationId
= GetApicId ();
983 return MsiAddress
.Uint32
;
987 Get the 64-bit data value that a device should use to send a Message Signaled
988 Interrupt (MSI) to the Local APIC of the currently executing processor.
990 If Vector is not in range 0x10..0xFE, then ASSERT().
991 If DeliveryMode is not supported, then ASSERT().
993 @param Vector The 8-bit interrupt vector associated with the MSI.
994 Must be in the range 0x10..0xFE
995 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
996 is handled. The only supported values are:
997 0: LOCAL_APIC_DELIVERY_MODE_FIXED
998 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
999 2: LOCAL_APIC_DELIVERY_MODE_SMI
1000 4: LOCAL_APIC_DELIVERY_MODE_NMI
1001 5: LOCAL_APIC_DELIVERY_MODE_INIT
1002 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
1004 @param LevelTriggered TRUE specifies a level triggered interrupt.
1005 FALSE specifies an edge triggered interrupt.
1006 @param AssertionLevel Ignored if LevelTriggered is FALSE.
1007 TRUE specifies a level triggered interrupt that active
1008 when the interrupt line is asserted.
1009 FALSE specifies a level triggered interrupt that active
1010 when the interrupt line is deasserted.
1012 @return 64-bit data value used to send an MSI to the Local APIC.
1018 IN UINTN DeliveryMode
,
1019 IN BOOLEAN LevelTriggered
,
1020 IN BOOLEAN AssertionLevel
1023 LOCAL_APIC_MSI_DATA MsiData
;
1025 ASSERT (Vector
>= 0x10 && Vector
<= 0xFE);
1026 ASSERT (DeliveryMode
< 8 && DeliveryMode
!= 6 && DeliveryMode
!= 3);
1029 MsiData
.Bits
.Vector
= Vector
;
1030 MsiData
.Bits
.DeliveryMode
= (UINT32
)DeliveryMode
;
1031 if (LevelTriggered
) {
1032 MsiData
.Bits
.TriggerMode
= 1;
1033 if (AssertionLevel
) {
1034 MsiData
.Bits
.Level
= 1;
1037 return MsiData
.Uint64
;