1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>
3 ; SPDX-License-Identifier: BSD-2-Clause-Patent
7 ; ExceptionHandlerAsm.Asm
11 ; x64 CPU Exception Handler
15 ;------------------------------------------------------------------------------
18 ; CommonExceptionHandler()
21 %define VC_EXCEPTION 29
23 extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions
24 extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag
25 extern ASM_PFX(CommonExceptionHandler)
34 ; Generate 32 IDT vectors.
35 ; 32 IDT vectors are enough because interrupts (32+) are not enabled in SEC and PEI phase.
41 mov rax, ASM_PFX(CommonInterruptEntry)
43 %assign Vector Vector+1
47 HookAfterStubHeaderBegin:
50 db 0 ; 0 will be fixed
52 mov rax, HookAfterStubHeaderEnd
54 HookAfterStubHeaderEnd:
56 and sp, 0xfff0 ; make sure 16-byte aligned for exception context
57 sub rsp, 0x18 ; reserve room for filling exception data later
60 bt [ASM_PFX(mErrorCodeFlag)], ecx
62 push qword [rsp] ; push additional rcx to make stack alignment
64 xchg rcx, [rsp] ; restore rcx, save Exception Number in stack
65 push qword [rax] ; push rax into stack to keep code consistence
67 ;---------------------------------------;
68 ; CommonInterruptEntry ;
69 ;---------------------------------------;
70 ; The follow algorithm is used for the common interrupt routine.
71 ; Entry from each interrupt with a push eax and eax=interrupt number
72 ; Stack frame would be as follows as specified in IA32 manuals:
74 ; +---------------------+ <-- 16-byte aligned ensured by processor
76 ; +---------------------+
78 ; +---------------------+
80 ; +---------------------+
82 ; +---------------------+
84 ; +---------------------+
86 ; +---------------------+
88 ; +---------------------+
90 ; +---------------------+ <-- RBP, 16-byte aligned
91 ; The follow algorithm is used for the common interrupt routine.
92 global ASM_PFX(CommonInterruptEntry)
93 ASM_PFX(CommonInterruptEntry):
97 ; All interrupt handlers are invoked through interrupt gates, so
98 ; IF flag automatically cleared at the entry point
100 xchg rcx, [rsp] ; Save rcx into stack and save vector number into rcx
102 cmp ecx, 32 ; Intel reserved vector for exceptions?
104 bt [ASM_PFX(mErrorCodeFlag)], ecx
110 ; Push a dummy error code on the stack
111 ; to maintain coherent stack map
114 mov qword [rsp + 8], 0
118 push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
119 push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
123 ; +---------------------+ <-- 16-byte aligned ensured by processor
125 ; +---------------------+
127 ; +---------------------+
129 ; +---------------------+
131 ; +---------------------+
133 ; +---------------------+
135 ; +---------------------+
136 ; + RCX / Vector Number +
137 ; +---------------------+
139 ; +---------------------+ <-- RBP, 16-byte aligned
143 ; Since here the stack pointer is 16-byte aligned, so
144 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
148 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
149 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
159 push qword [rbp + 8] ; RCX
162 push qword [rbp + 48] ; RSP
163 push qword [rbp] ; RBP
167 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
168 movzx rax, word [rbp + 56]
170 movzx rax, word [rbp + 32]
181 mov [rbp + 8], rcx ; save vector number
184 push qword [rbp + 24]
186 ;; UINT64 Gdtr[2], Idtr[2];
192 mov rax, qword [rsp + 2]
194 mov word [rsp + 8], bx
201 mov rax, qword [rsp + 2]
203 mov word [rsp + 8], bx
213 push qword [rbp + 40]
215 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
231 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
232 cmp qword [rbp + 8], VC_EXCEPTION
233 je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored
250 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid exception recursion
260 ;; FX_SAVE_STATE_X64 FxSaveState;
265 ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
268 ;; UINT32 ExceptionData;
269 push qword [rbp + 16]
271 ;; Prepare parameter and call
275 ; Per X64 calling convention, allocate maximum parameter stack space
276 ; and make sure RSP is 16-byte aligned
279 mov rax, ASM_PFX(CommonExceptionHandler)
284 ;; UINT64 ExceptionData;
287 ;; FX_SAVE_STATE_X64 FxSaveState;
293 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
294 ;; Skip restoration of DRx registers to support in-circuit emualators
295 ;; or debuggers set breakpoint in interrupt/exception context
298 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
301 add rsp, 8 ; not for Cr1
315 ;; UINT64 Gdtr[2], Idtr[2];
316 ;; Best not let anyone mess with these particular registers...
322 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
324 ; mov gs, rax ; not for gs
326 ; mov fs, rax ; not for fs
327 ; (X64 will not use fs and gs, so we do not restore it)
332 pop qword [rbp + 32] ; for cs
333 pop qword [rbp + 56] ; for ss
335 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
336 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
339 add rsp, 8 ; not for rbp
340 pop qword [rbp + 48] ; for rsp
357 cmp qword [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
359 cmp qword [rsp - 40], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
367 cmp qword [ASM_PFX(mDoFarReturnFlag)], 0 ; Check if need to do far return instead of IRET
370 mov rax, rsp ; save old RSP to rax
371 mov rsp, [rsp + 0x20]
372 push qword [rax + 0x10] ; save CS in new location
373 push qword [rax + 0x8] ; save EIP in new location
374 push qword [rax + 0x18] ; save EFLAGS in new location
375 mov rax, [rax] ; restore rax
376 popfq ; restore EFLAGS
381 ;-------------------------------------------------------------------------------------
382 ; GetTemplateAddressMap (&AddressMap);
383 ;-------------------------------------------------------------------------------------
384 ; comments here for definition of address map
385 global ASM_PFX(AsmGetTemplateAddressMap)
386 ASM_PFX(AsmGetTemplateAddressMap):
387 mov rax, AsmIdtVectorBegin
389 mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
390 mov rax, HookAfterStubHeaderBegin
391 mov qword [rcx + 0x10], rax
394 ;-------------------------------------------------------------------------------------
395 ; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
396 ;-------------------------------------------------------------------------------------
397 global ASM_PFX(AsmVectorNumFixup)
398 ASM_PFX(AsmVectorNumFixup):
400 mov [rcx + (@VectorNum - HookAfterStubHeaderBegin)], al