2 The CPU specific programming for PiSmmCpuDxeSmm module.
4 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #include <Library/SmmCpuFeaturesLib.h>
11 #include <Library/BaseLib.h>
12 #include <Library/MtrrLib.h>
13 #include <Library/PcdLib.h>
14 #include <Library/MemoryAllocationLib.h>
15 #include <Library/DebugLib.h>
16 #include <Register/Cpuid.h>
17 #include <Register/SmramSaveStateMap.h>
20 // Machine Specific Registers (MSRs)
22 #define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE
23 #define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A
24 #define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2
25 #define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3
26 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0
27 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
28 #define EFI_MSR_SMRR_MASK 0xFFFFF000
29 #define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
30 #define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0
33 // MSRs required for configuration of SMM Code Access Check
35 #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
36 #define SMM_CODE_ACCESS_CHK_BIT BIT58
39 Internal worker function that is called to complete CPU initialization at the
40 end of SmmCpuFeaturesInitializeProcessor().
44 FinishSmmCpuFeaturesInitializeProcessor (
49 // Set default value to assume SMRR is not supported
51 BOOLEAN mSmrrSupported
= FALSE
;
54 // Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
56 BOOLEAN mSmmFeatureControlSupported
= FALSE
;
59 // Set default value to assume IA-32 Architectural MSRs are used
61 UINT32 mSmrrPhysBaseMsr
= SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE
;
62 UINT32 mSmrrPhysMaskMsr
= SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK
;
65 // Set default value to assume MTRRs need to be configured on each SMI
67 BOOLEAN mNeedConfigureMtrrs
= TRUE
;
70 // Array for state of SMRR enable on all CPUs
72 BOOLEAN
*mSmrrEnabled
;
75 The constructor function
77 @param[in] ImageHandle The firmware allocated handle for the EFI image.
78 @param[in] SystemTable A pointer to the EFI System Table.
80 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
85 SmmCpuFeaturesLibConstructor (
86 IN EFI_HANDLE ImageHandle
,
87 IN EFI_SYSTEM_TABLE
*SystemTable
96 // Retrieve CPU Family and Model
98 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, &RegEdx
);
99 FamilyId
= (RegEax
>> 8) & 0xf;
100 ModelId
= (RegEax
>> 4) & 0xf;
101 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
102 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
106 // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
108 if ((RegEdx
& BIT12
) != 0) {
110 // Check MTRR_CAP MSR bit 11 for SMRR support
112 if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP
) & BIT11
) != 0) {
113 mSmrrSupported
= TRUE
;
118 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
119 // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
121 // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
122 // SMRR Physical Base and SMM Physical Mask MSRs are not available.
124 if (FamilyId
== 0x06) {
125 if (ModelId
== 0x1C || ModelId
== 0x26 || ModelId
== 0x27 || ModelId
== 0x35 || ModelId
== 0x36) {
126 mSmrrSupported
= FALSE
;
131 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
132 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
134 // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
135 // Processor Family MSRs
137 if (FamilyId
== 0x06) {
138 if (ModelId
== 0x17 || ModelId
== 0x0f) {
139 mSmrrPhysBaseMsr
= SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE
;
140 mSmrrPhysMaskMsr
= SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK
;
145 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
146 // Volume 3C, Section 34.4.2 SMRAM Caching
147 // An IA-32 processor does not automatically write back and invalidate its
148 // caches before entering SMM or before exiting SMM. Because of this behavior,
149 // care must be taken in the placement of the SMRAM in system memory and in
150 // the caching of the SMRAM to prevent cache incoherence when switching back
151 // and forth between SMM and protected mode operation.
153 // An IA-32 processor is a processor that does not support the Intel 64
154 // Architecture. Support for the Intel 64 Architecture can be detected from
155 // CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]
157 // If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,
158 // so caches are flushed on SMI entry and SMI exit, the interrupted code
159 // MTRRs are saved/restored, and MTRRs for SMM are loaded.
161 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
162 if (RegEax
>= CPUID_EXTENDED_CPU_SIG
) {
163 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
164 if ((RegEdx
& BIT29
) != 0) {
165 mNeedConfigureMtrrs
= FALSE
;
170 // Allocate array for state of SMRR enable on all CPUs
172 mSmrrEnabled
= (BOOLEAN
*)AllocatePool (sizeof (BOOLEAN
) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
173 ASSERT (mSmrrEnabled
!= NULL
);
179 Called during the very first SMI into System Management Mode to initialize
180 CPU features, including SMBASE, for the currently executing CPU. Since this
181 is the first SMI, the SMRAM Save State Map is at the default address of
182 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
183 CPU is specified by CpuIndex and CpuIndex can be used to access information
184 about the currently executing CPU in the ProcessorInfo array and the
185 HotPlugCpuData data structure.
187 @param[in] CpuIndex The index of the CPU to initialize. The value
188 must be between 0 and the NumberOfCpus field in
189 the System Management System Table (SMST).
190 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
191 was elected as monarch during System Management
193 FALSE if the CpuIndex is not the index of the CPU
194 that was elected as monarch during System
195 Management Mode initialization.
196 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
197 structures. ProcessorInfo[CpuIndex] contains the
198 information for the currently executing CPU.
199 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
200 contains the ApidId and SmBase arrays.
204 SmmCpuFeaturesInitializeProcessor (
206 IN BOOLEAN IsMonarch
,
207 IN EFI_PROCESSOR_INFORMATION
*ProcessorInfo
,
208 IN CPU_HOT_PLUG_DATA
*CpuHotPlugData
211 SMRAM_SAVE_STATE_MAP
*CpuState
;
212 UINT64 FeatureControl
;
221 CpuState
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
222 CpuState
->x86
.SMBASE
= (UINT32
)CpuHotPlugData
->SmBase
[CpuIndex
];
225 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
226 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
228 // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then
229 // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before
230 // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
231 // is set, then the MSR is locked and can not be modified.
233 if (mSmrrSupported
&& mSmrrPhysBaseMsr
== SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE
) {
234 FeatureControl
= AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL
);
235 if ((FeatureControl
& BIT3
) == 0) {
236 if ((FeatureControl
& BIT0
) == 0) {
237 AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL
, FeatureControl
| BIT3
);
239 mSmrrSupported
= FALSE
;
245 // If SMRR is supported, then program SMRR base/mask MSRs.
246 // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
247 // The code that initializes SMM environment is running in normal mode
248 // from SMRAM region. If SMRR is enabled here, then the SMRAM region
249 // is protected and the normal mode code execution will fail.
251 if (mSmrrSupported
) {
253 // SMRR size cannot be less than 4-KBytes
254 // SMRR size must be of length 2^n
255 // SMRR base alignment cannot be less than SMRR length
257 if ((CpuHotPlugData
->SmrrSize
< SIZE_4KB
) ||
258 (CpuHotPlugData
->SmrrSize
!= GetPowerOfTwo32 (CpuHotPlugData
->SmrrSize
)) ||
259 ((CpuHotPlugData
->SmrrBase
& ~(CpuHotPlugData
->SmrrSize
- 1)) != CpuHotPlugData
->SmrrBase
)) {
261 // Print message and halt if CPU is Monarch
264 DEBUG ((DEBUG_ERROR
, "SMM Base/Size does not meet alignment/size requirement!\n"));
268 AsmWriteMsr64 (mSmrrPhysBaseMsr
, CpuHotPlugData
->SmrrBase
| MTRR_CACHE_WRITE_BACK
);
269 AsmWriteMsr64 (mSmrrPhysMaskMsr
, (~(CpuHotPlugData
->SmrrSize
- 1) & EFI_MSR_SMRR_MASK
));
270 mSmrrEnabled
[CpuIndex
] = FALSE
;
275 // Retrieve CPU Family and Model
277 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, &RegEdx
);
278 FamilyId
= (RegEax
>> 8) & 0xf;
279 ModelId
= (RegEax
>> 4) & 0xf;
280 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
281 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
285 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
286 // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)
289 // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation
290 // Intel(R) Core(TM) Processor Family MSRs.
292 if (FamilyId
== 0x06) {
293 if (ModelId
== 0x3C || ModelId
== 0x45 || ModelId
== 0x46 ||
294 ModelId
== 0x3D || ModelId
== 0x47 || ModelId
== 0x4E || ModelId
== 0x4F ||
295 ModelId
== 0x3F || ModelId
== 0x56 || ModelId
== 0x57 || ModelId
== 0x5C) {
297 // Check to see if the CPU supports the SMM Code Access Check feature
298 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
300 if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) != 0) {
301 mSmmFeatureControlSupported
= TRUE
;
307 // Call internal worker function that completes the CPU initialization
309 FinishSmmCpuFeaturesInitializeProcessor ();
313 This function updates the SMRAM save state on the currently executing CPU
314 to resume execution at a specific address after an RSM instruction. This
315 function must evaluate the SMRAM save state to determine the execution mode
316 the RSM instruction resumes and update the resume execution address with
317 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
318 flag in the SMRAM save state must always be cleared. This function returns
319 the value of the instruction pointer from the SMRAM save state that was
320 replaced. If this function returns 0, then the SMRAM save state was not
323 This function is called during the very first SMI on each CPU after
324 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
325 to signal that the SMBASE of each CPU has been updated before the default
326 SMBASE address is used for the first SMI to the next CPU.
328 @param[in] CpuIndex The index of the CPU to hook. The value
329 must be between 0 and the NumberOfCpus
330 field in the System Management System Table
332 @param[in] CpuState Pointer to SMRAM Save State Map for the
333 currently executing CPU.
334 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
335 32-bit execution mode from 64-bit SMM.
336 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
337 same execution mode as SMM.
339 @retval 0 This function did modify the SMRAM save state.
340 @retval > 0 The original instruction pointer value from the SMRAM save state
341 before it was replaced.
345 SmmCpuFeaturesHookReturnFromSmm (
347 IN SMRAM_SAVE_STATE_MAP
*CpuState
,
348 IN UINT64 NewInstructionPointer32
,
349 IN UINT64 NewInstructionPointer
356 Hook point in normal execution mode that allows the one CPU that was elected
357 as monarch during System Management Mode initialization to perform additional
358 initialization actions immediately after all of the CPUs have processed their
359 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
360 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
364 SmmCpuFeaturesSmmRelocationComplete (
371 Determines if MTRR registers must be configured to set SMRAM cache-ability
372 when executing in System Management Mode.
374 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
375 @retval FALSE MTRR registers do not need to be configured to set SMRAM
380 SmmCpuFeaturesNeedConfigureMtrrs (
384 return mNeedConfigureMtrrs
;
388 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
393 SmmCpuFeaturesDisableSmrr (
397 if (mSmrrSupported
&& mNeedConfigureMtrrs
) {
398 AsmWriteMsr64 (mSmrrPhysMaskMsr
, AsmReadMsr64(mSmrrPhysMaskMsr
) & ~EFI_MSR_SMRR_PHYS_MASK_VALID
);
403 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
408 SmmCpuFeaturesReenableSmrr (
412 if (mSmrrSupported
&& mNeedConfigureMtrrs
) {
413 AsmWriteMsr64 (mSmrrPhysMaskMsr
, AsmReadMsr64(mSmrrPhysMaskMsr
) | EFI_MSR_SMRR_PHYS_MASK_VALID
);
418 Processor specific hook point each time a CPU enters System Management Mode.
420 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
421 must be between 0 and the NumberOfCpus field in the
422 System Management System Table (SMST).
426 SmmCpuFeaturesRendezvousEntry (
431 // If SMRR is supported and this is the first normal SMI, then enable SMRR
433 if (mSmrrSupported
&& !mSmrrEnabled
[CpuIndex
]) {
434 AsmWriteMsr64 (mSmrrPhysMaskMsr
, AsmReadMsr64 (mSmrrPhysMaskMsr
) | EFI_MSR_SMRR_PHYS_MASK_VALID
);
435 mSmrrEnabled
[CpuIndex
] = TRUE
;
440 Processor specific hook point each time a CPU exits System Management Mode.
442 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must
443 be between 0 and the NumberOfCpus field in the System
444 Management System Table (SMST).
448 SmmCpuFeaturesRendezvousExit (
455 Check to see if an SMM register is supported by a specified CPU.
457 @param[in] CpuIndex The index of the CPU to check for SMM register support.
458 The value must be between 0 and the NumberOfCpus field
459 in the System Management System Table (SMST).
460 @param[in] RegName Identifies the SMM register to check for support.
462 @retval TRUE The SMM register specified by RegName is supported by the CPU
463 specified by CpuIndex.
464 @retval FALSE The SMM register specified by RegName is not supported by the
465 CPU specified by CpuIndex.
469 SmmCpuFeaturesIsSmmRegisterSupported (
471 IN SMM_REG_NAME RegName
474 if (mSmmFeatureControlSupported
&& RegName
== SmmRegFeatureControl
) {
481 Returns the current value of the SMM register for the specified CPU.
482 If the SMM register is not supported, then 0 is returned.
484 @param[in] CpuIndex The index of the CPU to read the SMM register. The
485 value must be between 0 and the NumberOfCpus field in
486 the System Management System Table (SMST).
487 @param[in] RegName Identifies the SMM register to read.
489 @return The value of the SMM register specified by RegName from the CPU
490 specified by CpuIndex.
494 SmmCpuFeaturesGetSmmRegister (
496 IN SMM_REG_NAME RegName
499 if (mSmmFeatureControlSupported
&& RegName
== SmmRegFeatureControl
) {
500 return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL
);
506 Sets the value of an SMM register on a specified CPU.
507 If the SMM register is not supported, then no action is performed.
509 @param[in] CpuIndex The index of the CPU to write the SMM register. The
510 value must be between 0 and the NumberOfCpus field in
511 the System Management System Table (SMST).
512 @param[in] RegName Identifies the SMM register to write.
513 registers are read-only.
514 @param[in] Value The value to write to the SMM register.
518 SmmCpuFeaturesSetSmmRegister (
520 IN SMM_REG_NAME RegName
,
524 if (mSmmFeatureControlSupported
&& RegName
== SmmRegFeatureControl
) {
525 AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL
, Value
);
530 Read an SMM Save State register on the target processor. If this function
531 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
532 SMM Save Sate register.
534 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
535 value must be between 0 and the NumberOfCpus field in
536 the System Management System Table (SMST).
537 @param[in] Register The SMM Save State register to read.
538 @param[in] Width The number of bytes to read from the CPU save state.
539 @param[out] Buffer Upon return, this holds the CPU register value read
542 @retval EFI_SUCCESS The register was read from Save State.
543 @retval EFI_INVALID_PARAMTER Buffer is NULL.
544 @retval EFI_UNSUPPORTED This function does not support reading Register.
549 SmmCpuFeaturesReadSaveStateRegister (
551 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
556 return EFI_UNSUPPORTED
;
560 Writes an SMM Save State register on the target processor. If this function
561 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
562 SMM Save Sate register.
564 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
565 value must be between 0 and the NumberOfCpus field in
566 the System Management System Table (SMST).
567 @param[in] Register The SMM Save State register to write.
568 @param[in] Width The number of bytes to write to the CPU save state.
569 @param[in] Buffer Upon entry, this holds the new CPU register value.
571 @retval EFI_SUCCESS The register was written to Save State.
572 @retval EFI_INVALID_PARAMTER Buffer is NULL.
573 @retval EFI_UNSUPPORTED This function does not support writing Register.
577 SmmCpuFeaturesWriteSaveStateRegister (
579 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
581 IN CONST VOID
*Buffer
584 return EFI_UNSUPPORTED
;
588 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
589 notification is completely processed.
593 SmmCpuFeaturesCompleteSmmReadyToLock (
600 This API provides a method for a CPU to allocate a specific region for storing page tables.
602 This API can be called more once to allocate memory for page tables.
604 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
605 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
606 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
609 This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.
611 @param Pages The number of 4 KB pages to allocate.
613 @return A pointer to the allocated buffer for page tables.
614 @retval NULL Fail to allocate a specific region for storing page tables,
615 Or there is no preference on where the page tables are allocated in SMRAM.
620 SmmCpuFeaturesAllocatePageTableMemory (