UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   4 ;
   5 ; Module Name:
   6 ;
   7 ;   SmiException.nasm
   8 ;
   9 ; Abstract:
  10 ;
  11 ;   Exception handlers used in SM mode
  12 ;
  13 ;-------------------------------------------------------------------------------
  14
  15 %include "StuffRsbNasm.inc"
  16
  17 global  ASM_PFX(gcStmPsd)
  18
  19 extern  ASM_PFX(SmmStmExceptionHandler)
  20 extern  ASM_PFX(SmmStmSetup)
  21 extern  ASM_PFX(SmmStmTeardown)
  22 extern  ASM_PFX(gStmXdSupported)
  23 extern  ASM_PFX(gStmSmiHandlerIdtr)
  24
  25 %define MSR_IA32_MISC_ENABLE 0x1A0
  26 %define MSR_EFER      0xc0000080
  27 %define MSR_EFER_XD   0x800
  28
  29 CODE_SEL          equ 0x38
  30 DATA_SEL          equ 0x20
  31 TR_SEL            equ 0x40
  32
  33     SECTION .data
  34
  35 ;
  36 ; This structure serves as a template for all processors.
  37 ;
  38 ASM_PFX(gcStmPsd):
  39             DB      'TXTPSSIG'
  40             DW      PSD_SIZE
  41             DW      1              ; Version
  42             DD      0              ; LocalApicId
  43             DB      0x0F           ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
  44             DB      0              ; BIOS to STM
  45             DB      0              ; STM to BIOS
  46             DB      0
  47             DW      CODE_SEL
  48             DW      DATA_SEL
  49             DW      DATA_SEL
  50             DW      DATA_SEL
  51             DW      TR_SEL
  52             DW      0
  53             DQ      0              ; SmmCr3
  54             DQ      ASM_PFX(OnStmSetup)
  55             DQ      ASM_PFX(OnStmTeardown)
  56             DQ      0              ; SmmSmiHandlerRip - SMM guest entrypoint
  57             DQ      0              ; SmmSmiHandlerRsp
  58             DQ      0
  59             DD      0
  60             DD      0x80010100     ; RequiredStmSmmRevId
  61             DQ      ASM_PFX(OnException)
  62             DQ      0              ; ExceptionStack
  63             DW      DATA_SEL
  64             DW      0x01F          ; ExceptionFilter
  65             DD      0
  66             DQ      0
  67             DQ      0              ; BiosHwResourceRequirementsPtr
  68             DQ      0              ; AcpiRsdp
  69             DB      0              ; PhysicalAddressBits
  70 PSD_SIZE  equ $ -   ASM_PFX(gcStmPsd)
  71
  72     DEFAULT REL
  73     SECTION .text
  74 ;------------------------------------------------------------------------------
  75 ; SMM Exception handlers
  76 ;------------------------------------------------------------------------------
  77 global ASM_PFX(OnException)
  78 ASM_PFX(OnException):
  79     mov  rcx, rsp
  80     add  rsp, -0x28
  81     call ASM_PFX(SmmStmExceptionHandler)
  82     add  rsp, 0x28
  83     mov  ebx, eax
  84     mov  eax, 4
  85     vmcall
  86     jmp $
  87
  88 global ASM_PFX(OnStmSetup)
  89 ASM_PFX(OnStmSetup):
  90 ;
  91 ; Check XD disable bit
  92 ;
  93     xor     r8, r8
  94     lea     rax, [ASM_PFX(gStmXdSupported)]
  95     mov     al, [rax]
  96     cmp     al, 0
  97     jz      @StmXdDone1
  98     mov     ecx, MSR_IA32_MISC_ENABLE
  99     rdmsr
 100     mov     r8, rdx                    ; save MSR_IA32_MISC_ENABLE[63-32]
 101     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 102     jz      .01
 103     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 104     wrmsr
 105 .01:
 106     mov     ecx, MSR_EFER
 107     rdmsr
 108     or      ax, MSR_EFER_XD            ; enable NXE
 109     wrmsr
 110 @StmXdDone1:
 111     push    r8
 112
 113   add  rsp, -0x20
 114   call ASM_PFX(SmmStmSetup)
 115   add  rsp, 0x20
 116
 117     lea     rax, [ASM_PFX(gStmXdSupported)]
 118     mov     al, [rax]
 119     cmp     al, 0
 120     jz      .11
 121     pop     rdx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 122     test    edx, BIT2
 123     jz      .11
 124     mov     ecx, MSR_IA32_MISC_ENABLE
 125     rdmsr
 126     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 127     wrmsr
 128
 129 .11:
 130     StuffRsb64
 131     rsm
 132
 133 global ASM_PFX(OnStmTeardown)
 134 ASM_PFX(OnStmTeardown):
 135 ;
 136 ; Check XD disable bit
 137 ;
 138     xor     r8, r8
 139     lea     rax, [ASM_PFX(gStmXdSupported)]
 140     mov     al, [rax]
 141     cmp     al, 0
 142     jz      @StmXdDone2
 143     mov     ecx, MSR_IA32_MISC_ENABLE
 144     rdmsr
 145     mov     r8, rdx                    ; save MSR_IA32_MISC_ENABLE[63-32]
 146     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 147     jz      .02
 148     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 149     wrmsr
 150 .02:
 151     mov     ecx, MSR_EFER
 152     rdmsr
 153     or      ax, MSR_EFER_XD            ; enable NXE
 154     wrmsr
 155 @StmXdDone2:
 156     push    r8
 157
 158   add  rsp, -0x20
 159   call ASM_PFX(SmmStmTeardown)
 160   add  rsp, 0x20
 161
 162     lea     rax, [ASM_PFX(gStmXdSupported)]
 163     mov     al, [rax]
 164     cmp     al, 0
 165     jz      .12
 166     pop     rdx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 167     test    edx, BIT2
 168     jz      .12
 169     mov     ecx, MSR_IA32_MISC_ENABLE
 170     rdmsr
 171     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 172     wrmsr
 173
 174 .12:
 175     StuffRsb64
 176     rsm