1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Code template of the SMI handler for a particular processor
19 ;-------------------------------------------------------------------------------
33 PROTECT_MODE_CS EQU 08h
34 PROTECT_MODE_DS EQU 20h
38 CpuSmmDebugEntry PROTO C
39 CpuSmmDebugExit PROTO C
41 EXTERNDEF gcSmiHandlerTemplate:BYTE
42 EXTERNDEF gcSmiHandlerSize:WORD
43 EXTERNDEF gSmiCr3:DWORD
44 EXTERNDEF gSmiStack:DWORD
45 EXTERNDEF gSmbase:DWORD
46 EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
47 EXTERNDEF gSmiHandlerIdtr:FWORD
51 gcSmiHandlerTemplate LABEL BYTE
54 DB 0bbh ; mov bx, imm16
55 DW offset _GdtDesc - _SmiEntryPoint + 8000h
56 DB 2eh, 0a1h ; mov ax, cs:[offset16]
57 DW DSC_OFFSET + DSC_GDTSIZ
59 mov cs:[edi], eax ; mov cs:[bx], ax
60 DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
61 DW DSC_OFFSET + DSC_GDTPTR
62 mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
63 mov bp, ax ; ebp = GDT base
65 lgdt fword ptr cs:[edi] ; lgdt fword ptr cs:[bx]
66 ; Patch ProtectedMode Segment
67 DB 0b8h ; mov ax, imm16
68 DW PROTECT_MODE_CS ; set AX for segment directly
69 mov cs:[edi - 2], eax ; mov cs:[bx - 2], ax
70 ; Patch ProtectedMode entry
71 DB 66h, 0bfh ; mov edi, SMBASE
74 lea ax, [edi + (@32bit - _SmiEntryPoint) + 8000h]
75 mov cs:[edi - 6], ax ; mov cs:[bx - 6], eax
88 mov ax, PROTECT_MODE_DS
94 DB 0bch ; mov esp, imm32
96 mov eax, offset gSmiHandlerIdtr
101 DB 0b8h ; mov eax, imm32
105 ; Need to test for CR4 specific bit support
108 cpuid ; use CPUID to determine if specific CR4 bits are supported
109 xor eax, eax ; Clear EAX
110 test edx, BIT2 ; Check for DE capabilities
114 test edx, BIT6 ; Check for PAE capabilities
118 test edx, BIT7 ; Check for MCE capabilities
122 test edx, BIT24 ; Check for FXSR capabilities
126 test edx, BIT25 ; Check for SSE capabilities
129 @@: ; as cr4.PGE is not set here, refresh cr3
130 mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
132 or ebx, 080010000h ; enable paging + WP
134 lea ebx, [edi + DSC_OFFSET]
135 mov ax, [ebx + DSC_DS]
137 mov ax, [ebx + DSC_OTHERSEG]
141 mov ax, [ebx + DSC_SS]
144 cmp FeaturePcdGet (PcdCpuSmmStackGuard), 0
148 mov byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag
152 ; jmp _SmiHandler ; instruction is not needed
155 mov ebx, [esp] ; CPU Index
158 mov eax, CpuSmmDebugEntry
163 mov eax, SmiRendezvous
168 mov eax, CpuSmmDebugExit
175 gcSmiHandlerSize DW $ - _SmiEntryPoint