1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Code template of the SMI handler for a particular processor
19 ;-------------------------------------------------------------------------------
21 %define MSR_IA32_MISC_ENABLE 0x1A0
22 %define MSR_EFER 0xc0000080
23 %define MSR_EFER_XD 0x800
26 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
28 %define DSC_OFFSET 0xfb00
29 %define DSC_GDTPTR 0x30
30 %define DSC_GDTSIZ 0x38
34 %define DSC_OTHERSEG 20
36 %define PROTECT_MODE_CS 0x8
37 %define PROTECT_MODE_DS 0x20
38 %define TSS_SEGMENT 0x40
40 extern ASM_PFX(SmiRendezvous)
41 extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
42 extern ASM_PFX(CpuSmmDebugEntry)
43 extern ASM_PFX(CpuSmmDebugExit)
45 global ASM_PFX(gcSmiHandlerTemplate)
46 global ASM_PFX(gcSmiHandlerSize)
47 global ASM_PFX(gPatchSmiCr3)
48 global ASM_PFX(gPatchSmiStack)
49 global ASM_PFX(gPatchSmbase)
50 extern ASM_PFX(mXdSupported)
51 global ASM_PFX(gPatchXdSupported)
52 extern ASM_PFX(gSmiHandlerIdtr)
57 ASM_PFX(gcSmiHandlerTemplate):
59 mov bx, _GdtDesc - _SmiEntryPoint + 0x8000
60 mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
63 mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
65 mov ebp, eax ; ebp = GDT base
66 o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
67 mov ax, PROTECT_MODE_CS
69 mov edi, strict dword 0 ; source operand will be patched
70 ASM_PFX(gPatchSmbase):
71 lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]
84 mov ax, PROTECT_MODE_DS
90 mov esp, strict dword 0 ; source operand will be patched
91 ASM_PFX(gPatchSmiStack):
92 mov eax, ASM_PFX(gSmiHandlerIdtr)
97 mov eax, strict dword 0 ; source operand will be patched
98 ASM_PFX(gPatchSmiCr3):
101 ; Need to test for CR4 specific bit support
104 cpuid ; use CPUID to determine if specific CR4 bits are supported
105 xor eax, eax ; Clear EAX
106 test edx, BIT2 ; Check for DE capabilities
110 test edx, BIT6 ; Check for PAE capabilities
114 test edx, BIT7 ; Check for MCE capabilities
118 test edx, BIT24 ; Check for FXSR capabilities
122 test edx, BIT25 ; Check for SSE capabilities
125 .4: ; as cr4.PGE is not set here, refresh cr3
126 mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
128 cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0
131 mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag
136 ; enable NXE if supported
137 mov al, strict byte 1 ; source operand may be patched
138 ASM_PFX(gPatchXdSupported):
142 ; Check XD disable bit
144 mov ecx, MSR_IA32_MISC_ENABLE
146 push edx ; save MSR_IA32_MISC_ENABLE[63-32]
147 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
149 and dx, 0xFFFB ; clear XD Disable bit if it is set
154 or ax, MSR_EFER_XD ; enable NXE
162 or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
164 lea ebx, [edi + DSC_OFFSET]
165 mov ax, [ebx + DSC_DS]
167 mov ax, [ebx + DSC_OTHERSEG]
171 mov ax, [ebx + DSC_SS]
174 ; jmp _SmiHandler ; instruction is not needed
176 global ASM_PFX(SmiHandler)
178 mov ebx, [esp + 4] ; CPU Index
180 mov eax, ASM_PFX(CpuSmmDebugEntry)
185 mov eax, ASM_PFX(SmiRendezvous)
190 mov eax, ASM_PFX(CpuSmmDebugExit)
194 mov eax, ASM_PFX(mXdSupported)
198 pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
201 mov ecx, MSR_IA32_MISC_ENABLE
203 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
209 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
211 global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
212 ASM_PFX(PiSmmCpuSmiEntryFixupAddress):