2 SMM MP service implementation
4 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PiSmmCpuDxeSmm.h"
18 // Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)
20 UINT64 gSmiMtrrs
[MTRR_NUMBER_OF_FIXED_MTRR
+ 2 * MTRR_NUMBER_OF_VARIABLE_MTRR
+ 1];
22 SMM_DISPATCHER_MP_SYNC_DATA
*mSmmMpSyncData
= NULL
;
23 UINTN mSmmMpSyncDataSize
;
26 Performs an atomic compare exchange operation to get semaphore.
27 The compare exchange operation must be performed using
30 @param Sem IN: 32-bit unsigned integer
31 OUT: original integer - 1
32 @return Original integer - 1
37 IN OUT
volatile UINT32
*Sem
44 } while (Value
== 0 ||
45 InterlockedCompareExchange32 (
55 Performs an atomic compare exchange operation to release semaphore.
56 The compare exchange operation must be performed using
59 @param Sem IN: 32-bit unsigned integer
60 OUT: original integer + 1
61 @return Original integer + 1
66 IN OUT
volatile UINT32
*Sem
73 } while (Value
+ 1 != 0 &&
74 InterlockedCompareExchange32 (
83 Performs an atomic compare exchange operation to lock semaphore.
84 The compare exchange operation must be performed using
87 @param Sem IN: 32-bit unsigned integer
89 @return Original integer
94 IN OUT
volatile UINT32
*Sem
101 } while (InterlockedCompareExchange32 (
109 Wait all APs to performs an atomic compare exchange operation to release semaphore.
111 @param NumberOfAPs AP number
121 BspIndex
= mSmmMpSyncData
->BspIndex
;
122 while (NumberOfAPs
-- > 0) {
123 WaitForSemaphore (&mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
128 Performs an atomic compare exchange operation to release semaphore
140 BspIndex
= mSmmMpSyncData
->BspIndex
;
141 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
142 if (Index
!= BspIndex
&& mSmmMpSyncData
->CpuData
[Index
].Present
) {
143 ReleaseSemaphore (&mSmmMpSyncData
->CpuData
[Index
].Run
);
149 Checks if all CPUs (with certain exceptions) have checked in for this SMI run
151 @param Exceptions CPU Arrival exception flags.
153 @retval TRUE if all CPUs the have checked in.
154 @retval FALSE if at least one Normal AP hasn't checked in.
158 AllCpusInSmmWithExceptions (
159 SMM_CPU_ARRIVAL_EXCEPTIONS Exceptions
163 SMM_CPU_DATA_BLOCK
*CpuData
;
164 EFI_PROCESSOR_INFORMATION
*ProcessorInfo
;
166 ASSERT (mSmmMpSyncData
->Counter
<= mNumberOfCpus
);
168 if (mSmmMpSyncData
->Counter
== mNumberOfCpus
) {
172 CpuData
= mSmmMpSyncData
->CpuData
;
173 ProcessorInfo
= gSmmCpuPrivate
->ProcessorInfo
;
174 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
175 if (!CpuData
[Index
].Present
&& ProcessorInfo
[Index
].ProcessorId
!= INVALID_APIC_ID
) {
176 if (((Exceptions
& ARRIVAL_EXCEPTION_DELAYED
) != 0) && SmmCpuFeaturesGetSmmRegister (Index
, SmmRegSmmDelayed
) != 0) {
179 if (((Exceptions
& ARRIVAL_EXCEPTION_BLOCKED
) != 0) && SmmCpuFeaturesGetSmmRegister (Index
, SmmRegSmmBlocked
) != 0) {
182 if (((Exceptions
& ARRIVAL_EXCEPTION_SMI_DISABLED
) != 0) && SmmCpuFeaturesGetSmmRegister (Index
, SmmRegSmmEnable
) != 0) {
195 Given timeout constraint, wait for all APs to arrive, and insure when this function returns, no AP will execute normal mode code before
196 entering SMM, except SMI disabled APs.
200 SmmWaitForApArrival (
207 ASSERT (mSmmMpSyncData
->Counter
<= mNumberOfCpus
);
210 // Platform implementor should choose a timeout value appropriately:
211 // - The timeout value should balance the SMM time constrains and the likelihood that delayed CPUs are excluded in the SMM run. Note
212 // the SMI Handlers must ALWAYS take into account the cases that not all APs are available in an SMI run.
213 // - The timeout value must, in the case of 2nd timeout, be at least long enough to give time for all APs to receive the SMI IPI
214 // and either enter SMM or buffer the SMI, to insure there is no CPU running normal mode code when SMI handling starts. This will
215 // be TRUE even if a blocked CPU is brought out of the blocked state by a normal mode CPU (before the normal mode CPU received the
216 // SMI IPI), because with a buffered SMI, and CPU will enter SMM immediately after it is brought out of the blocked state.
217 // - The timeout value must be longer than longest possible IO operation in the system
221 // Sync with APs 1st timeout
223 for (Timer
= StartSyncTimer ();
224 !IsSyncTimerTimeout (Timer
) &&
225 !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED
| ARRIVAL_EXCEPTION_SMI_DISABLED
);
231 // Not all APs have arrived, so we need 2nd round of timeout. IPIs should be sent to ALL none present APs,
233 // a) Delayed AP may have just come out of the delayed state. Blocked AP may have just been brought out of blocked state by some AP running
234 // normal mode code. These APs need to be guaranteed to have an SMI pending to insure that once they are out of delayed / blocked state, they
235 // enter SMI immediately without executing instructions in normal mode. Note traditional flow requires there are no APs doing normal mode
236 // work while SMI handling is on-going.
237 // b) As a consequence of SMI IPI sending, (spurious) SMI may occur after this SMM run.
238 // c) ** NOTE **: Use SMI disabling feature VERY CAREFULLY (if at all) for traditional flow, because a processor in SMI-disabled state
239 // will execute normal mode code, which breaks the traditional SMI handlers' assumption that no APs are doing normal
240 // mode work while SMI handling is on-going.
241 // d) We don't add code to check SMI disabling status to skip sending IPI to SMI disabled APs, because:
242 // - In traditional flow, SMI disabling is discouraged.
243 // - In relaxed flow, CheckApArrival() will check SMI disabling status before calling this function.
244 // In both cases, adding SMI-disabling checking code increases overhead.
246 if (mSmmMpSyncData
->Counter
< mNumberOfCpus
) {
248 // Send SMI IPIs to bring outside processors in
250 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
251 if (!mSmmMpSyncData
->CpuData
[Index
].Present
&& gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
!= INVALID_APIC_ID
) {
252 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
257 // Sync with APs 2nd timeout.
259 for (Timer
= StartSyncTimer ();
260 !IsSyncTimerTimeout (Timer
) &&
261 !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED
| ARRIVAL_EXCEPTION_SMI_DISABLED
);
272 Replace OS MTRR's with SMI MTRR's.
274 @param CpuIndex Processor Index
282 PROCESSOR_SMM_DESCRIPTOR
*Psd
;
284 MTRR_SETTINGS
*BiosMtrr
;
286 Psd
= (PROCESSOR_SMM_DESCRIPTOR
*)(mCpuHotPlugData
.SmBase
[CpuIndex
] + SMM_PSD_OFFSET
);
287 SmiMtrrs
= (UINT64
*)(UINTN
)Psd
->MtrrBaseMaskPtr
;
289 SmmCpuFeaturesDisableSmrr ();
292 // Replace all MTRRs registers
294 BiosMtrr
= (MTRR_SETTINGS
*)SmiMtrrs
;
295 MtrrSetAllMtrrs(BiosMtrr
);
301 @param CpuIndex BSP processor Index
302 @param SyncMode SMM MP sync mode
308 IN SMM_CPU_SYNC_MODE SyncMode
314 BOOLEAN ClearTopLevelSmiResult
;
317 ASSERT (CpuIndex
== mSmmMpSyncData
->BspIndex
);
321 // Flag BSP's presence
323 mSmmMpSyncData
->InsideSmm
= TRUE
;
326 // Initialize Debug Agent to start source level debug in BSP handler
328 InitializeDebugAgent (DEBUG_AGENT_INIT_ENTER_SMI
, NULL
, NULL
);
331 // Mark this processor's presence
333 mSmmMpSyncData
->CpuData
[CpuIndex
].Present
= TRUE
;
336 // Clear platform top level SMI status bit before calling SMI handlers. If
337 // we cleared it after SMI handlers are run, we would miss the SMI that
338 // occurs after SMI handlers are done and before SMI status bit is cleared.
340 ClearTopLevelSmiResult
= ClearTopLevelSmiStatus();
341 ASSERT (ClearTopLevelSmiResult
== TRUE
);
344 // Set running processor index
346 gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
= CpuIndex
;
349 // If Traditional Sync Mode or need to configure MTRRs: gather all available APs.
351 if (SyncMode
== SmmCpuSyncModeTradition
|| SmmCpuFeaturesNeedConfigureMtrrs()) {
354 // Wait for APs to arrive
356 SmmWaitForApArrival();
359 // Lock the counter down and retrieve the number of APs
361 mSmmMpSyncData
->AllCpusInSync
= TRUE
;
362 ApCount
= LockdownSemaphore (&mSmmMpSyncData
->Counter
) - 1;
365 // Wait for all APs to get ready for programming MTRRs
367 WaitForAllAPs (ApCount
);
369 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
371 // Signal all APs it's time for backup MTRRs
376 // WaitForSemaphore() may wait for ever if an AP happens to enter SMM at
377 // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has been set
378 // to a large enough value to avoid this situation.
379 // Note: For HT capable CPUs, threads within a core share the same set of MTRRs.
380 // We do the backup first and then set MTRR to avoid race condition for threads
383 MtrrGetAllMtrrs(&Mtrrs
);
386 // Wait for all APs to complete their MTRR saving
388 WaitForAllAPs (ApCount
);
391 // Let all processors program SMM MTRRs together
396 // WaitForSemaphore() may wait for ever if an AP happens to enter SMM at
397 // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has been set
398 // to a large enough value to avoid this situation.
400 ReplaceOSMtrrs (CpuIndex
);
403 // Wait for all APs to complete their MTRR programming
405 WaitForAllAPs (ApCount
);
410 // The BUSY lock is initialized to Acquired state
412 AcquireSpinLockOrFail (&mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
415 // Restore SMM Configuration in S3 boot path.
417 if (mRestoreSmmConfigurationInS3
) {
419 // Configure SMM Code Access Check feature if available.
421 ConfigSmmCodeAccessCheck ();
422 mRestoreSmmConfigurationInS3
= FALSE
;
426 // Invoke SMM Foundation EntryPoint with the processor information context.
428 gSmmCpuPrivate
->SmmCoreEntry (&gSmmCpuPrivate
->SmmCoreEntryContext
);
431 // Make sure all APs have completed their pending none-block tasks
433 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
434 if (Index
!= CpuIndex
&& mSmmMpSyncData
->CpuData
[Index
].Present
) {
435 AcquireSpinLock (&mSmmMpSyncData
->CpuData
[Index
].Busy
);
436 ReleaseSpinLock (&mSmmMpSyncData
->CpuData
[Index
].Busy
);;
441 // Perform the remaining tasks
443 PerformRemainingTasks ();
446 // If Relaxed-AP Sync Mode: gather all available APs after BSP SMM handlers are done, and
447 // make those APs to exit SMI synchronously. APs which arrive later will be excluded and
448 // will run through freely.
450 if (SyncMode
!= SmmCpuSyncModeTradition
&& !SmmCpuFeaturesNeedConfigureMtrrs()) {
453 // Lock the counter down and retrieve the number of APs
455 mSmmMpSyncData
->AllCpusInSync
= TRUE
;
456 ApCount
= LockdownSemaphore (&mSmmMpSyncData
->Counter
) - 1;
458 // Make sure all APs have their Present flag set
462 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
463 if (mSmmMpSyncData
->CpuData
[Index
].Present
) {
467 if (PresentCount
> ApCount
) {
474 // Notify all APs to exit
476 mSmmMpSyncData
->InsideSmm
= FALSE
;
480 // Wait for all APs to complete their pending tasks
482 WaitForAllAPs (ApCount
);
484 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
486 // Signal APs to restore MTRRs
493 SmmCpuFeaturesReenableSmrr ();
494 MtrrSetAllMtrrs(&Mtrrs
);
497 // Wait for all APs to complete MTRR programming
499 WaitForAllAPs (ApCount
);
503 // Stop source level debug in BSP handler, the code below will not be
506 InitializeDebugAgent (DEBUG_AGENT_INIT_EXIT_SMI
, NULL
, NULL
);
509 // Signal APs to Reset states/semaphore for this processor
514 // Perform pending operations for hot-plug
519 // Clear the Present flag of BSP
521 mSmmMpSyncData
->CpuData
[CpuIndex
].Present
= FALSE
;
524 // Gather APs to exit SMM synchronously. Note the Present flag is cleared by now but
525 // WaitForAllAps does not depend on the Present flag.
527 WaitForAllAPs (ApCount
);
530 // Reset BspIndex to -1, meaning BSP has not been elected.
532 if (FeaturePcdGet (PcdCpuSmmEnableBspElection
)) {
533 mSmmMpSyncData
->BspIndex
= (UINT32
)-1;
537 // Allow APs to check in from this point on
539 mSmmMpSyncData
->Counter
= 0;
540 mSmmMpSyncData
->AllCpusInSync
= FALSE
;
546 @param CpuIndex AP processor Index.
547 @param ValidSmi Indicates that current SMI is a valid SMI or not.
548 @param SyncMode SMM MP sync mode.
555 IN SMM_CPU_SYNC_MODE SyncMode
565 for (Timer
= StartSyncTimer ();
566 !IsSyncTimerTimeout (Timer
) &&
567 !mSmmMpSyncData
->InsideSmm
;
572 if (!mSmmMpSyncData
->InsideSmm
) {
574 // BSP timeout in the first round
576 if (mSmmMpSyncData
->BspIndex
!= -1) {
578 // BSP Index is known
580 BspIndex
= mSmmMpSyncData
->BspIndex
;
581 ASSERT (CpuIndex
!= BspIndex
);
584 // Send SMI IPI to bring BSP in
586 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[BspIndex
].ProcessorId
);
589 // Now clock BSP for the 2nd time
591 for (Timer
= StartSyncTimer ();
592 !IsSyncTimerTimeout (Timer
) &&
593 !mSmmMpSyncData
->InsideSmm
;
598 if (!mSmmMpSyncData
->InsideSmm
) {
600 // Give up since BSP is unable to enter SMM
601 // and signal the completion of this AP
602 WaitForSemaphore (&mSmmMpSyncData
->Counter
);
607 // Don't know BSP index. Give up without sending IPI to BSP.
609 WaitForSemaphore (&mSmmMpSyncData
->Counter
);
617 BspIndex
= mSmmMpSyncData
->BspIndex
;
618 ASSERT (CpuIndex
!= BspIndex
);
621 // Mark this processor's presence
623 mSmmMpSyncData
->CpuData
[CpuIndex
].Present
= TRUE
;
625 if (SyncMode
== SmmCpuSyncModeTradition
|| SmmCpuFeaturesNeedConfigureMtrrs()) {
627 // Notify BSP of arrival at this point
629 ReleaseSemaphore (&mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
632 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
634 // Wait for the signal from BSP to backup MTRRs
636 WaitForSemaphore (&mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
641 MtrrGetAllMtrrs(&Mtrrs
);
644 // Signal BSP the completion of this AP
646 ReleaseSemaphore (&mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
649 // Wait for BSP's signal to program MTRRs
651 WaitForSemaphore (&mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
654 // Replace OS MTRRs with SMI MTRRs
656 ReplaceOSMtrrs (CpuIndex
);
659 // Signal BSP the completion of this AP
661 ReleaseSemaphore (&mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
666 // Wait for something to happen
668 WaitForSemaphore (&mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
671 // Check if BSP wants to exit SMM
673 if (!mSmmMpSyncData
->InsideSmm
) {
678 // BUSY should be acquired by SmmStartupThisAp()
681 !AcquireSpinLockOrFail (&mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
)
685 // Invoke the scheduled procedure
687 (*mSmmMpSyncData
->CpuData
[CpuIndex
].Procedure
) (
688 (VOID
*)mSmmMpSyncData
->CpuData
[CpuIndex
].Parameter
694 ReleaseSpinLock (&mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
697 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
699 // Notify BSP the readiness of this AP to program MTRRs
701 ReleaseSemaphore (&mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
704 // Wait for the signal from BSP to program MTRRs
706 WaitForSemaphore (&mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
711 SmmCpuFeaturesReenableSmrr ();
712 MtrrSetAllMtrrs(&Mtrrs
);
716 // Notify BSP the readiness of this AP to Reset states/semaphore for this processor
718 ReleaseSemaphore (&mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
721 // Wait for the signal from BSP to Reset states/semaphore for this processor
723 WaitForSemaphore (&mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
726 // Reset states/semaphore for this processor
728 mSmmMpSyncData
->CpuData
[CpuIndex
].Present
= FALSE
;
731 // Notify BSP the readiness of this AP to exit SMM
733 ReleaseSemaphore (&mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
738 Create 4G PageTable in SMRAM.
740 @param ExtraPages Additional page numbers besides for 4G memory
741 @return PageTable Address
754 UINTN High2MBoundary
;
764 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
766 // Add one more page for known good stack, then find the lower 2MB aligned address.
768 Low2MBoundary
= (mSmmStackArrayBase
+ EFI_PAGE_SIZE
) & ~(SIZE_2MB
-1);
770 // Add two more pages for known good stack and stack guard page,
771 // then find the lower 2MB aligned address.
773 High2MBoundary
= (mSmmStackArrayEnd
- mSmmStackSize
+ EFI_PAGE_SIZE
* 2) & ~(SIZE_2MB
-1);
774 PagesNeeded
= ((High2MBoundary
- Low2MBoundary
) / SIZE_2MB
) + 1;
777 // Allocate the page table
779 PageTable
= AllocatePages (ExtraPages
+ 5 + PagesNeeded
);
780 ASSERT (PageTable
!= NULL
);
782 PageTable
= (VOID
*)((UINTN
)PageTable
+ EFI_PAGES_TO_SIZE (ExtraPages
));
783 Pte
= (UINT64
*)PageTable
;
786 // Zero out all page table entries first
788 ZeroMem (Pte
, EFI_PAGES_TO_SIZE (1));
791 // Set Page Directory Pointers
793 for (Index
= 0; Index
< 4; Index
++) {
794 Pte
[Index
] = (UINTN
)PageTable
+ EFI_PAGE_SIZE
* (Index
+ 1) + IA32_PG_P
;
796 Pte
+= EFI_PAGE_SIZE
/ sizeof (*Pte
);
799 // Fill in Page Directory Entries
801 for (Index
= 0; Index
< EFI_PAGE_SIZE
* 4 / sizeof (*Pte
); Index
++) {
802 Pte
[Index
] = (Index
<< 21) + IA32_PG_PS
+ IA32_PG_RW
+ IA32_PG_P
;
805 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
806 Pages
= (UINTN
)PageTable
+ EFI_PAGES_TO_SIZE (5);
807 GuardPage
= mSmmStackArrayBase
+ EFI_PAGE_SIZE
;
808 Pdpte
= (UINT64
*)PageTable
;
809 for (PageIndex
= Low2MBoundary
; PageIndex
<= High2MBoundary
; PageIndex
+= SIZE_2MB
) {
810 Pte
= (UINT64
*)(UINTN
)(Pdpte
[BitFieldRead32 ((UINT32
)PageIndex
, 30, 31)] & ~(EFI_PAGE_SIZE
- 1));
811 Pte
[BitFieldRead32 ((UINT32
)PageIndex
, 21, 29)] = (UINT64
)Pages
+ IA32_PG_RW
+ IA32_PG_P
;
813 // Fill in Page Table Entries
815 Pte
= (UINT64
*)Pages
;
816 PageAddress
= PageIndex
;
817 for (Index
= 0; Index
< EFI_PAGE_SIZE
/ sizeof (*Pte
); Index
++) {
818 if (PageAddress
== GuardPage
) {
820 // Mark the guard page as non-present
822 Pte
[Index
] = PageAddress
;
823 GuardPage
+= mSmmStackSize
;
824 if (GuardPage
> mSmmStackArrayEnd
) {
828 Pte
[Index
] = PageAddress
+ IA32_PG_RW
+ IA32_PG_P
;
830 PageAddress
+= EFI_PAGE_SIZE
;
832 Pages
+= EFI_PAGE_SIZE
;
836 return (UINT32
)(UINTN
)PageTable
;
840 Set memory cache ability.
842 @param PageTable PageTable Address
843 @param Address Memory Address to change cache ability
844 @param Cacheability Cache ability to set
849 IN UINT64
*PageTable
,
851 IN UINT8 Cacheability
855 VOID
*NewPageTableAddress
;
856 UINT64
*NewPageTable
;
859 ASSERT ((Address
& EFI_PAGE_MASK
) == 0);
861 if (sizeof (UINTN
) == sizeof (UINT64
)) {
862 PTIndex
= (UINTN
)RShiftU64 (Address
, 39) & 0x1ff;
863 ASSERT (PageTable
[PTIndex
] & IA32_PG_P
);
864 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & gPhyMask
);
867 PTIndex
= (UINTN
)RShiftU64 (Address
, 30) & 0x1ff;
868 ASSERT (PageTable
[PTIndex
] & IA32_PG_P
);
869 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & gPhyMask
);
872 // A perfect implementation should check the original cacheability with the
873 // one being set, and break a 2M page entry into pieces only when they
876 PTIndex
= (UINTN
)RShiftU64 (Address
, 21) & 0x1ff;
877 if ((PageTable
[PTIndex
] & IA32_PG_PS
) != 0) {
879 // Allocate a page from SMRAM
881 NewPageTableAddress
= AllocatePages (1);
882 ASSERT (NewPageTableAddress
!= NULL
);
884 NewPageTable
= (UINT64
*)NewPageTableAddress
;
886 for (Index
= 0; Index
< 0x200; Index
++) {
887 NewPageTable
[Index
] = PageTable
[PTIndex
];
888 if ((NewPageTable
[Index
] & IA32_PG_PAT_2M
) != 0) {
889 NewPageTable
[Index
] &= ~((UINT64
)IA32_PG_PAT_2M
);
890 NewPageTable
[Index
] |= (UINT64
)IA32_PG_PAT_4K
;
892 NewPageTable
[Index
] |= (UINT64
)(Index
<< EFI_PAGE_SHIFT
);
895 PageTable
[PTIndex
] = ((UINTN
)NewPageTableAddress
& gPhyMask
) | IA32_PG_P
;
898 ASSERT (PageTable
[PTIndex
] & IA32_PG_P
);
899 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & gPhyMask
);
901 PTIndex
= (UINTN
)RShiftU64 (Address
, 12) & 0x1ff;
902 ASSERT (PageTable
[PTIndex
] & IA32_PG_P
);
903 PageTable
[PTIndex
] &= ~((UINT64
)((IA32_PG_PAT_4K
| IA32_PG_CD
| IA32_PG_WT
)));
904 PageTable
[PTIndex
] |= (UINT64
)Cacheability
;
909 Schedule a procedure to run on the specified CPU.
911 @param Procedure The address of the procedure to run
912 @param CpuIndex Target CPU Index
913 @param ProcArguments The parameter to pass to the procedure
915 @retval EFI_INVALID_PARAMETER CpuNumber not valid
916 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
917 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
918 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
919 @retval EFI_SUCCESS The procedure has been successfully scheduled
925 IN EFI_AP_PROCEDURE Procedure
,
927 IN OUT VOID
*ProcArguments OPTIONAL
930 if (CpuIndex
>= gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
||
931 CpuIndex
== gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
||
932 !mSmmMpSyncData
->CpuData
[CpuIndex
].Present
||
933 gSmmCpuPrivate
->Operation
[CpuIndex
] == SmmCpuRemove
||
934 !AcquireSpinLockOrFail (&mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
)) {
935 return EFI_INVALID_PARAMETER
;
938 mSmmMpSyncData
->CpuData
[CpuIndex
].Procedure
= Procedure
;
939 mSmmMpSyncData
->CpuData
[CpuIndex
].Parameter
= ProcArguments
;
940 ReleaseSemaphore (&mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
942 if (FeaturePcdGet (PcdCpuSmmBlockStartupThisAp
)) {
943 AcquireSpinLock (&mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
944 ReleaseSpinLock (&mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
950 C function for SMI entry, each processor comes here upon SMI trigger.
952 @param CpuIndex CPU Index
964 BOOLEAN BspInProgress
;
969 // Save Cr2 because Page Fault exception in SMM may override its value
974 // Perform CPU specific entry hooks
976 SmmCpuFeaturesRendezvousEntry (CpuIndex
);
979 // Determine if this is a valid SMI
981 ValidSmi
= PlatformValidSmi();
984 // Determine if BSP has been already in progress. Note this must be checked after
985 // ValidSmi because BSP may clear a valid SMI source after checking in.
987 BspInProgress
= mSmmMpSyncData
->InsideSmm
;
989 if (!BspInProgress
&& !ValidSmi
) {
991 // If we reach here, it means when we sampled the ValidSmi flag, SMI status had not
992 // been cleared by BSP in a new SMI run (so we have a truly invalid SMI), or SMI
993 // status had been cleared by BSP and an existing SMI run has almost ended. (Note
994 // we sampled ValidSmi flag BEFORE judging BSP-in-progress status.) In both cases, there
995 // is nothing we need to do.
1000 // Signal presence of this processor
1002 if (ReleaseSemaphore (&mSmmMpSyncData
->Counter
) == 0) {
1004 // BSP has already ended the synchronization, so QUIT!!!
1008 // Wait for BSP's signal to finish SMI
1010 while (mSmmMpSyncData
->AllCpusInSync
) {
1017 // The BUSY lock is initialized to Released state.
1018 // This needs to be done early enough to be ready for BSP's SmmStartupThisAp() call.
1019 // E.g., with Relaxed AP flow, SmmStartupThisAp() may be called immediately
1020 // after AP's present flag is detected.
1022 InitializeSpinLock (&mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
1032 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1033 ActivateSmmProfile (CpuIndex
);
1036 if (BspInProgress
) {
1038 // BSP has been elected. Follow AP path, regardless of ValidSmi flag
1039 // as BSP may have cleared the SMI status
1041 APHandler (CpuIndex
, ValidSmi
, mSmmMpSyncData
->EffectiveSyncMode
);
1044 // We have a valid SMI
1051 if (FeaturePcdGet (PcdCpuSmmEnableBspElection
)) {
1052 if (!mSmmMpSyncData
->SwitchBsp
|| mSmmMpSyncData
->CandidateBsp
[CpuIndex
]) {
1054 // Call platform hook to do BSP election
1056 Status
= PlatformSmmBspElection (&IsBsp
);
1057 if (EFI_SUCCESS
== Status
) {
1059 // Platform hook determines successfully
1062 mSmmMpSyncData
->BspIndex
= (UINT32
)CpuIndex
;
1066 // Platform hook fails to determine, use default BSP election method
1068 InterlockedCompareExchange32 (
1069 (UINT32
*)&mSmmMpSyncData
->BspIndex
,
1078 // "mSmmMpSyncData->BspIndex == CpuIndex" means this is the BSP
1080 if (mSmmMpSyncData
->BspIndex
== CpuIndex
) {
1083 // Clear last request for SwitchBsp.
1085 if (mSmmMpSyncData
->SwitchBsp
) {
1086 mSmmMpSyncData
->SwitchBsp
= FALSE
;
1087 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
1088 mSmmMpSyncData
->CandidateBsp
[Index
] = FALSE
;
1092 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1093 SmmProfileRecordSmiNum ();
1097 // BSP Handler is always called with a ValidSmi == TRUE
1099 BSPHandler (CpuIndex
, mSmmMpSyncData
->EffectiveSyncMode
);
1102 APHandler (CpuIndex
, ValidSmi
, mSmmMpSyncData
->EffectiveSyncMode
);
1106 ASSERT (mSmmMpSyncData
->CpuData
[CpuIndex
].Run
== 0);
1109 // Wait for BSP's signal to exit SMI
1111 while (mSmmMpSyncData
->AllCpusInSync
) {
1117 SmmCpuFeaturesRendezvousExit (CpuIndex
);
1126 Initialize un-cacheable data.
1131 InitializeMpSyncData (
1135 if (mSmmMpSyncData
!= NULL
) {
1136 ZeroMem (mSmmMpSyncData
, mSmmMpSyncDataSize
);
1137 mSmmMpSyncData
->CpuData
= (SMM_CPU_DATA_BLOCK
*)((UINT8
*)mSmmMpSyncData
+ sizeof (SMM_DISPATCHER_MP_SYNC_DATA
));
1138 mSmmMpSyncData
->CandidateBsp
= (BOOLEAN
*)(mSmmMpSyncData
->CpuData
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
);
1139 if (FeaturePcdGet (PcdCpuSmmEnableBspElection
)) {
1141 // Enable BSP election by setting BspIndex to -1
1143 mSmmMpSyncData
->BspIndex
= (UINT32
)-1;
1145 mSmmMpSyncData
->EffectiveSyncMode
= (SMM_CPU_SYNC_MODE
) PcdGet8 (PcdCpuSmmSyncMode
);
1150 Initialize global data for MP synchronization.
1152 @param Stacks Base address of SMI stack buffer for all processors.
1153 @param StackSize Stack size for each processor in SMM.
1157 InitializeMpServiceData (
1164 MTRR_SETTINGS
*Mtrr
;
1165 PROCESSOR_SMM_DESCRIPTOR
*Psd
;
1166 UINT8
*GdtTssTables
;
1167 UINTN GdtTableStepSize
;
1170 // Initialize physical address mask
1171 // NOTE: Physical memory above virtual address limit is not supported !!!
1173 AsmCpuid (0x80000008, (UINT32
*)&Index
, NULL
, NULL
, NULL
);
1174 gPhyMask
= LShiftU64 (1, (UINT8
)Index
) - 1;
1175 gPhyMask
&= (1ull << 48) - EFI_PAGE_SIZE
;
1178 // Create page tables
1180 Cr3
= SmmInitPageTable ();
1182 GdtTssTables
= InitGdt (Cr3
, &GdtTableStepSize
);
1185 // Initialize PROCESSOR_SMM_DESCRIPTOR for each CPU
1187 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
1188 Psd
= (PROCESSOR_SMM_DESCRIPTOR
*)(VOID
*)(UINTN
)(mCpuHotPlugData
.SmBase
[Index
] + SMM_PSD_OFFSET
);
1189 CopyMem (Psd
, &gcPsd
, sizeof (gcPsd
));
1190 Psd
->SmmGdtPtr
= (UINT64
)(UINTN
)(GdtTssTables
+ GdtTableStepSize
* Index
);
1191 Psd
->SmmGdtSize
= gcSmiGdtr
.Limit
+ 1;
1194 // Install SMI handler
1198 (UINT32
)mCpuHotPlugData
.SmBase
[Index
],
1199 (VOID
*)((UINTN
)Stacks
+ (StackSize
* Index
)),
1201 (UINTN
)Psd
->SmmGdtPtr
,
1204 gcSmiIdtr
.Limit
+ 1,
1210 // Initialize mSmmMpSyncData
1212 mSmmMpSyncDataSize
= sizeof (SMM_DISPATCHER_MP_SYNC_DATA
) +
1213 (sizeof (SMM_CPU_DATA_BLOCK
) + sizeof (BOOLEAN
)) * gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
;
1214 mSmmMpSyncData
= (SMM_DISPATCHER_MP_SYNC_DATA
*) AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize
));
1215 ASSERT (mSmmMpSyncData
!= NULL
);
1216 InitializeMpSyncData ();
1219 // Record current MTRR settings
1221 ZeroMem(gSmiMtrrs
, sizeof (gSmiMtrrs
));
1222 Mtrr
= (MTRR_SETTINGS
*)gSmiMtrrs
;
1223 MtrrGetAllMtrrs (Mtrr
);
1230 Register the SMM Foundation entry point.
1232 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
1233 @param SmmEntryPoint SMM Foundation EntryPoint
1235 @retval EFI_SUCCESS Successfully to register SMM foundation entry point
1241 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL
*This
,
1242 IN EFI_SMM_ENTRY_POINT SmmEntryPoint
1246 // Record SMM Foundation EntryPoint, later invoke it on SMI entry vector.
1248 gSmmCpuPrivate
->SmmCoreEntry
= SmmEntryPoint
;