2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PiSmmCpuDxeSmm.h"
18 // SMM CPU Private Data structure that contains SMM Configuration Protocol
19 // along its supporting fields.
21 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
= {
22 SMM_CPU_PRIVATE_DATA_SIGNATURE
, // Signature
24 NULL
, // Pointer to ProcessorInfo array
25 NULL
, // Pointer to Operation array
26 NULL
, // Pointer to CpuSaveStateSize array
27 NULL
, // Pointer to CpuSaveState array
28 { {0} }, // SmmReservedSmramRegion
30 SmmStartupThisAp
, // SmmCoreEntryContext.SmmStartupThisAp
31 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
32 0, // SmmCoreEntryContext.NumberOfCpus
33 NULL
, // SmmCoreEntryContext.CpuSaveStateSize
34 NULL
// SmmCoreEntryContext.CpuSaveState
38 mSmmCpuPrivateData
.SmmReservedSmramRegion
, // SmmConfiguration.SmramReservedRegions
39 RegisterSmmEntry
// SmmConfiguration.RegisterSmmEntry
43 CPU_HOT_PLUG_DATA mCpuHotPlugData
= {
44 CPU_HOT_PLUG_DATA_REVISION_1
, // Revision
45 0, // Array Length of SmBase and APIC ID
46 NULL
, // Pointer to APIC ID array
47 NULL
, // Pointer to SMBASE array
54 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
56 SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
= &mSmmCpuPrivateData
;
59 // SMM Relocation variables
61 volatile BOOLEAN
*mRebased
;
62 volatile BOOLEAN mIsBsp
;
65 /// Handle for the SMM CPU Protocol
67 EFI_HANDLE mSmmCpuHandle
= NULL
;
70 /// SMM CPU Protocol instance
72 EFI_SMM_CPU_PROTOCOL mSmmCpu
= {
77 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable
[EXCEPTION_VECTOR_NUMBER
];
80 // SMM stack information
82 UINTN mSmmStackArrayBase
;
83 UINTN mSmmStackArrayEnd
;
87 // Pointer to structure used during S3 Resume
89 SMM_S3_RESUME_STATE
*mSmmS3ResumeState
= NULL
;
91 UINTN mMaxNumberOfCpus
= 1;
92 UINTN mNumberOfCpus
= 1;
95 // SMM ready to lock flag
97 BOOLEAN mSmmReadyToLock
= FALSE
;
100 // Global used to cache PCD for SMM Code Access Check enable
102 BOOLEAN mSmmCodeAccessCheckEnable
= FALSE
;
105 // Spin lock used to serialize setting of SMM Code Access Check feature
107 SPIN_LOCK mConfigSmmCodeAccessCheckLock
;
110 Initialize IDT to setup exception handlers for SMM.
119 BOOLEAN InterruptState
;
120 IA32_DESCRIPTOR DxeIdtr
;
122 // Disable Interrupt and save DXE IDT table
124 InterruptState
= SaveAndDisableInterrupts ();
125 AsmReadIdtr (&DxeIdtr
);
127 // Load SMM temporary IDT table
129 AsmWriteIdtr (&gcSmiIdtr
);
131 // Setup SMM default exception handlers, SMM IDT table
132 // will be updated and saved in gcSmiIdtr
134 Status
= InitializeCpuExceptionHandlers (NULL
);
135 ASSERT_EFI_ERROR (Status
);
137 // Restore DXE IDT table and CPU interrupt
139 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &DxeIdtr
);
140 SetInterruptState (InterruptState
);
144 Search module name by input IP address and output it.
146 @param CallerIpAddress Caller instruction pointer.
151 IN UINTN CallerIpAddress
155 EFI_IMAGE_DOS_HEADER
*DosHdr
;
156 EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr
;
158 UINT64 DumpIpAddress
;
163 Pe32Data
= CallerIpAddress
& ~(SIZE_4KB
- 1);
164 while (Pe32Data
!= 0) {
165 DosHdr
= (EFI_IMAGE_DOS_HEADER
*) Pe32Data
;
166 if (DosHdr
->e_magic
== EFI_IMAGE_DOS_SIGNATURE
) {
168 // DOS image header is present, so read the PE header after the DOS image header.
170 Hdr
.Pe32
= (EFI_IMAGE_NT_HEADERS32
*)(Pe32Data
+ (UINTN
) ((DosHdr
->e_lfanew
) & 0x0ffff));
172 // Make sure PE header address does not overflow and is less than the initial address.
174 if (((UINTN
)Hdr
.Pe32
> Pe32Data
) && ((UINTN
)Hdr
.Pe32
< CallerIpAddress
)) {
175 if (Hdr
.Pe32
->Signature
== EFI_IMAGE_NT_SIGNATURE
) {
185 // Not found the image base, check the previous aligned address
187 Pe32Data
-= SIZE_4KB
;
190 DumpIpAddress
= CallerIpAddress
;
191 DEBUG ((EFI_D_ERROR
, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress
));
194 PdbPointer
= PeCoffLoaderGetPdbPointer ((VOID
*) Pe32Data
);
195 if (PdbPointer
!= NULL
) {
196 DEBUG ((EFI_D_ERROR
, " in module (%a)", PdbPointer
));
202 Read information from the CPU save state.
204 @param This EFI_SMM_CPU_PROTOCOL instance
205 @param Width The number of bytes to read from the CPU save state.
206 @param Register Specifies the CPU register to read form the save state.
207 @param CpuIndex Specifies the zero-based index of the CPU save state.
208 @param Buffer Upon return, this holds the CPU register value read from the save state.
210 @retval EFI_SUCCESS The register was read from Save State
211 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
212 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
218 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
220 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
228 // Retrieve pointer to the specified CPU's SMM Save State buffer
230 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
231 return EFI_INVALID_PARAMETER
;
235 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
237 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
239 // The pseudo-register only supports the 64-bit size specified by Width.
241 if (Width
!= sizeof (UINT64
)) {
242 return EFI_INVALID_PARAMETER
;
245 // If the processor is in SMM at the time the SMI occurred,
246 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
247 // Otherwise, EFI_NOT_FOUND is returned.
249 if (mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
250 *(UINT64
*)Buffer
= gSmmCpuPrivate
->ProcessorInfo
[CpuIndex
].ProcessorId
;
253 return EFI_NOT_FOUND
;
257 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
258 return EFI_INVALID_PARAMETER
;
261 Status
= SmmCpuFeaturesReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
262 if (Status
== EFI_UNSUPPORTED
) {
263 Status
= ReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
269 Write data to the CPU save state.
271 @param This EFI_SMM_CPU_PROTOCOL instance
272 @param Width The number of bytes to read from the CPU save state.
273 @param Register Specifies the CPU register to write to the save state.
274 @param CpuIndex Specifies the zero-based index of the CPU save state
275 @param Buffer Upon entry, this holds the new CPU register value.
277 @retval EFI_SUCCESS The register was written from Save State
278 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
279 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
285 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
287 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
289 IN CONST VOID
*Buffer
295 // Retrieve pointer to the specified CPU's SMM Save State buffer
297 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
298 return EFI_INVALID_PARAMETER
;
302 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
304 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
308 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
309 return EFI_INVALID_PARAMETER
;
312 Status
= SmmCpuFeaturesWriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
313 if (Status
== EFI_UNSUPPORTED
) {
314 Status
= WriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
321 C function for SMI handler. To change all processor's SMMBase Register.
334 // Update SMM IDT entries' code segment and load IDT
336 AsmWriteIdtr (&gcSmiIdtr
);
337 ApicId
= GetApicId ();
339 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
341 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
342 if (ApicId
== (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
344 // Initialize SMM specific features on the currently executing CPU
346 SmmCpuFeaturesInitializeProcessor (
349 gSmmCpuPrivate
->ProcessorInfo
,
355 // BSP rebase is already done above.
356 // Initialize private data during S3 resume
358 InitializeMpSyncData ();
362 // Hook return after RSM to set SMM re-based flag
364 SemaphoreHook (Index
, &mRebased
[Index
]);
373 Relocate SmmBases for each processor.
375 Execute on first boot and all S3 resumes
384 UINT8 BakBuf
[BACK_BUF_SIZE
];
385 SMRAM_SAVE_STATE_MAP BakBuf2
;
386 SMRAM_SAVE_STATE_MAP
*CpuStatePtr
;
393 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
395 ASSERT (sizeof (BakBuf
) >= gcSmmInitSize
);
398 // Patch ASM code template with current CR0, CR3, and CR4 values
400 gSmmCr0
= (UINT32
)AsmReadCr0 ();
401 gSmmCr3
= (UINT32
)AsmReadCr3 ();
402 gSmmCr4
= (UINT32
)AsmReadCr4 ();
405 // Patch GDTR for SMM base relocation
407 gcSmiInitGdtr
.Base
= gcSmiGdtr
.Base
;
408 gcSmiInitGdtr
.Limit
= gcSmiGdtr
.Limit
;
410 U8Ptr
= (UINT8
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMM_HANDLER_OFFSET
);
411 CpuStatePtr
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
414 // Backup original contents at address 0x38000
416 CopyMem (BakBuf
, U8Ptr
, sizeof (BakBuf
));
417 CopyMem (&BakBuf2
, CpuStatePtr
, sizeof (BakBuf2
));
420 // Load image for relocation
422 CopyMem (U8Ptr
, gcSmmInitTemplate
, gcSmmInitSize
);
425 // Retrieve the local APIC ID of current processor
427 ApicId
= GetApicId ();
430 // Relocate SM bases for all APs
431 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
434 BspIndex
= (UINTN
)-1;
435 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
436 mRebased
[Index
] = FALSE
;
437 if (ApicId
!= (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
438 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
440 // Wait for this AP to finish its 1st SMI
442 while (!mRebased
[Index
]);
445 // BSP will be Relocated later
452 // Relocate BSP's SMM base
454 ASSERT (BspIndex
!= (UINTN
)-1);
458 // Wait for the BSP to finish its 1st SMI
460 while (!mRebased
[BspIndex
]);
463 // Restore contents at address 0x38000
465 CopyMem (CpuStatePtr
, &BakBuf2
, sizeof (BakBuf2
));
466 CopyMem (U8Ptr
, BakBuf
, sizeof (BakBuf
));
470 Perform SMM initialization for all processors in the S3 boot path.
472 For a native platform, MP initialization in the S3 boot path is also performed in this function.
480 SMM_S3_RESUME_STATE
*SmmS3ResumeState
;
481 IA32_DESCRIPTOR Ia32Idtr
;
482 IA32_DESCRIPTOR X64Idtr
;
483 IA32_IDT_GATE_DESCRIPTOR IdtEntryTable
[EXCEPTION_VECTOR_NUMBER
];
486 DEBUG ((EFI_D_INFO
, "SmmRestoreCpu()\n"));
489 // See if there is enough context to resume PEI Phase
491 if (mSmmS3ResumeState
== NULL
) {
492 DEBUG ((EFI_D_ERROR
, "No context to return to PEI Phase\n"));
496 SmmS3ResumeState
= mSmmS3ResumeState
;
497 ASSERT (SmmS3ResumeState
!= NULL
);
499 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_64
) {
501 // Save the IA32 IDT Descriptor
503 AsmReadIdtr ((IA32_DESCRIPTOR
*) &Ia32Idtr
);
506 // Setup X64 IDT table
508 ZeroMem (IdtEntryTable
, sizeof (IA32_IDT_GATE_DESCRIPTOR
) * 32);
509 X64Idtr
.Base
= (UINTN
) IdtEntryTable
;
510 X64Idtr
.Limit
= (UINT16
) (sizeof (IA32_IDT_GATE_DESCRIPTOR
) * 32 - 1);
511 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &X64Idtr
);
514 // Setup the default exception handler
516 Status
= InitializeCpuExceptionHandlers (NULL
);
517 ASSERT_EFI_ERROR (Status
);
520 // Initialize Debug Agent to support source level debug
522 InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64
, (VOID
*)&Ia32Idtr
, NULL
);
526 // Skip initialization if mAcpiCpuData is not valid
528 if (mAcpiCpuData
.NumberOfCpus
> 0) {
530 // First time microcode load and restore MTRRs
532 EarlyInitializeCpu ();
536 // Restore SMBASE for BSP and all APs
541 // Skip initialization if mAcpiCpuData is not valid
543 if (mAcpiCpuData
.NumberOfCpus
> 0) {
545 // Restore MSRs for BSP and all APs
551 // Set a flag to restore SMM configuration in S3 path.
553 mRestoreSmmConfigurationInS3
= TRUE
;
555 DEBUG (( EFI_D_INFO
, "SMM S3 Return CS = %x\n", SmmS3ResumeState
->ReturnCs
));
556 DEBUG (( EFI_D_INFO
, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState
->ReturnEntryPoint
));
557 DEBUG (( EFI_D_INFO
, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState
->ReturnContext1
));
558 DEBUG (( EFI_D_INFO
, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState
->ReturnContext2
));
559 DEBUG (( EFI_D_INFO
, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState
->ReturnStackPointer
));
562 // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
564 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_32
) {
565 DEBUG ((EFI_D_INFO
, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
568 (SWITCH_STACK_ENTRY_POINT
)(UINTN
)SmmS3ResumeState
->ReturnEntryPoint
,
569 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnContext1
,
570 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnContext2
,
571 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnStackPointer
576 // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
578 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_64
) {
579 DEBUG ((EFI_D_INFO
, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
581 // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
583 SaveAndSetDebugTimerInterrupt (FALSE
);
585 // Restore IA32 IDT table
587 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &Ia32Idtr
);
589 SmmS3ResumeState
->ReturnCs
,
590 (UINT32
)SmmS3ResumeState
->ReturnEntryPoint
,
591 (UINT32
)SmmS3ResumeState
->ReturnContext1
,
592 (UINT32
)SmmS3ResumeState
->ReturnContext2
,
593 (UINT32
)SmmS3ResumeState
->ReturnStackPointer
598 // Can not resume PEI Phase
600 DEBUG ((EFI_D_ERROR
, "No context to return to PEI Phase\n"));
605 Copy register table from ACPI NVS memory into SMRAM.
607 @param[in] DestinationRegisterTableList Points to destination register table.
608 @param[in] SourceRegisterTableList Points to source register table.
609 @param[in] NumberOfCpus Number of CPUs.
614 IN CPU_REGISTER_TABLE
*DestinationRegisterTableList
,
615 IN CPU_REGISTER_TABLE
*SourceRegisterTableList
,
616 IN UINT32 NumberOfCpus
621 CPU_REGISTER_TABLE_ENTRY
*RegisterTableEntry
;
623 CopyMem (DestinationRegisterTableList
, SourceRegisterTableList
, NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
624 for (Index
= 0; Index
< NumberOfCpus
; Index
++) {
625 DestinationRegisterTableList
[Index
].RegisterTableEntry
= AllocatePool (DestinationRegisterTableList
[Index
].AllocatedSize
);
626 ASSERT (DestinationRegisterTableList
[Index
].RegisterTableEntry
!= NULL
);
627 CopyMem (DestinationRegisterTableList
[Index
].RegisterTableEntry
, SourceRegisterTableList
[Index
].RegisterTableEntry
, DestinationRegisterTableList
[Index
].AllocatedSize
);
629 // Go though all MSRs in register table to initialize MSR spin lock
631 RegisterTableEntry
= DestinationRegisterTableList
[Index
].RegisterTableEntry
;
632 for (Index1
= 0; Index1
< DestinationRegisterTableList
[Index
].TableLength
; Index1
++, RegisterTableEntry
++) {
633 if ((RegisterTableEntry
->RegisterType
== Msr
) && (RegisterTableEntry
->ValidBitLength
< 64)) {
635 // Initialize MSR spin lock only for those MSRs need bit field writing
637 InitMsrSpinLockByIndex (RegisterTableEntry
->Index
);
644 SMM Ready To Lock event notification handler.
646 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
647 perform additional lock actions that must be performed from SMM on the next SMI.
649 @param[in] Protocol Points to the protocol's unique identifier.
650 @param[in] Interface Points to the interface instance.
651 @param[in] Handle The handle on which the interface was installed.
653 @retval EFI_SUCCESS Notification handler runs successfully.
657 SmmReadyToLockEventNotify (
658 IN CONST EFI_GUID
*Protocol
,
663 ACPI_CPU_DATA
*AcpiCpuData
;
664 IA32_DESCRIPTOR
*Gdtr
;
665 IA32_DESCRIPTOR
*Idtr
;
668 // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
670 mAcpiCpuData
.NumberOfCpus
= 0;
673 // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
675 AcpiCpuData
= (ACPI_CPU_DATA
*)(UINTN
)PcdGet64 (PcdCpuS3DataAddress
);
676 if (AcpiCpuData
== 0) {
681 // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
683 CopyMem (&mAcpiCpuData
, AcpiCpuData
, sizeof (mAcpiCpuData
));
685 mAcpiCpuData
.MtrrTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (MTRR_SETTINGS
));
686 ASSERT (mAcpiCpuData
.MtrrTable
!= 0);
688 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.MtrrTable
, (VOID
*)(UINTN
)AcpiCpuData
->MtrrTable
, sizeof (MTRR_SETTINGS
));
690 mAcpiCpuData
.GdtrProfile
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (IA32_DESCRIPTOR
));
691 ASSERT (mAcpiCpuData
.GdtrProfile
!= 0);
693 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.GdtrProfile
, (VOID
*)(UINTN
)AcpiCpuData
->GdtrProfile
, sizeof (IA32_DESCRIPTOR
));
695 mAcpiCpuData
.IdtrProfile
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (IA32_DESCRIPTOR
));
696 ASSERT (mAcpiCpuData
.IdtrProfile
!= 0);
698 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.IdtrProfile
, (VOID
*)(UINTN
)AcpiCpuData
->IdtrProfile
, sizeof (IA32_DESCRIPTOR
));
700 mAcpiCpuData
.PreSmmInitRegisterTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (mAcpiCpuData
.NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
701 ASSERT (mAcpiCpuData
.PreSmmInitRegisterTable
!= 0);
704 (CPU_REGISTER_TABLE
*)(UINTN
)mAcpiCpuData
.PreSmmInitRegisterTable
,
705 (CPU_REGISTER_TABLE
*)(UINTN
)AcpiCpuData
->PreSmmInitRegisterTable
,
706 mAcpiCpuData
.NumberOfCpus
709 mAcpiCpuData
.RegisterTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (mAcpiCpuData
.NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
710 ASSERT (mAcpiCpuData
.RegisterTable
!= 0);
713 (CPU_REGISTER_TABLE
*)(UINTN
)mAcpiCpuData
.RegisterTable
,
714 (CPU_REGISTER_TABLE
*)(UINTN
)AcpiCpuData
->RegisterTable
,
715 mAcpiCpuData
.NumberOfCpus
719 // Copy AP's GDT, IDT and Machine Check handler into SMRAM.
721 Gdtr
= (IA32_DESCRIPTOR
*)(UINTN
)mAcpiCpuData
.GdtrProfile
;
722 Idtr
= (IA32_DESCRIPTOR
*)(UINTN
)mAcpiCpuData
.IdtrProfile
;
724 mGdtForAp
= AllocatePool ((Gdtr
->Limit
+ 1) + (Idtr
->Limit
+ 1) + mAcpiCpuData
.ApMachineCheckHandlerSize
);
725 ASSERT (mGdtForAp
!= NULL
);
726 mIdtForAp
= (VOID
*) ((UINTN
)mGdtForAp
+ (Gdtr
->Limit
+ 1));
727 mMachineCheckHandlerForAp
= (VOID
*) ((UINTN
)mIdtForAp
+ (Idtr
->Limit
+ 1));
729 CopyMem (mGdtForAp
, (VOID
*)Gdtr
->Base
, Gdtr
->Limit
+ 1);
730 CopyMem (mIdtForAp
, (VOID
*)Idtr
->Base
, Idtr
->Limit
+ 1);
731 CopyMem (mMachineCheckHandlerForAp
, (VOID
*)(UINTN
)mAcpiCpuData
.ApMachineCheckHandlerBase
, mAcpiCpuData
.ApMachineCheckHandlerSize
);
735 // Set SMM ready to lock flag and return
737 mSmmReadyToLock
= TRUE
;
742 The module Entry Point of the CPU SMM driver.
744 @param ImageHandle The firmware allocated handle for the EFI image.
745 @param SystemTable A pointer to the EFI System Table.
747 @retval EFI_SUCCESS The entry point is executed successfully.
748 @retval Other Some error occurs when executing this entry point.
754 IN EFI_HANDLE ImageHandle
,
755 IN EFI_SYSTEM_TABLE
*SystemTable
759 EFI_MP_SERVICES_PROTOCOL
*MpServices
;
760 UINTN NumberOfEnabledProcessors
;
768 EFI_SMRAM_DESCRIPTOR
*SmramDescriptor
;
769 SMM_S3_RESUME_STATE
*SmmS3ResumeState
;
779 // Initialize Debug Agent to support source level debug in SMM code
781 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM
, NULL
, NULL
);
784 // Report the start of CPU SMM initialization.
788 EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_INIT
792 // Fix segment address of the long-mode-switch jump
794 if (sizeof (UINTN
) == sizeof (UINT64
)) {
795 gSmmJmpAddr
.Segment
= LONG_MODE_CODE_SEGMENT
;
799 // Find out SMRR Base and SMRR Size
801 FindSmramInfo (&mCpuHotPlugData
.SmrrBase
, &mCpuHotPlugData
.SmrrSize
);
804 // Get MP Services Protocol
806 Status
= SystemTable
->BootServices
->LocateProtocol (&gEfiMpServiceProtocolGuid
, NULL
, (VOID
**)&MpServices
);
807 ASSERT_EFI_ERROR (Status
);
810 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
812 Status
= MpServices
->GetNumberOfProcessors (MpServices
, &mNumberOfCpus
, &NumberOfEnabledProcessors
);
813 ASSERT_EFI_ERROR (Status
);
814 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
817 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
818 // A constant BSP index makes no sense because it may be hot removed.
821 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
823 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection
));
828 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
830 mSmmCodeAccessCheckEnable
= PcdGetBool (PcdCpuSmmCodeAccessCheckEnable
);
831 DEBUG ((EFI_D_INFO
, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable
));
834 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
836 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
837 mMaxNumberOfCpus
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
839 mMaxNumberOfCpus
= mNumberOfCpus
;
841 gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
= mMaxNumberOfCpus
;
844 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
845 // allocated buffer. The minimum size of this buffer for a uniprocessor system
846 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
847 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
848 // then the SMI entry point and the CPU save state areas can be tiles to minimize
849 // the total amount SMRAM required for all the CPUs. The tile size can be computed
850 // by adding the // CPU save state size, any extra CPU specific context, and
851 // the size of code that must be placed at the SMI entry point to transfer
852 // control to a C function in the native SMM execution mode. This size is
853 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
854 // The total amount of memory required is the maximum number of CPUs that
855 // platform supports times the tile size. The picture below shows the tiling,
856 // where m is the number of tiles that fit in 32KB.
858 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
859 // | CPU m+1 Save State |
860 // +-----------------------------+
861 // | CPU m+1 Extra Data |
862 // +-----------------------------+
864 // +-----------------------------+
865 // | CPU 2m SMI Entry |
866 // +#############################+ <-- Base of allocated buffer + 64 KB
867 // | CPU m-1 Save State |
868 // +-----------------------------+
869 // | CPU m-1 Extra Data |
870 // +-----------------------------+
872 // +-----------------------------+
873 // | CPU 2m-1 SMI Entry |
874 // +=============================+ <-- 2^n offset from Base of allocated buffer
875 // | . . . . . . . . . . . . |
876 // +=============================+ <-- 2^n offset from Base of allocated buffer
877 // | CPU 2 Save State |
878 // +-----------------------------+
879 // | CPU 2 Extra Data |
880 // +-----------------------------+
882 // +-----------------------------+
883 // | CPU m+1 SMI Entry |
884 // +=============================+ <-- Base of allocated buffer + 32 KB
885 // | CPU 1 Save State |
886 // +-----------------------------+
887 // | CPU 1 Extra Data |
888 // +-----------------------------+
890 // +-----------------------------+
891 // | CPU m SMI Entry |
892 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
893 // | CPU 0 Save State |
894 // +-----------------------------+
895 // | CPU 0 Extra Data |
896 // +-----------------------------+
898 // +-----------------------------+
899 // | CPU m-1 SMI Entry |
900 // +=============================+ <-- 2^n offset from Base of allocated buffer
901 // | . . . . . . . . . . . . |
902 // +=============================+ <-- 2^n offset from Base of allocated buffer
904 // +-----------------------------+
905 // | CPU 1 SMI Entry |
906 // +=============================+ <-- 2^n offset from Base of allocated buffer
908 // +-----------------------------+
909 // | CPU 0 SMI Entry |
910 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
914 // Retrieve CPU Family
916 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, NULL
);
917 FamilyId
= (RegEax
>> 8) & 0xf;
918 ModelId
= (RegEax
>> 4) & 0xf;
919 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
920 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
924 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
925 if (RegEax
>= CPUID_EXTENDED_CPU_SIG
) {
926 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
929 // Determine the mode of the CPU at the time an SMI occurs
930 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
931 // Volume 3C, Section 34.4.1.1
933 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
;
934 if ((RegEdx
& BIT29
) != 0) {
935 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
937 if (FamilyId
== 0x06) {
938 if (ModelId
== 0x17 || ModelId
== 0x0f || ModelId
== 0x1c) {
939 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
944 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
945 // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size
946 // is rounded up to nearest power of 2.
948 TileCodeSize
= GetSmiHandlerSize ();
949 TileCodeSize
= ALIGN_VALUE(TileCodeSize
, SIZE_4KB
);
950 TileDataSize
= sizeof (SMRAM_SAVE_STATE_MAP
) + sizeof (PROCESSOR_SMM_DESCRIPTOR
);
951 TileDataSize
= ALIGN_VALUE(TileDataSize
, SIZE_4KB
);
952 TileSize
= TileDataSize
+ TileCodeSize
- 1;
953 TileSize
= 2 * GetPowerOfTwo32 ((UINT32
)TileSize
);
954 DEBUG ((EFI_D_INFO
, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize
, TileCodeSize
, TileDataSize
));
957 // If the TileSize is larger than space available for the SMI Handler of CPU[i],
958 // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
959 // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be
962 ASSERT (TileSize
<= (SMRAM_SAVE_STATE_MAP_OFFSET
+ sizeof (SMRAM_SAVE_STATE_MAP
) - SMM_HANDLER_OFFSET
));
965 // Allocate buffer for all of the tiles.
967 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
968 // Volume 3C, Section 34.11 SMBASE Relocation
969 // For Pentium and Intel486 processors, the SMBASE values must be
970 // aligned on a 32-KByte boundary or the processor will enter shutdown
971 // state during the execution of a RSM instruction.
973 // Intel486 processors: FamilyId is 4
974 // Pentium processors : FamilyId is 5
976 BufferPages
= EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1));
977 if ((FamilyId
== 4) || (FamilyId
== 5)) {
978 Buffer
= AllocateAlignedPages (BufferPages
, SIZE_32KB
);
980 Buffer
= AllocateAlignedPages (BufferPages
, SIZE_4KB
);
982 ASSERT (Buffer
!= NULL
);
983 DEBUG ((EFI_D_INFO
, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer
, EFI_PAGES_TO_SIZE(BufferPages
)));
986 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
988 gSmmCpuPrivate
->ProcessorInfo
= (EFI_PROCESSOR_INFORMATION
*)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION
) * mMaxNumberOfCpus
);
989 ASSERT (gSmmCpuPrivate
->ProcessorInfo
!= NULL
);
991 gSmmCpuPrivate
->Operation
= (SMM_CPU_OPERATION
*)AllocatePool (sizeof (SMM_CPU_OPERATION
) * mMaxNumberOfCpus
);
992 ASSERT (gSmmCpuPrivate
->Operation
!= NULL
);
994 gSmmCpuPrivate
->CpuSaveStateSize
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
995 ASSERT (gSmmCpuPrivate
->CpuSaveStateSize
!= NULL
);
997 gSmmCpuPrivate
->CpuSaveState
= (VOID
**)AllocatePool (sizeof (VOID
*) * mMaxNumberOfCpus
);
998 ASSERT (gSmmCpuPrivate
->CpuSaveState
!= NULL
);
1000 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveStateSize
= gSmmCpuPrivate
->CpuSaveStateSize
;
1001 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveState
= gSmmCpuPrivate
->CpuSaveState
;
1004 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
1006 mCpuHotPlugData
.ApicId
= (UINT64
*)AllocatePool (sizeof (UINT64
) * mMaxNumberOfCpus
);
1007 ASSERT (mCpuHotPlugData
.ApicId
!= NULL
);
1008 mCpuHotPlugData
.SmBase
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
1009 ASSERT (mCpuHotPlugData
.SmBase
!= NULL
);
1010 mCpuHotPlugData
.ArrayLength
= (UINT32
)mMaxNumberOfCpus
;
1013 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
1014 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
1015 // size for each CPU in the platform
1017 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
1018 mCpuHotPlugData
.SmBase
[Index
] = (UINTN
)Buffer
+ Index
* TileSize
- SMM_HANDLER_OFFSET
;
1019 gSmmCpuPrivate
->CpuSaveStateSize
[Index
] = sizeof(SMRAM_SAVE_STATE_MAP
);
1020 gSmmCpuPrivate
->CpuSaveState
[Index
] = (VOID
*)(mCpuHotPlugData
.SmBase
[Index
] + SMRAM_SAVE_STATE_MAP_OFFSET
);
1021 gSmmCpuPrivate
->Operation
[Index
] = SmmCpuNone
;
1023 if (Index
< mNumberOfCpus
) {
1024 Status
= MpServices
->GetProcessorInfo (MpServices
, Index
, &gSmmCpuPrivate
->ProcessorInfo
[Index
]);
1025 ASSERT_EFI_ERROR (Status
);
1026 mCpuHotPlugData
.ApicId
[Index
] = gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
;
1028 DEBUG ((EFI_D_INFO
, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
1030 (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
,
1031 mCpuHotPlugData
.SmBase
[Index
],
1032 gSmmCpuPrivate
->CpuSaveState
[Index
],
1033 gSmmCpuPrivate
->CpuSaveStateSize
[Index
]
1036 gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
= INVALID_APIC_ID
;
1037 mCpuHotPlugData
.ApicId
[Index
] = INVALID_APIC_ID
;
1042 // Allocate SMI stacks for all processors.
1044 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
1046 // 2 more pages is allocated for each processor.
1047 // one is guard page and the other is known good stack.
1049 // +-------------------------------------------+-----+-------------------------------------------+
1050 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
1051 // +-------------------------------------------+-----+-------------------------------------------+
1053 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
1055 mSmmStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2);
1056 Stacks
= (UINT8
*) AllocatePages (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2));
1057 ASSERT (Stacks
!= NULL
);
1058 mSmmStackArrayBase
= (UINTN
)Stacks
;
1059 mSmmStackArrayEnd
= mSmmStackArrayBase
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
- 1;
1061 mSmmStackSize
= PcdGet32 (PcdCpuSmmStackSize
);
1062 Stacks
= (UINT8
*) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
));
1063 ASSERT (Stacks
!= NULL
);
1067 // Set SMI stack for SMM base relocation
1069 gSmmInitStack
= (UINTN
) (Stacks
+ mSmmStackSize
- sizeof (UINTN
));
1074 InitializeSmmIdt ();
1077 // Relocate SMM Base addresses to the ones allocated from SMRAM
1079 mRebased
= (BOOLEAN
*)AllocateZeroPool (sizeof (BOOLEAN
) * mMaxNumberOfCpus
);
1080 ASSERT (mRebased
!= NULL
);
1081 SmmRelocateBases ();
1084 // Call hook for BSP to perform extra actions in normal mode after all
1085 // SMM base addresses have been relocated on all CPUs
1087 SmmCpuFeaturesSmmRelocationComplete ();
1090 // SMM Time initialization
1092 InitializeSmmTimer ();
1095 // Initialize MP globals
1097 Cr3
= InitializeMpServiceData (Stacks
, mSmmStackSize
);
1100 // Fill in SMM Reserved Regions
1102 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedStart
= 0;
1103 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedSize
= 0;
1106 // Install the SMM Configuration Protocol onto a new handle on the handle database.
1107 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
1108 // to an SMRAM address will be present in the handle database
1110 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
1111 &gSmmCpuPrivate
->SmmCpuHandle
,
1112 &gEfiSmmConfigurationProtocolGuid
, &gSmmCpuPrivate
->SmmConfiguration
,
1115 ASSERT_EFI_ERROR (Status
);
1118 // Install the SMM CPU Protocol into SMM protocol database
1120 Status
= gSmst
->SmmInstallProtocolInterface (
1122 &gEfiSmmCpuProtocolGuid
,
1123 EFI_NATIVE_INTERFACE
,
1126 ASSERT_EFI_ERROR (Status
);
1129 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
1131 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
1132 Status
= PcdSet64S (PcdCpuHotPlugDataAddress
, (UINT64
)(UINTN
)&mCpuHotPlugData
);
1133 ASSERT_EFI_ERROR (Status
);
1137 // Initialize SMM CPU Services Support
1139 Status
= InitializeSmmCpuServices (mSmmCpuHandle
);
1140 ASSERT_EFI_ERROR (Status
);
1143 // register SMM Ready To Lock Protocol notification
1145 Status
= gSmst
->SmmRegisterProtocolNotify (
1146 &gEfiSmmReadyToLockProtocolGuid
,
1147 SmmReadyToLockEventNotify
,
1150 ASSERT_EFI_ERROR (Status
);
1152 GuidHob
= GetFirstGuidHob (&gEfiAcpiVariableGuid
);
1153 if (GuidHob
!= NULL
) {
1154 SmramDescriptor
= (EFI_SMRAM_DESCRIPTOR
*) GET_GUID_HOB_DATA (GuidHob
);
1156 DEBUG ((EFI_D_INFO
, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor
));
1157 DEBUG ((EFI_D_INFO
, "SMM S3 Structure = %x\n", SmramDescriptor
->CpuStart
));
1159 SmmS3ResumeState
= (SMM_S3_RESUME_STATE
*)(UINTN
)SmramDescriptor
->CpuStart
;
1160 ZeroMem (SmmS3ResumeState
, sizeof (SMM_S3_RESUME_STATE
));
1162 mSmmS3ResumeState
= SmmS3ResumeState
;
1163 SmmS3ResumeState
->Smst
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)gSmst
;
1165 SmmS3ResumeState
->SmmS3ResumeEntryPoint
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)SmmRestoreCpu
;
1167 SmmS3ResumeState
->SmmS3StackSize
= SIZE_32KB
;
1168 SmmS3ResumeState
->SmmS3StackBase
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN
)SmmS3ResumeState
->SmmS3StackSize
));
1169 if (SmmS3ResumeState
->SmmS3StackBase
== 0) {
1170 SmmS3ResumeState
->SmmS3StackSize
= 0;
1173 SmmS3ResumeState
->SmmS3Cr0
= gSmmCr0
;
1174 SmmS3ResumeState
->SmmS3Cr3
= Cr3
;
1175 SmmS3ResumeState
->SmmS3Cr4
= gSmmCr4
;
1177 if (sizeof (UINTN
) == sizeof (UINT64
)) {
1178 SmmS3ResumeState
->Signature
= SMM_S3_RESUME_SMM_64
;
1180 if (sizeof (UINTN
) == sizeof (UINT32
)) {
1181 SmmS3ResumeState
->Signature
= SMM_S3_RESUME_SMM_32
;
1186 // Check XD and BTS features
1188 CheckProcessorFeature ();
1191 // Initialize SMM Profile feature
1193 InitSmmProfile (Cr3
);
1196 // Patch SmmS3ResumeState->SmmS3Cr3
1200 DEBUG ((EFI_D_INFO
, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
1207 Find out SMRAM information including SMRR base and SMRR size.
1209 @param SmrrBase SMRR base
1210 @param SmrrSize SMRR size
1215 OUT UINT32
*SmrrBase
,
1216 OUT UINT32
*SmrrSize
1221 EFI_SMM_ACCESS2_PROTOCOL
*SmmAccess
;
1222 EFI_SMRAM_DESCRIPTOR
*CurrentSmramRange
;
1223 EFI_SMRAM_DESCRIPTOR
*SmramRanges
;
1224 UINTN SmramRangeCount
;
1230 // Get SMM Access Protocol
1232 Status
= gBS
->LocateProtocol (&gEfiSmmAccess2ProtocolGuid
, NULL
, (VOID
**)&SmmAccess
);
1233 ASSERT_EFI_ERROR (Status
);
1236 // Get SMRAM information
1239 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, NULL
);
1240 ASSERT (Status
== EFI_BUFFER_TOO_SMALL
);
1242 SmramRanges
= (EFI_SMRAM_DESCRIPTOR
*)AllocatePool (Size
);
1243 ASSERT (SmramRanges
!= NULL
);
1245 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, SmramRanges
);
1246 ASSERT_EFI_ERROR (Status
);
1248 SmramRangeCount
= Size
/ sizeof (EFI_SMRAM_DESCRIPTOR
);
1251 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
1253 CurrentSmramRange
= NULL
;
1254 for (Index
= 0, MaxSize
= SIZE_256KB
- EFI_PAGE_SIZE
; Index
< SmramRangeCount
; Index
++) {
1256 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
1258 if ((SmramRanges
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
1262 if (SmramRanges
[Index
].CpuStart
>= BASE_1MB
) {
1263 if ((SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
) <= BASE_4GB
) {
1264 if (SmramRanges
[Index
].PhysicalSize
>= MaxSize
) {
1265 MaxSize
= SmramRanges
[Index
].PhysicalSize
;
1266 CurrentSmramRange
= &SmramRanges
[Index
];
1272 ASSERT (CurrentSmramRange
!= NULL
);
1274 *SmrrBase
= (UINT32
)CurrentSmramRange
->CpuStart
;
1275 *SmrrSize
= (UINT32
)CurrentSmramRange
->PhysicalSize
;
1279 for (Index
= 0; Index
< SmramRangeCount
; Index
++) {
1280 if (SmramRanges
[Index
].CpuStart
< *SmrrBase
&& *SmrrBase
== (SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
)) {
1281 *SmrrBase
= (UINT32
)SmramRanges
[Index
].CpuStart
;
1282 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1284 } else if ((*SmrrBase
+ *SmrrSize
) == SmramRanges
[Index
].CpuStart
&& SmramRanges
[Index
].PhysicalSize
> 0) {
1285 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1291 DEBUG ((EFI_D_INFO
, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase
, *SmrrSize
));
1295 Configure SMM Code Access Check feature on an AP.
1296 SMM Feature Control MSR will be locked after configuration.
1298 @param[in,out] Buffer Pointer to private data buffer.
1302 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1307 UINT64 SmmFeatureControlMsr
;
1308 UINT64 NewSmmFeatureControlMsr
;
1311 // Retrieve the CPU Index from the context passed in
1313 CpuIndex
= *(UINTN
*)Buffer
;
1316 // Get the current SMM Feature Control MSR value
1318 SmmFeatureControlMsr
= SmmCpuFeaturesGetSmmRegister (CpuIndex
, SmmRegFeatureControl
);
1321 // Compute the new SMM Feature Control MSR value
1323 NewSmmFeatureControlMsr
= SmmFeatureControlMsr
;
1324 if (mSmmCodeAccessCheckEnable
) {
1325 NewSmmFeatureControlMsr
|= SMM_CODE_CHK_EN_BIT
;
1326 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1327 NewSmmFeatureControlMsr
|= SMM_FEATURE_CONTROL_LOCK_BIT
;
1332 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1334 if (NewSmmFeatureControlMsr
!= SmmFeatureControlMsr
) {
1335 SmmCpuFeaturesSetSmmRegister (CpuIndex
, SmmRegFeatureControl
, NewSmmFeatureControlMsr
);
1339 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1341 ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock
);
1345 Configure SMM Code Access Check feature for all processors.
1346 SMM Feature Control MSR will be locked after configuration.
1349 ConfigSmmCodeAccessCheck (
1357 // Check to see if the Feature Control MSR is supported on this CPU
1359 Index
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1360 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index
, SmmRegFeatureControl
)) {
1361 mSmmCodeAccessCheckEnable
= FALSE
;
1366 // Check to see if the CPU supports the SMM Code Access Check feature
1367 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1369 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) == 0) {
1370 mSmmCodeAccessCheckEnable
= FALSE
;
1375 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1377 InitializeSpinLock (&mConfigSmmCodeAccessCheckLock
);
1380 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1381 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1383 AcquireSpinLock (&mConfigSmmCodeAccessCheckLock
);
1386 // Enable SMM Code Access Check feature on the BSP.
1388 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index
);
1391 // Enable SMM Code Access Check feature for the APs.
1393 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1394 if (Index
!= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
1397 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1398 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1400 AcquireSpinLock (&mConfigSmmCodeAccessCheckLock
);
1403 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1405 Status
= gSmst
->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor
, Index
, &Index
);
1406 ASSERT_EFI_ERROR (Status
);
1409 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1411 while (!AcquireSpinLockOrFail (&mConfigSmmCodeAccessCheckLock
)) {
1416 // Release the Config SMM Code Access Check spin lock.
1418 ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock
);
1424 This API provides a way to allocate memory for page table.
1426 This API can be called more once to allocate memory for page tables.
1428 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1429 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1430 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1433 @param Pages The number of 4 KB pages to allocate.
1435 @return A pointer to the allocated buffer or NULL if allocation fails.
1439 AllocatePageTableMemory (
1445 Buffer
= SmmCpuFeaturesAllocatePageTableMemory (Pages
);
1446 if (Buffer
!= NULL
) {
1449 return AllocatePages (Pages
);
1453 Perform the remaining tasks.
1457 PerformRemainingTasks (
1461 if (mSmmReadyToLock
) {
1463 // Start SMM Profile feature
1465 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1469 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1473 // Configure SMM Code Access Check feature if available.
1475 ConfigSmmCodeAccessCheck ();
1477 SmmCpuFeaturesCompleteSmmReadyToLock ();
1480 // Clean SMM ready to lock flag
1482 mSmmReadyToLock
= FALSE
;
1487 Perform the pre tasks.
1496 // Restore SMM Configuration in S3 boot path.
1498 if (mRestoreSmmConfigurationInS3
) {
1500 // Need make sure gSmst is correct because below function may use them.
1502 gSmst
->SmmStartupThisAp
= gSmmCpuPrivate
->SmmCoreEntryContext
.SmmStartupThisAp
;
1503 gSmst
->CurrentlyExecutingCpu
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1504 gSmst
->NumberOfCpus
= gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
;
1505 gSmst
->CpuSaveStateSize
= gSmmCpuPrivate
->SmmCoreEntryContext
.CpuSaveStateSize
;
1506 gSmst
->CpuSaveState
= gSmmCpuPrivate
->SmmCoreEntryContext
.CpuSaveState
;
1509 // Configure SMM Code Access Check feature if available.
1511 ConfigSmmCodeAccessCheck ();
1513 SmmCpuFeaturesCompleteSmmReadyToLock ();
1515 mRestoreSmmConfigurationInS3
= FALSE
;