2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include "PiSmmCpuDxeSmm.h"
20 // SMM CPU Private Data structure that contains SMM Configuration Protocol
21 // along its supporting fields.
23 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
= {
24 SMM_CPU_PRIVATE_DATA_SIGNATURE
, // Signature
26 NULL
, // Pointer to ProcessorInfo array
27 NULL
, // Pointer to Operation array
28 NULL
, // Pointer to CpuSaveStateSize array
29 NULL
, // Pointer to CpuSaveState array
30 { {0} }, // SmmReservedSmramRegion
32 SmmStartupThisAp
, // SmmCoreEntryContext.SmmStartupThisAp
33 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
34 0, // SmmCoreEntryContext.NumberOfCpus
35 NULL
, // SmmCoreEntryContext.CpuSaveStateSize
36 NULL
// SmmCoreEntryContext.CpuSaveState
40 mSmmCpuPrivateData
.SmmReservedSmramRegion
, // SmmConfiguration.SmramReservedRegions
41 RegisterSmmEntry
// SmmConfiguration.RegisterSmmEntry
45 CPU_HOT_PLUG_DATA mCpuHotPlugData
= {
46 CPU_HOT_PLUG_DATA_REVISION_1
, // Revision
47 0, // Array Length of SmBase and APIC ID
48 NULL
, // Pointer to APIC ID array
49 NULL
, // Pointer to SMBASE array
56 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
58 SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
= &mSmmCpuPrivateData
;
61 // SMM Relocation variables
63 volatile BOOLEAN
*mRebased
;
64 volatile BOOLEAN mIsBsp
;
67 /// Handle for the SMM CPU Protocol
69 EFI_HANDLE mSmmCpuHandle
= NULL
;
72 /// SMM CPU Protocol instance
74 EFI_SMM_CPU_PROTOCOL mSmmCpu
= {
80 /// SMM Memory Attribute Protocol instance
82 EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute
= {
83 EdkiiSmmGetMemoryAttributes
,
84 EdkiiSmmSetMemoryAttributes
,
85 EdkiiSmmClearMemoryAttributes
88 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable
[EXCEPTION_VECTOR_NUMBER
];
91 // SMM stack information
93 UINTN mSmmStackArrayBase
;
94 UINTN mSmmStackArrayEnd
;
97 UINTN mMaxNumberOfCpus
= 1;
98 UINTN mNumberOfCpus
= 1;
101 // SMM ready to lock flag
103 BOOLEAN mSmmReadyToLock
= FALSE
;
106 // Global used to cache PCD for SMM Code Access Check enable
108 BOOLEAN mSmmCodeAccessCheckEnable
= FALSE
;
111 // Global copy of the PcdPteMemoryEncryptionAddressOrMask
113 UINT64 mAddressEncMask
= 0;
116 // Spin lock used to serialize setting of SMM Code Access Check feature
118 SPIN_LOCK
*mConfigSmmCodeAccessCheckLock
= NULL
;
121 // Saved SMM ranges information
123 EFI_SMRAM_DESCRIPTOR
*mSmmCpuSmramRanges
;
124 UINTN mSmmCpuSmramRangeCount
;
126 UINT8 mPhysicalAddressBits
;
129 Initialize IDT to setup exception handlers for SMM.
138 BOOLEAN InterruptState
;
139 IA32_DESCRIPTOR DxeIdtr
;
142 // There are 32 (not 255) entries in it since only processor
143 // generated exceptions will be handled.
145 gcSmiIdtr
.Limit
= (sizeof(IA32_IDT_GATE_DESCRIPTOR
) * 32) - 1;
147 // Allocate page aligned IDT, because it might be set as read only.
149 gcSmiIdtr
.Base
= (UINTN
)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr
.Limit
+ 1));
150 ASSERT (gcSmiIdtr
.Base
!= 0);
151 ZeroMem ((VOID
*)gcSmiIdtr
.Base
, gcSmiIdtr
.Limit
+ 1);
154 // Disable Interrupt and save DXE IDT table
156 InterruptState
= SaveAndDisableInterrupts ();
157 AsmReadIdtr (&DxeIdtr
);
159 // Load SMM temporary IDT table
161 AsmWriteIdtr (&gcSmiIdtr
);
163 // Setup SMM default exception handlers, SMM IDT table
164 // will be updated and saved in gcSmiIdtr
166 Status
= InitializeCpuExceptionHandlers (NULL
);
167 ASSERT_EFI_ERROR (Status
);
169 // Restore DXE IDT table and CPU interrupt
171 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &DxeIdtr
);
172 SetInterruptState (InterruptState
);
176 Search module name by input IP address and output it.
178 @param CallerIpAddress Caller instruction pointer.
183 IN UINTN CallerIpAddress
192 Pe32Data
= PeCoffSearchImageBase (CallerIpAddress
);
194 DEBUG ((DEBUG_ERROR
, "It is invoked from the instruction before IP(0x%p)", (VOID
*) CallerIpAddress
));
195 PdbPointer
= PeCoffLoaderGetPdbPointer ((VOID
*) Pe32Data
);
196 if (PdbPointer
!= NULL
) {
197 DEBUG ((DEBUG_ERROR
, " in module (%a)\n", PdbPointer
));
203 Read information from the CPU save state.
205 @param This EFI_SMM_CPU_PROTOCOL instance
206 @param Width The number of bytes to read from the CPU save state.
207 @param Register Specifies the CPU register to read form the save state.
208 @param CpuIndex Specifies the zero-based index of the CPU save state.
209 @param Buffer Upon return, this holds the CPU register value read from the save state.
211 @retval EFI_SUCCESS The register was read from Save State
212 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
213 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
219 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
221 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
229 // Retrieve pointer to the specified CPU's SMM Save State buffer
231 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
232 return EFI_INVALID_PARAMETER
;
236 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
238 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
240 // The pseudo-register only supports the 64-bit size specified by Width.
242 if (Width
!= sizeof (UINT64
)) {
243 return EFI_INVALID_PARAMETER
;
246 // If the processor is in SMM at the time the SMI occurred,
247 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
248 // Otherwise, EFI_NOT_FOUND is returned.
250 if (*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
)) {
251 *(UINT64
*)Buffer
= gSmmCpuPrivate
->ProcessorInfo
[CpuIndex
].ProcessorId
;
254 return EFI_NOT_FOUND
;
258 if (!(*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
))) {
259 return EFI_INVALID_PARAMETER
;
262 Status
= SmmCpuFeaturesReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
263 if (Status
== EFI_UNSUPPORTED
) {
264 Status
= ReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
270 Write data to the CPU save state.
272 @param This EFI_SMM_CPU_PROTOCOL instance
273 @param Width The number of bytes to read from the CPU save state.
274 @param Register Specifies the CPU register to write to the save state.
275 @param CpuIndex Specifies the zero-based index of the CPU save state
276 @param Buffer Upon entry, this holds the new CPU register value.
278 @retval EFI_SUCCESS The register was written from Save State
279 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
280 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
286 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
288 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
290 IN CONST VOID
*Buffer
296 // Retrieve pointer to the specified CPU's SMM Save State buffer
298 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
299 return EFI_INVALID_PARAMETER
;
303 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
305 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
309 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
310 return EFI_INVALID_PARAMETER
;
313 Status
= SmmCpuFeaturesWriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
314 if (Status
== EFI_UNSUPPORTED
) {
315 Status
= WriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
322 C function for SMI handler. To change all processor's SMMBase Register.
335 // Update SMM IDT entries' code segment and load IDT
337 AsmWriteIdtr (&gcSmiIdtr
);
338 ApicId
= GetApicId ();
340 ASSERT (mNumberOfCpus
<= mMaxNumberOfCpus
);
342 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
343 if (ApicId
== (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
345 // Initialize SMM specific features on the currently executing CPU
347 SmmCpuFeaturesInitializeProcessor (
350 gSmmCpuPrivate
->ProcessorInfo
,
356 // Check XD and BTS features on each processor on normal boot
358 CheckFeatureSupported ();
363 // BSP rebase is already done above.
364 // Initialize private data during S3 resume
366 InitializeMpSyncData ();
370 // Hook return after RSM to set SMM re-based flag
372 SemaphoreHook (Index
, &mRebased
[Index
]);
381 Relocate SmmBases for each processor.
383 Execute on first boot and all S3 resumes
392 UINT8 BakBuf
[BACK_BUF_SIZE
];
393 SMRAM_SAVE_STATE_MAP BakBuf2
;
394 SMRAM_SAVE_STATE_MAP
*CpuStatePtr
;
401 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
403 ASSERT (sizeof (BakBuf
) >= gcSmmInitSize
);
406 // Patch ASM code template with current CR0, CR3, and CR4 values
408 gSmmCr0
= (UINT32
)AsmReadCr0 ();
409 gSmmCr3
= (UINT32
)AsmReadCr3 ();
410 gSmmCr4
= (UINT32
)AsmReadCr4 ();
413 // Patch GDTR for SMM base relocation
415 gcSmiInitGdtr
.Base
= gcSmiGdtr
.Base
;
416 gcSmiInitGdtr
.Limit
= gcSmiGdtr
.Limit
;
418 U8Ptr
= (UINT8
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMM_HANDLER_OFFSET
);
419 CpuStatePtr
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
422 // Backup original contents at address 0x38000
424 CopyMem (BakBuf
, U8Ptr
, sizeof (BakBuf
));
425 CopyMem (&BakBuf2
, CpuStatePtr
, sizeof (BakBuf2
));
428 // Load image for relocation
430 CopyMem (U8Ptr
, gcSmmInitTemplate
, gcSmmInitSize
);
433 // Retrieve the local APIC ID of current processor
435 ApicId
= GetApicId ();
438 // Relocate SM bases for all APs
439 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
442 BspIndex
= (UINTN
)-1;
443 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
444 mRebased
[Index
] = FALSE
;
445 if (ApicId
!= (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
446 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
448 // Wait for this AP to finish its 1st SMI
450 while (!mRebased
[Index
]);
453 // BSP will be Relocated later
460 // Relocate BSP's SMM base
462 ASSERT (BspIndex
!= (UINTN
)-1);
466 // Wait for the BSP to finish its 1st SMI
468 while (!mRebased
[BspIndex
]);
471 // Restore contents at address 0x38000
473 CopyMem (CpuStatePtr
, &BakBuf2
, sizeof (BakBuf2
));
474 CopyMem (U8Ptr
, BakBuf
, sizeof (BakBuf
));
478 SMM Ready To Lock event notification handler.
480 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
481 perform additional lock actions that must be performed from SMM on the next SMI.
483 @param[in] Protocol Points to the protocol's unique identifier.
484 @param[in] Interface Points to the interface instance.
485 @param[in] Handle The handle on which the interface was installed.
487 @retval EFI_SUCCESS Notification handler runs successfully.
491 SmmReadyToLockEventNotify (
492 IN CONST EFI_GUID
*Protocol
,
500 // Cache a copy of UEFI memory map before we start profiling feature.
505 // Set SMM ready to lock flag and return
507 mSmmReadyToLock
= TRUE
;
512 The module Entry Point of the CPU SMM driver.
514 @param ImageHandle The firmware allocated handle for the EFI image.
515 @param SystemTable A pointer to the EFI System Table.
517 @retval EFI_SUCCESS The entry point is executed successfully.
518 @retval Other Some error occurs when executing this entry point.
524 IN EFI_HANDLE ImageHandle
,
525 IN EFI_SYSTEM_TABLE
*SystemTable
529 EFI_MP_SERVICES_PROTOCOL
*MpServices
;
530 UINTN NumberOfEnabledProcessors
;
546 // Initialize Debug Agent to support source level debug in SMM code
548 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM
, NULL
, NULL
);
551 // Report the start of CPU SMM initialization.
555 EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_INIT
559 // Fix segment address of the long-mode-switch jump
561 if (sizeof (UINTN
) == sizeof (UINT64
)) {
562 gSmmJmpAddr
.Segment
= LONG_MODE_CODE_SEGMENT
;
566 // Find out SMRR Base and SMRR Size
568 FindSmramInfo (&mCpuHotPlugData
.SmrrBase
, &mCpuHotPlugData
.SmrrSize
);
571 // Get MP Services Protocol
573 Status
= SystemTable
->BootServices
->LocateProtocol (&gEfiMpServiceProtocolGuid
, NULL
, (VOID
**)&MpServices
);
574 ASSERT_EFI_ERROR (Status
);
577 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
579 Status
= MpServices
->GetNumberOfProcessors (MpServices
, &mNumberOfCpus
, &NumberOfEnabledProcessors
);
580 ASSERT_EFI_ERROR (Status
);
581 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
584 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
585 // A constant BSP index makes no sense because it may be hot removed.
588 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
590 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection
));
595 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
597 mSmmCodeAccessCheckEnable
= PcdGetBool (PcdCpuSmmCodeAccessCheckEnable
);
598 DEBUG ((EFI_D_INFO
, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable
));
601 // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.
602 // Make sure AddressEncMask is contained to smallest supported address field.
604 mAddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
605 DEBUG ((EFI_D_INFO
, "mAddressEncMask = 0x%lx\n", mAddressEncMask
));
608 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
610 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
611 mMaxNumberOfCpus
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
613 mMaxNumberOfCpus
= mNumberOfCpus
;
615 gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
= mMaxNumberOfCpus
;
618 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
619 // allocated buffer. The minimum size of this buffer for a uniprocessor system
620 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
621 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
622 // then the SMI entry point and the CPU save state areas can be tiles to minimize
623 // the total amount SMRAM required for all the CPUs. The tile size can be computed
624 // by adding the // CPU save state size, any extra CPU specific context, and
625 // the size of code that must be placed at the SMI entry point to transfer
626 // control to a C function in the native SMM execution mode. This size is
627 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
628 // The total amount of memory required is the maximum number of CPUs that
629 // platform supports times the tile size. The picture below shows the tiling,
630 // where m is the number of tiles that fit in 32KB.
632 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
633 // | CPU m+1 Save State |
634 // +-----------------------------+
635 // | CPU m+1 Extra Data |
636 // +-----------------------------+
638 // +-----------------------------+
639 // | CPU 2m SMI Entry |
640 // +#############################+ <-- Base of allocated buffer + 64 KB
641 // | CPU m-1 Save State |
642 // +-----------------------------+
643 // | CPU m-1 Extra Data |
644 // +-----------------------------+
646 // +-----------------------------+
647 // | CPU 2m-1 SMI Entry |
648 // +=============================+ <-- 2^n offset from Base of allocated buffer
649 // | . . . . . . . . . . . . |
650 // +=============================+ <-- 2^n offset from Base of allocated buffer
651 // | CPU 2 Save State |
652 // +-----------------------------+
653 // | CPU 2 Extra Data |
654 // +-----------------------------+
656 // +-----------------------------+
657 // | CPU m+1 SMI Entry |
658 // +=============================+ <-- Base of allocated buffer + 32 KB
659 // | CPU 1 Save State |
660 // +-----------------------------+
661 // | CPU 1 Extra Data |
662 // +-----------------------------+
664 // +-----------------------------+
665 // | CPU m SMI Entry |
666 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
667 // | CPU 0 Save State |
668 // +-----------------------------+
669 // | CPU 0 Extra Data |
670 // +-----------------------------+
672 // +-----------------------------+
673 // | CPU m-1 SMI Entry |
674 // +=============================+ <-- 2^n offset from Base of allocated buffer
675 // | . . . . . . . . . . . . |
676 // +=============================+ <-- 2^n offset from Base of allocated buffer
678 // +-----------------------------+
679 // | CPU 1 SMI Entry |
680 // +=============================+ <-- 2^n offset from Base of allocated buffer
682 // +-----------------------------+
683 // | CPU 0 SMI Entry |
684 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
688 // Retrieve CPU Family
690 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, NULL
);
691 FamilyId
= (RegEax
>> 8) & 0xf;
692 ModelId
= (RegEax
>> 4) & 0xf;
693 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
694 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
698 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
699 if (RegEax
>= CPUID_EXTENDED_CPU_SIG
) {
700 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
703 // Determine the mode of the CPU at the time an SMI occurs
704 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
705 // Volume 3C, Section 34.4.1.1
707 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
;
708 if ((RegEdx
& BIT29
) != 0) {
709 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
711 if (FamilyId
== 0x06) {
712 if (ModelId
== 0x17 || ModelId
== 0x0f || ModelId
== 0x1c) {
713 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
718 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
719 // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
720 // This size is rounded up to nearest power of 2.
722 TileCodeSize
= GetSmiHandlerSize ();
723 TileCodeSize
= ALIGN_VALUE(TileCodeSize
, SIZE_4KB
);
724 TileDataSize
= (SMRAM_SAVE_STATE_MAP_OFFSET
- SMM_PSD_OFFSET
) + sizeof (SMRAM_SAVE_STATE_MAP
);
725 TileDataSize
= ALIGN_VALUE(TileDataSize
, SIZE_4KB
);
726 TileSize
= TileDataSize
+ TileCodeSize
- 1;
727 TileSize
= 2 * GetPowerOfTwo32 ((UINT32
)TileSize
);
728 DEBUG ((EFI_D_INFO
, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize
, TileCodeSize
, TileDataSize
));
731 // If the TileSize is larger than space available for the SMI Handler of
732 // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save
733 // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then
734 // the SMI Handler size must be reduced or the size of the extra CPU specific
735 // context must be reduced.
737 ASSERT (TileSize
<= (SMRAM_SAVE_STATE_MAP_OFFSET
+ sizeof (SMRAM_SAVE_STATE_MAP
) - SMM_HANDLER_OFFSET
));
740 // Allocate buffer for all of the tiles.
742 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
743 // Volume 3C, Section 34.11 SMBASE Relocation
744 // For Pentium and Intel486 processors, the SMBASE values must be
745 // aligned on a 32-KByte boundary or the processor will enter shutdown
746 // state during the execution of a RSM instruction.
748 // Intel486 processors: FamilyId is 4
749 // Pentium processors : FamilyId is 5
751 BufferPages
= EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1));
752 if ((FamilyId
== 4) || (FamilyId
== 5)) {
753 Buffer
= AllocateAlignedCodePages (BufferPages
, SIZE_32KB
);
755 Buffer
= AllocateAlignedCodePages (BufferPages
, SIZE_4KB
);
757 ASSERT (Buffer
!= NULL
);
758 DEBUG ((EFI_D_INFO
, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer
, EFI_PAGES_TO_SIZE(BufferPages
)));
761 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
763 gSmmCpuPrivate
->ProcessorInfo
= (EFI_PROCESSOR_INFORMATION
*)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION
) * mMaxNumberOfCpus
);
764 ASSERT (gSmmCpuPrivate
->ProcessorInfo
!= NULL
);
766 gSmmCpuPrivate
->Operation
= (SMM_CPU_OPERATION
*)AllocatePool (sizeof (SMM_CPU_OPERATION
) * mMaxNumberOfCpus
);
767 ASSERT (gSmmCpuPrivate
->Operation
!= NULL
);
769 gSmmCpuPrivate
->CpuSaveStateSize
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
770 ASSERT (gSmmCpuPrivate
->CpuSaveStateSize
!= NULL
);
772 gSmmCpuPrivate
->CpuSaveState
= (VOID
**)AllocatePool (sizeof (VOID
*) * mMaxNumberOfCpus
);
773 ASSERT (gSmmCpuPrivate
->CpuSaveState
!= NULL
);
775 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveStateSize
= gSmmCpuPrivate
->CpuSaveStateSize
;
776 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveState
= gSmmCpuPrivate
->CpuSaveState
;
779 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
781 mCpuHotPlugData
.ApicId
= (UINT64
*)AllocatePool (sizeof (UINT64
) * mMaxNumberOfCpus
);
782 ASSERT (mCpuHotPlugData
.ApicId
!= NULL
);
783 mCpuHotPlugData
.SmBase
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
784 ASSERT (mCpuHotPlugData
.SmBase
!= NULL
);
785 mCpuHotPlugData
.ArrayLength
= (UINT32
)mMaxNumberOfCpus
;
788 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
789 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
790 // size for each CPU in the platform
792 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
793 mCpuHotPlugData
.SmBase
[Index
] = (UINTN
)Buffer
+ Index
* TileSize
- SMM_HANDLER_OFFSET
;
794 gSmmCpuPrivate
->CpuSaveStateSize
[Index
] = sizeof(SMRAM_SAVE_STATE_MAP
);
795 gSmmCpuPrivate
->CpuSaveState
[Index
] = (VOID
*)(mCpuHotPlugData
.SmBase
[Index
] + SMRAM_SAVE_STATE_MAP_OFFSET
);
796 gSmmCpuPrivate
->Operation
[Index
] = SmmCpuNone
;
798 if (Index
< mNumberOfCpus
) {
799 Status
= MpServices
->GetProcessorInfo (MpServices
, Index
, &gSmmCpuPrivate
->ProcessorInfo
[Index
]);
800 ASSERT_EFI_ERROR (Status
);
801 mCpuHotPlugData
.ApicId
[Index
] = gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
;
803 DEBUG ((EFI_D_INFO
, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
805 (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
,
806 mCpuHotPlugData
.SmBase
[Index
],
807 gSmmCpuPrivate
->CpuSaveState
[Index
],
808 gSmmCpuPrivate
->CpuSaveStateSize
[Index
]
811 gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
= INVALID_APIC_ID
;
812 mCpuHotPlugData
.ApicId
[Index
] = INVALID_APIC_ID
;
817 // Allocate SMI stacks for all processors.
819 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
821 // 2 more pages is allocated for each processor.
822 // one is guard page and the other is known good stack.
824 // +-------------------------------------------+-----+-------------------------------------------+
825 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
826 // +-------------------------------------------+-----+-------------------------------------------+
828 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
830 mSmmStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2);
831 Stacks
= (UINT8
*) AllocatePages (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2));
832 ASSERT (Stacks
!= NULL
);
833 mSmmStackArrayBase
= (UINTN
)Stacks
;
834 mSmmStackArrayEnd
= mSmmStackArrayBase
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
- 1;
836 mSmmStackSize
= PcdGet32 (PcdCpuSmmStackSize
);
837 Stacks
= (UINT8
*) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
));
838 ASSERT (Stacks
!= NULL
);
842 // Set SMI stack for SMM base relocation
844 gSmmInitStack
= (UINTN
) (Stacks
+ mSmmStackSize
- sizeof (UINTN
));
852 // Relocate SMM Base addresses to the ones allocated from SMRAM
854 mRebased
= (BOOLEAN
*)AllocateZeroPool (sizeof (BOOLEAN
) * mMaxNumberOfCpus
);
855 ASSERT (mRebased
!= NULL
);
859 // Call hook for BSP to perform extra actions in normal mode after all
860 // SMM base addresses have been relocated on all CPUs
862 SmmCpuFeaturesSmmRelocationComplete ();
864 DEBUG ((DEBUG_INFO
, "mXdSupported - 0x%x\n", mXdSupported
));
867 // SMM Time initialization
869 InitializeSmmTimer ();
872 // Initialize MP globals
874 Cr3
= InitializeMpServiceData (Stacks
, mSmmStackSize
);
877 // Fill in SMM Reserved Regions
879 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedStart
= 0;
880 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedSize
= 0;
883 // Install the SMM Configuration Protocol onto a new handle on the handle database.
884 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
885 // to an SMRAM address will be present in the handle database
887 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
888 &gSmmCpuPrivate
->SmmCpuHandle
,
889 &gEfiSmmConfigurationProtocolGuid
, &gSmmCpuPrivate
->SmmConfiguration
,
892 ASSERT_EFI_ERROR (Status
);
895 // Install the SMM CPU Protocol into SMM protocol database
897 Status
= gSmst
->SmmInstallProtocolInterface (
899 &gEfiSmmCpuProtocolGuid
,
900 EFI_NATIVE_INTERFACE
,
903 ASSERT_EFI_ERROR (Status
);
906 // Install the SMM Memory Attribute Protocol into SMM protocol database
908 Status
= gSmst
->SmmInstallProtocolInterface (
910 &gEdkiiSmmMemoryAttributeProtocolGuid
,
911 EFI_NATIVE_INTERFACE
,
914 ASSERT_EFI_ERROR (Status
);
917 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
919 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
920 Status
= PcdSet64S (PcdCpuHotPlugDataAddress
, (UINT64
)(UINTN
)&mCpuHotPlugData
);
921 ASSERT_EFI_ERROR (Status
);
925 // Initialize SMM CPU Services Support
927 Status
= InitializeSmmCpuServices (mSmmCpuHandle
);
928 ASSERT_EFI_ERROR (Status
);
931 // register SMM Ready To Lock Protocol notification
933 Status
= gSmst
->SmmRegisterProtocolNotify (
934 &gEfiSmmReadyToLockProtocolGuid
,
935 SmmReadyToLockEventNotify
,
938 ASSERT_EFI_ERROR (Status
);
941 // Initialize SMM Profile feature
943 InitSmmProfile (Cr3
);
945 GetAcpiS3EnableFlag ();
946 InitSmmS3ResumeState (Cr3
);
948 DEBUG ((EFI_D_INFO
, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
955 Find out SMRAM information including SMRR base and SMRR size.
957 @param SmrrBase SMRR base
958 @param SmrrSize SMRR size
963 OUT UINT32
*SmrrBase
,
969 EFI_SMM_ACCESS2_PROTOCOL
*SmmAccess
;
970 EFI_SMRAM_DESCRIPTOR
*CurrentSmramRange
;
976 // Get SMM Access Protocol
978 Status
= gBS
->LocateProtocol (&gEfiSmmAccess2ProtocolGuid
, NULL
, (VOID
**)&SmmAccess
);
979 ASSERT_EFI_ERROR (Status
);
982 // Get SMRAM information
985 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, NULL
);
986 ASSERT (Status
== EFI_BUFFER_TOO_SMALL
);
988 mSmmCpuSmramRanges
= (EFI_SMRAM_DESCRIPTOR
*)AllocatePool (Size
);
989 ASSERT (mSmmCpuSmramRanges
!= NULL
);
991 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, mSmmCpuSmramRanges
);
992 ASSERT_EFI_ERROR (Status
);
994 mSmmCpuSmramRangeCount
= Size
/ sizeof (EFI_SMRAM_DESCRIPTOR
);
997 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
999 CurrentSmramRange
= NULL
;
1000 for (Index
= 0, MaxSize
= SIZE_256KB
- EFI_PAGE_SIZE
; Index
< mSmmCpuSmramRangeCount
; Index
++) {
1002 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
1004 if ((mSmmCpuSmramRanges
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
1008 if (mSmmCpuSmramRanges
[Index
].CpuStart
>= BASE_1MB
) {
1009 if ((mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
) <= SMRR_MAX_ADDRESS
) {
1010 if (mSmmCpuSmramRanges
[Index
].PhysicalSize
>= MaxSize
) {
1011 MaxSize
= mSmmCpuSmramRanges
[Index
].PhysicalSize
;
1012 CurrentSmramRange
= &mSmmCpuSmramRanges
[Index
];
1018 ASSERT (CurrentSmramRange
!= NULL
);
1020 *SmrrBase
= (UINT32
)CurrentSmramRange
->CpuStart
;
1021 *SmrrSize
= (UINT32
)CurrentSmramRange
->PhysicalSize
;
1025 for (Index
= 0; Index
< mSmmCpuSmramRangeCount
; Index
++) {
1026 if (mSmmCpuSmramRanges
[Index
].CpuStart
< *SmrrBase
&&
1027 *SmrrBase
== (mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
)) {
1028 *SmrrBase
= (UINT32
)mSmmCpuSmramRanges
[Index
].CpuStart
;
1029 *SmrrSize
= (UINT32
)(*SmrrSize
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
);
1031 } else if ((*SmrrBase
+ *SmrrSize
) == mSmmCpuSmramRanges
[Index
].CpuStart
&& mSmmCpuSmramRanges
[Index
].PhysicalSize
> 0) {
1032 *SmrrSize
= (UINT32
)(*SmrrSize
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
);
1038 DEBUG ((EFI_D_INFO
, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase
, *SmrrSize
));
1042 Configure SMM Code Access Check feature on an AP.
1043 SMM Feature Control MSR will be locked after configuration.
1045 @param[in,out] Buffer Pointer to private data buffer.
1049 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1054 UINT64 SmmFeatureControlMsr
;
1055 UINT64 NewSmmFeatureControlMsr
;
1058 // Retrieve the CPU Index from the context passed in
1060 CpuIndex
= *(UINTN
*)Buffer
;
1063 // Get the current SMM Feature Control MSR value
1065 SmmFeatureControlMsr
= SmmCpuFeaturesGetSmmRegister (CpuIndex
, SmmRegFeatureControl
);
1068 // Compute the new SMM Feature Control MSR value
1070 NewSmmFeatureControlMsr
= SmmFeatureControlMsr
;
1071 if (mSmmCodeAccessCheckEnable
) {
1072 NewSmmFeatureControlMsr
|= SMM_CODE_CHK_EN_BIT
;
1073 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1074 NewSmmFeatureControlMsr
|= SMM_FEATURE_CONTROL_LOCK_BIT
;
1079 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1081 if (NewSmmFeatureControlMsr
!= SmmFeatureControlMsr
) {
1082 SmmCpuFeaturesSetSmmRegister (CpuIndex
, SmmRegFeatureControl
, NewSmmFeatureControlMsr
);
1086 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1088 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1092 Configure SMM Code Access Check feature for all processors.
1093 SMM Feature Control MSR will be locked after configuration.
1096 ConfigSmmCodeAccessCheck (
1104 // Check to see if the Feature Control MSR is supported on this CPU
1106 Index
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1107 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index
, SmmRegFeatureControl
)) {
1108 mSmmCodeAccessCheckEnable
= FALSE
;
1113 // Check to see if the CPU supports the SMM Code Access Check feature
1114 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1116 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) == 0) {
1117 mSmmCodeAccessCheckEnable
= FALSE
;
1122 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1124 InitializeSpinLock (mConfigSmmCodeAccessCheckLock
);
1127 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1128 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1130 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1133 // Enable SMM Code Access Check feature on the BSP.
1135 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index
);
1138 // Enable SMM Code Access Check feature for the APs.
1140 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1141 if (Index
!= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
1142 if (gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
== INVALID_APIC_ID
) {
1144 // If this processor does not exist
1149 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1150 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1152 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1155 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1157 Status
= gSmst
->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor
, Index
, &Index
);
1158 ASSERT_EFI_ERROR (Status
);
1161 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1163 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock
)) {
1168 // Release the Config SMM Code Access Check spin lock.
1170 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1176 This API provides a way to allocate memory for page table.
1178 This API can be called more once to allocate memory for page tables.
1180 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1181 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1182 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1185 @param Pages The number of 4 KB pages to allocate.
1187 @return A pointer to the allocated buffer or NULL if allocation fails.
1191 AllocatePageTableMemory (
1197 Buffer
= SmmCpuFeaturesAllocatePageTableMemory (Pages
);
1198 if (Buffer
!= NULL
) {
1201 return AllocatePages (Pages
);
1205 Allocate pages for code.
1207 @param[in] Pages Number of pages to be allocated.
1209 @return Allocated memory.
1217 EFI_PHYSICAL_ADDRESS Memory
;
1223 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, Pages
, &Memory
);
1224 if (EFI_ERROR (Status
)) {
1227 return (VOID
*) (UINTN
) Memory
;
1231 Allocate aligned pages for code.
1233 @param[in] Pages Number of pages to be allocated.
1234 @param[in] Alignment The requested alignment of the allocation.
1235 Must be a power of two.
1236 If Alignment is zero, then byte alignment is used.
1238 @return Allocated memory.
1241 AllocateAlignedCodePages (
1247 EFI_PHYSICAL_ADDRESS Memory
;
1248 UINTN AlignedMemory
;
1249 UINTN AlignmentMask
;
1250 UINTN UnalignedPages
;
1254 // Alignment must be a power of two or zero.
1256 ASSERT ((Alignment
& (Alignment
- 1)) == 0);
1261 if (Alignment
> EFI_PAGE_SIZE
) {
1263 // Calculate the total number of pages since alignment is larger than page size.
1265 AlignmentMask
= Alignment
- 1;
1266 RealPages
= Pages
+ EFI_SIZE_TO_PAGES (Alignment
);
1268 // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
1270 ASSERT (RealPages
> Pages
);
1272 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, RealPages
, &Memory
);
1273 if (EFI_ERROR (Status
)) {
1276 AlignedMemory
= ((UINTN
) Memory
+ AlignmentMask
) & ~AlignmentMask
;
1277 UnalignedPages
= EFI_SIZE_TO_PAGES (AlignedMemory
- (UINTN
) Memory
);
1278 if (UnalignedPages
> 0) {
1280 // Free first unaligned page(s).
1282 Status
= gSmst
->SmmFreePages (Memory
, UnalignedPages
);
1283 ASSERT_EFI_ERROR (Status
);
1285 Memory
= AlignedMemory
+ EFI_PAGES_TO_SIZE (Pages
);
1286 UnalignedPages
= RealPages
- Pages
- UnalignedPages
;
1287 if (UnalignedPages
> 0) {
1289 // Free last unaligned page(s).
1291 Status
= gSmst
->SmmFreePages (Memory
, UnalignedPages
);
1292 ASSERT_EFI_ERROR (Status
);
1296 // Do not over-allocate pages in this case.
1298 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, Pages
, &Memory
);
1299 if (EFI_ERROR (Status
)) {
1302 AlignedMemory
= (UINTN
) Memory
;
1304 return (VOID
*) AlignedMemory
;
1308 Perform the remaining tasks.
1312 PerformRemainingTasks (
1316 if (mSmmReadyToLock
) {
1318 // Start SMM Profile feature
1320 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1324 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1329 // Mark critical region to be read-only in page table
1331 SetMemMapAttributes ();
1334 // For outside SMRAM, we only map SMM communication buffer or MMIO.
1336 SetUefiMemMapAttributes ();
1339 // Set page table itself to be read-only
1341 SetPageTableAttributes ();
1344 // Configure SMM Code Access Check feature if available.
1346 ConfigSmmCodeAccessCheck ();
1348 SmmCpuFeaturesCompleteSmmReadyToLock ();
1351 // Clean SMM ready to lock flag
1353 mSmmReadyToLock
= FALSE
;
1358 Perform the pre tasks.
1366 RestoreSmmConfigurationInS3 ();