2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PiSmmCpuDxeSmm.h"
18 // SMM CPU Private Data structure that contains SMM Configuration Protocol
19 // along its supporting fields.
21 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
= {
22 SMM_CPU_PRIVATE_DATA_SIGNATURE
, // Signature
24 NULL
, // Pointer to ProcessorInfo array
25 NULL
, // Pointer to Operation array
26 NULL
, // Pointer to CpuSaveStateSize array
27 NULL
, // Pointer to CpuSaveState array
28 { {0} }, // SmmReservedSmramRegion
30 SmmStartupThisAp
, // SmmCoreEntryContext.SmmStartupThisAp
31 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
32 0, // SmmCoreEntryContext.NumberOfCpus
33 NULL
, // SmmCoreEntryContext.CpuSaveStateSize
34 NULL
// SmmCoreEntryContext.CpuSaveState
38 mSmmCpuPrivateData
.SmmReservedSmramRegion
, // SmmConfiguration.SmramReservedRegions
39 RegisterSmmEntry
// SmmConfiguration.RegisterSmmEntry
43 CPU_HOT_PLUG_DATA mCpuHotPlugData
= {
44 CPU_HOT_PLUG_DATA_REVISION_1
, // Revision
45 0, // Array Length of SmBase and APIC ID
46 NULL
, // Pointer to APIC ID array
47 NULL
, // Pointer to SMBASE array
54 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
56 SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
= &mSmmCpuPrivateData
;
59 // SMM Relocation variables
61 volatile BOOLEAN
*mRebased
;
62 volatile BOOLEAN mIsBsp
;
65 /// Handle for the SMM CPU Protocol
67 EFI_HANDLE mSmmCpuHandle
= NULL
;
70 /// SMM CPU Protocol instance
72 EFI_SMM_CPU_PROTOCOL mSmmCpu
= {
77 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable
[EXCEPTION_VECTOR_NUMBER
];
80 // SMM stack information
82 UINTN mSmmStackArrayBase
;
83 UINTN mSmmStackArrayEnd
;
87 // Pointer to structure used during S3 Resume
89 SMM_S3_RESUME_STATE
*mSmmS3ResumeState
= NULL
;
91 UINTN mMaxNumberOfCpus
= 1;
92 UINTN mNumberOfCpus
= 1;
95 // SMM ready to lock flag
97 BOOLEAN mSmmReadyToLock
= FALSE
;
100 // Global used to cache PCD for SMM Code Access Check enable
102 BOOLEAN mSmmCodeAccessCheckEnable
= FALSE
;
105 // Spin lock used to serialize setting of SMM Code Access Check feature
107 SPIN_LOCK mConfigSmmCodeAccessCheckLock
;
110 Initialize IDT to setup exception handlers for SMM.
119 BOOLEAN InterruptState
;
120 IA32_DESCRIPTOR DxeIdtr
;
122 // Disable Interrupt and save DXE IDT table
124 InterruptState
= SaveAndDisableInterrupts ();
125 AsmReadIdtr (&DxeIdtr
);
127 // Load SMM temporary IDT table
129 AsmWriteIdtr (&gcSmiIdtr
);
131 // Setup SMM default exception handlers, SMM IDT table
132 // will be updated and saved in gcSmiIdtr
134 Status
= InitializeCpuExceptionHandlers (NULL
);
135 ASSERT_EFI_ERROR (Status
);
137 // Restore DXE IDT table and CPU interrupt
139 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &DxeIdtr
);
140 SetInterruptState (InterruptState
);
144 Search module name by input IP address and output it.
146 @param CallerIpAddress Caller instruction pointer.
151 IN UINTN CallerIpAddress
155 EFI_IMAGE_DOS_HEADER
*DosHdr
;
156 EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr
;
158 UINT64 DumpIpAddress
;
163 Pe32Data
= CallerIpAddress
& ~(SIZE_4KB
- 1);
164 while (Pe32Data
!= 0) {
165 DosHdr
= (EFI_IMAGE_DOS_HEADER
*) Pe32Data
;
166 if (DosHdr
->e_magic
== EFI_IMAGE_DOS_SIGNATURE
) {
168 // DOS image header is present, so read the PE header after the DOS image header.
170 Hdr
.Pe32
= (EFI_IMAGE_NT_HEADERS32
*)(Pe32Data
+ (UINTN
) ((DosHdr
->e_lfanew
) & 0x0ffff));
172 // Make sure PE header address does not overflow and is less than the initial address.
174 if (((UINTN
)Hdr
.Pe32
> Pe32Data
) && ((UINTN
)Hdr
.Pe32
< CallerIpAddress
)) {
175 if (Hdr
.Pe32
->Signature
== EFI_IMAGE_NT_SIGNATURE
) {
185 // Not found the image base, check the previous aligned address
187 Pe32Data
-= SIZE_4KB
;
190 DumpIpAddress
= CallerIpAddress
;
191 DEBUG ((EFI_D_ERROR
, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress
));
194 PdbPointer
= PeCoffLoaderGetPdbPointer ((VOID
*) Pe32Data
);
195 if (PdbPointer
!= NULL
) {
196 DEBUG ((EFI_D_ERROR
, " in module (%a)", PdbPointer
));
202 Read information from the CPU save state.
204 @param This EFI_SMM_CPU_PROTOCOL instance
205 @param Width The number of bytes to read from the CPU save state.
206 @param Register Specifies the CPU register to read form the save state.
207 @param CpuIndex Specifies the zero-based index of the CPU save state.
208 @param Buffer Upon return, this holds the CPU register value read from the save state.
210 @retval EFI_SUCCESS The register was read from Save State
211 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
212 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
218 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
220 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
228 // Retrieve pointer to the specified CPU's SMM Save State buffer
230 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
231 return EFI_INVALID_PARAMETER
;
235 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
237 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
239 // The pseudo-register only supports the 64-bit size specified by Width.
241 if (Width
!= sizeof (UINT64
)) {
242 return EFI_INVALID_PARAMETER
;
245 // If the processor is in SMM at the time the SMI occurred,
246 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
247 // Otherwise, EFI_NOT_FOUND is returned.
249 if (mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
250 *(UINT64
*)Buffer
= gSmmCpuPrivate
->ProcessorInfo
[CpuIndex
].ProcessorId
;
253 return EFI_NOT_FOUND
;
257 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
258 return EFI_INVALID_PARAMETER
;
261 Status
= SmmCpuFeaturesReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
262 if (Status
== EFI_UNSUPPORTED
) {
263 Status
= ReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
269 Write data to the CPU save state.
271 @param This EFI_SMM_CPU_PROTOCOL instance
272 @param Width The number of bytes to read from the CPU save state.
273 @param Register Specifies the CPU register to write to the save state.
274 @param CpuIndex Specifies the zero-based index of the CPU save state
275 @param Buffer Upon entry, this holds the new CPU register value.
277 @retval EFI_SUCCESS The register was written from Save State
278 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
279 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
285 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
287 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
289 IN CONST VOID
*Buffer
295 // Retrieve pointer to the specified CPU's SMM Save State buffer
297 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
298 return EFI_INVALID_PARAMETER
;
302 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
304 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
308 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
309 return EFI_INVALID_PARAMETER
;
312 Status
= SmmCpuFeaturesWriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
313 if (Status
== EFI_UNSUPPORTED
) {
314 Status
= WriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
321 C function for SMI handler. To change all processor's SMMBase Register.
334 // Update SMM IDT entries' code segment and load IDT
336 AsmWriteIdtr (&gcSmiIdtr
);
337 ApicId
= GetApicId ();
339 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
341 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
342 if (ApicId
== (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
344 // Initialize SMM specific features on the currently executing CPU
346 SmmCpuFeaturesInitializeProcessor (
349 gSmmCpuPrivate
->ProcessorInfo
,
355 // BSP rebase is already done above.
356 // Initialize private data during S3 resume
358 InitializeMpSyncData ();
362 // Hook return after RSM to set SMM re-based flag
364 SemaphoreHook (Index
, &mRebased
[Index
]);
373 Relocate SmmBases for each processor.
375 Execute on first boot and all S3 resumes
384 UINT8 BakBuf
[BACK_BUF_SIZE
];
385 SMRAM_SAVE_STATE_MAP BakBuf2
;
386 SMRAM_SAVE_STATE_MAP
*CpuStatePtr
;
393 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
395 ASSERT (sizeof (BakBuf
) >= gcSmmInitSize
);
398 // Patch ASM code template with current CR0, CR3, and CR4 values
400 gSmmCr0
= (UINT32
)AsmReadCr0 ();
401 gSmmCr3
= (UINT32
)AsmReadCr3 ();
402 gSmmCr4
= (UINT32
)AsmReadCr4 ();
405 // Patch GDTR for SMM base relocation
407 gcSmiInitGdtr
.Base
= gcSmiGdtr
.Base
;
408 gcSmiInitGdtr
.Limit
= gcSmiGdtr
.Limit
;
410 U8Ptr
= (UINT8
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMM_HANDLER_OFFSET
);
411 CpuStatePtr
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
414 // Backup original contents at address 0x38000
416 CopyMem (BakBuf
, U8Ptr
, sizeof (BakBuf
));
417 CopyMem (&BakBuf2
, CpuStatePtr
, sizeof (BakBuf2
));
420 // Load image for relocation
422 CopyMem (U8Ptr
, gcSmmInitTemplate
, gcSmmInitSize
);
425 // Retrieve the local APIC ID of current processor
427 ApicId
= GetApicId ();
430 // Relocate SM bases for all APs
431 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
434 BspIndex
= (UINTN
)-1;
435 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
436 mRebased
[Index
] = FALSE
;
437 if (ApicId
!= (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
438 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
440 // Wait for this AP to finish its 1st SMI
442 while (!mRebased
[Index
]);
445 // BSP will be Relocated later
452 // Relocate BSP's SMM base
454 ASSERT (BspIndex
!= (UINTN
)-1);
458 // Wait for the BSP to finish its 1st SMI
460 while (!mRebased
[BspIndex
]);
463 // Restore contents at address 0x38000
465 CopyMem (CpuStatePtr
, &BakBuf2
, sizeof (BakBuf2
));
466 CopyMem (U8Ptr
, BakBuf
, sizeof (BakBuf
));
470 Perform SMM initialization for all processors in the S3 boot path.
472 For a native platform, MP initialization in the S3 boot path is also performed in this function.
480 SMM_S3_RESUME_STATE
*SmmS3ResumeState
;
481 IA32_DESCRIPTOR Ia32Idtr
;
482 IA32_DESCRIPTOR X64Idtr
;
483 IA32_IDT_GATE_DESCRIPTOR IdtEntryTable
[EXCEPTION_VECTOR_NUMBER
];
486 DEBUG ((EFI_D_INFO
, "SmmRestoreCpu()\n"));
489 // See if there is enough context to resume PEI Phase
491 if (mSmmS3ResumeState
== NULL
) {
492 DEBUG ((EFI_D_ERROR
, "No context to return to PEI Phase\n"));
496 SmmS3ResumeState
= mSmmS3ResumeState
;
497 ASSERT (SmmS3ResumeState
!= NULL
);
499 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_64
) {
501 // Save the IA32 IDT Descriptor
503 AsmReadIdtr ((IA32_DESCRIPTOR
*) &Ia32Idtr
);
506 // Setup X64 IDT table
508 ZeroMem (IdtEntryTable
, sizeof (IA32_IDT_GATE_DESCRIPTOR
) * 32);
509 X64Idtr
.Base
= (UINTN
) IdtEntryTable
;
510 X64Idtr
.Limit
= (UINT16
) (sizeof (IA32_IDT_GATE_DESCRIPTOR
) * 32 - 1);
511 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &X64Idtr
);
514 // Setup the default exception handler
516 Status
= InitializeCpuExceptionHandlers (NULL
);
517 ASSERT_EFI_ERROR (Status
);
520 // Initialize Debug Agent to support source level debug
522 InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64
, (VOID
*)&Ia32Idtr
, NULL
);
526 // Skip initialization if mAcpiCpuData is not valid
528 if (mAcpiCpuData
.NumberOfCpus
> 0) {
530 // First time microcode load and restore MTRRs
532 EarlyInitializeCpu ();
536 // Restore SMBASE for BSP and all APs
541 // Skip initialization if mAcpiCpuData is not valid
543 if (mAcpiCpuData
.NumberOfCpus
> 0) {
545 // Restore MSRs for BSP and all APs
551 // Set a flag to restore SMM configuration in S3 path.
553 mRestoreSmmConfigurationInS3
= TRUE
;
555 DEBUG (( EFI_D_INFO
, "SMM S3 Return CS = %x\n", SmmS3ResumeState
->ReturnCs
));
556 DEBUG (( EFI_D_INFO
, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState
->ReturnEntryPoint
));
557 DEBUG (( EFI_D_INFO
, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState
->ReturnContext1
));
558 DEBUG (( EFI_D_INFO
, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState
->ReturnContext2
));
559 DEBUG (( EFI_D_INFO
, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState
->ReturnStackPointer
));
562 // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
564 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_32
) {
565 DEBUG ((EFI_D_INFO
, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
568 (SWITCH_STACK_ENTRY_POINT
)(UINTN
)SmmS3ResumeState
->ReturnEntryPoint
,
569 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnContext1
,
570 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnContext2
,
571 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnStackPointer
576 // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
578 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_64
) {
579 DEBUG ((EFI_D_INFO
, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
581 // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
583 SaveAndSetDebugTimerInterrupt (FALSE
);
585 // Restore IA32 IDT table
587 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &Ia32Idtr
);
589 SmmS3ResumeState
->ReturnCs
,
590 (UINT32
)SmmS3ResumeState
->ReturnEntryPoint
,
591 (UINT32
)SmmS3ResumeState
->ReturnContext1
,
592 (UINT32
)SmmS3ResumeState
->ReturnContext2
,
593 (UINT32
)SmmS3ResumeState
->ReturnStackPointer
598 // Can not resume PEI Phase
600 DEBUG ((EFI_D_ERROR
, "No context to return to PEI Phase\n"));
605 Copy register table from ACPI NVS memory into SMRAM.
607 @param[in] DestinationRegisterTableList Points to destination register table.
608 @param[in] SourceRegisterTableList Points to source register table.
609 @param[in] NumberOfCpus Number of CPUs.
614 IN CPU_REGISTER_TABLE
*DestinationRegisterTableList
,
615 IN CPU_REGISTER_TABLE
*SourceRegisterTableList
,
616 IN UINT32 NumberOfCpus
621 CPU_REGISTER_TABLE_ENTRY
*RegisterTableEntry
;
623 CopyMem (DestinationRegisterTableList
, SourceRegisterTableList
, NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
624 for (Index
= 0; Index
< NumberOfCpus
; Index
++) {
625 DestinationRegisterTableList
[Index
].RegisterTableEntry
= AllocatePool (DestinationRegisterTableList
[Index
].AllocatedSize
);
626 ASSERT (DestinationRegisterTableList
[Index
].RegisterTableEntry
!= NULL
);
627 CopyMem (DestinationRegisterTableList
[Index
].RegisterTableEntry
, SourceRegisterTableList
[Index
].RegisterTableEntry
, DestinationRegisterTableList
[Index
].AllocatedSize
);
629 // Go though all MSRs in register table to initialize MSR spin lock
631 RegisterTableEntry
= DestinationRegisterTableList
[Index
].RegisterTableEntry
;
632 for (Index1
= 0; Index1
< DestinationRegisterTableList
[Index
].TableLength
; Index1
++, RegisterTableEntry
++) {
633 if ((RegisterTableEntry
->RegisterType
== Msr
) && (RegisterTableEntry
->ValidBitLength
< 64)) {
635 // Initialize MSR spin lock only for those MSRs need bit field writing
637 InitMsrSpinLockByIndex (RegisterTableEntry
->Index
);
644 SMM Ready To Lock event notification handler.
646 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
647 perform additional lock actions that must be performed from SMM on the next SMI.
649 @param[in] Protocol Points to the protocol's unique identifier.
650 @param[in] Interface Points to the interface instance.
651 @param[in] Handle The handle on which the interface was installed.
653 @retval EFI_SUCCESS Notification handler runs successfully.
657 SmmReadyToLockEventNotify (
658 IN CONST EFI_GUID
*Protocol
,
663 ACPI_CPU_DATA
*AcpiCpuData
;
664 IA32_DESCRIPTOR
*Gdtr
;
665 IA32_DESCRIPTOR
*Idtr
;
668 // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
670 mAcpiCpuData
.NumberOfCpus
= 0;
673 // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
675 AcpiCpuData
= (ACPI_CPU_DATA
*)(UINTN
)PcdGet64 (PcdCpuS3DataAddress
);
676 if (AcpiCpuData
== 0) {
681 // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
683 CopyMem (&mAcpiCpuData
, AcpiCpuData
, sizeof (mAcpiCpuData
));
685 mAcpiCpuData
.MtrrTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (MTRR_SETTINGS
));
686 ASSERT (mAcpiCpuData
.MtrrTable
!= 0);
688 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.MtrrTable
, (VOID
*)(UINTN
)AcpiCpuData
->MtrrTable
, sizeof (MTRR_SETTINGS
));
690 mAcpiCpuData
.GdtrProfile
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (IA32_DESCRIPTOR
));
691 ASSERT (mAcpiCpuData
.GdtrProfile
!= 0);
693 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.GdtrProfile
, (VOID
*)(UINTN
)AcpiCpuData
->GdtrProfile
, sizeof (IA32_DESCRIPTOR
));
695 mAcpiCpuData
.IdtrProfile
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (IA32_DESCRIPTOR
));
696 ASSERT (mAcpiCpuData
.IdtrProfile
!= 0);
698 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.IdtrProfile
, (VOID
*)(UINTN
)AcpiCpuData
->IdtrProfile
, sizeof (IA32_DESCRIPTOR
));
700 mAcpiCpuData
.PreSmmInitRegisterTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (mAcpiCpuData
.NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
701 ASSERT (mAcpiCpuData
.PreSmmInitRegisterTable
!= 0);
704 (CPU_REGISTER_TABLE
*)(UINTN
)mAcpiCpuData
.PreSmmInitRegisterTable
,
705 (CPU_REGISTER_TABLE
*)(UINTN
)AcpiCpuData
->PreSmmInitRegisterTable
,
706 mAcpiCpuData
.NumberOfCpus
709 mAcpiCpuData
.RegisterTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (mAcpiCpuData
.NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
710 ASSERT (mAcpiCpuData
.RegisterTable
!= 0);
713 (CPU_REGISTER_TABLE
*)(UINTN
)mAcpiCpuData
.RegisterTable
,
714 (CPU_REGISTER_TABLE
*)(UINTN
)AcpiCpuData
->RegisterTable
,
715 mAcpiCpuData
.NumberOfCpus
719 // Copy AP's GDT, IDT and Machine Check handler into SMRAM.
721 Gdtr
= (IA32_DESCRIPTOR
*)(UINTN
)mAcpiCpuData
.GdtrProfile
;
722 Idtr
= (IA32_DESCRIPTOR
*)(UINTN
)mAcpiCpuData
.IdtrProfile
;
724 mGdtForAp
= AllocatePool ((Gdtr
->Limit
+ 1) + (Idtr
->Limit
+ 1) + mAcpiCpuData
.ApMachineCheckHandlerSize
);
725 ASSERT (mGdtForAp
!= NULL
);
726 mIdtForAp
= (VOID
*) ((UINTN
)mGdtForAp
+ (Gdtr
->Limit
+ 1));
727 mMachineCheckHandlerForAp
= (VOID
*) ((UINTN
)mIdtForAp
+ (Idtr
->Limit
+ 1));
729 CopyMem (mGdtForAp
, (VOID
*)Gdtr
->Base
, Gdtr
->Limit
+ 1);
730 CopyMem (mIdtForAp
, (VOID
*)Idtr
->Base
, Idtr
->Limit
+ 1);
731 CopyMem (mMachineCheckHandlerForAp
, (VOID
*)(UINTN
)mAcpiCpuData
.ApMachineCheckHandlerBase
, mAcpiCpuData
.ApMachineCheckHandlerSize
);
735 // Set SMM ready to lock flag and return
737 mSmmReadyToLock
= TRUE
;
742 The module Entry Point of the CPU SMM driver.
744 @param ImageHandle The firmware allocated handle for the EFI image.
745 @param SystemTable A pointer to the EFI System Table.
747 @retval EFI_SUCCESS The entry point is executed successfully.
748 @retval Other Some error occurs when executing this entry point.
754 IN EFI_HANDLE ImageHandle
,
755 IN EFI_SYSTEM_TABLE
*SystemTable
759 EFI_MP_SERVICES_PROTOCOL
*MpServices
;
760 UINTN NumberOfEnabledProcessors
;
765 EFI_SMRAM_DESCRIPTOR
*SmramDescriptor
;
766 SMM_S3_RESUME_STATE
*SmmS3ResumeState
;
776 // Initialize Debug Agent to support source level debug in SMM code
778 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM
, NULL
, NULL
);
781 // Report the start of CPU SMM initialization.
785 EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_INIT
789 // Fix segment address of the long-mode-switch jump
791 if (sizeof (UINTN
) == sizeof (UINT64
)) {
792 gSmmJmpAddr
.Segment
= LONG_MODE_CODE_SEGMENT
;
796 // Find out SMRR Base and SMRR Size
798 FindSmramInfo (&mCpuHotPlugData
.SmrrBase
, &mCpuHotPlugData
.SmrrSize
);
801 // Get MP Services Protocol
803 Status
= SystemTable
->BootServices
->LocateProtocol (&gEfiMpServiceProtocolGuid
, NULL
, (VOID
**)&MpServices
);
804 ASSERT_EFI_ERROR (Status
);
807 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
809 Status
= MpServices
->GetNumberOfProcessors (MpServices
, &mNumberOfCpus
, &NumberOfEnabledProcessors
);
810 ASSERT_EFI_ERROR (Status
);
811 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
814 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
815 // A constant BSP index makes no sense because it may be hot removed.
818 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
820 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection
));
825 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
827 mSmmCodeAccessCheckEnable
= PcdGetBool (PcdCpuSmmCodeAccessCheckEnable
);
828 DEBUG ((EFI_D_INFO
, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable
));
831 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
833 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
834 mMaxNumberOfCpus
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
836 mMaxNumberOfCpus
= mNumberOfCpus
;
838 gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
= mMaxNumberOfCpus
;
841 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
842 // allocated buffer. The minimum size of this buffer for a uniprocessor system
843 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
844 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
845 // then the SMI entry point and the CPU save state areas can be tiles to minimize
846 // the total amount SMRAM required for all the CPUs. The tile size can be computed
847 // by adding the // CPU save state size, any extra CPU specific context, and
848 // the size of code that must be placed at the SMI entry point to transfer
849 // control to a C function in the native SMM execution mode. This size is
850 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
851 // The total amount of memory required is the maximum number of CPUs that
852 // platform supports times the tile size. The picture below shows the tiling,
853 // where m is the number of tiles that fit in 32KB.
855 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
856 // | CPU m+1 Save State |
857 // +-----------------------------+
858 // | CPU m+1 Extra Data |
859 // +-----------------------------+
861 // +-----------------------------+
862 // | CPU 2m SMI Entry |
863 // +#############################+ <-- Base of allocated buffer + 64 KB
864 // | CPU m-1 Save State |
865 // +-----------------------------+
866 // | CPU m-1 Extra Data |
867 // +-----------------------------+
869 // +-----------------------------+
870 // | CPU 2m-1 SMI Entry |
871 // +=============================+ <-- 2^n offset from Base of allocated buffer
872 // | . . . . . . . . . . . . |
873 // +=============================+ <-- 2^n offset from Base of allocated buffer
874 // | CPU 2 Save State |
875 // +-----------------------------+
876 // | CPU 2 Extra Data |
877 // +-----------------------------+
879 // +-----------------------------+
880 // | CPU m+1 SMI Entry |
881 // +=============================+ <-- Base of allocated buffer + 32 KB
882 // | CPU 1 Save State |
883 // +-----------------------------+
884 // | CPU 1 Extra Data |
885 // +-----------------------------+
887 // +-----------------------------+
888 // | CPU m SMI Entry |
889 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
890 // | CPU 0 Save State |
891 // +-----------------------------+
892 // | CPU 0 Extra Data |
893 // +-----------------------------+
895 // +-----------------------------+
896 // | CPU m-1 SMI Entry |
897 // +=============================+ <-- 2^n offset from Base of allocated buffer
898 // | . . . . . . . . . . . . |
899 // +=============================+ <-- 2^n offset from Base of allocated buffer
901 // +-----------------------------+
902 // | CPU 1 SMI Entry |
903 // +=============================+ <-- 2^n offset from Base of allocated buffer
905 // +-----------------------------+
906 // | CPU 0 SMI Entry |
907 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
911 // Retrieve CPU Family
913 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, &RegEdx
);
914 FamilyId
= (RegEax
>> 8) & 0xf;
915 ModelId
= (RegEax
>> 4) & 0xf;
916 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
917 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
921 // Determine the mode of the CPU at the time an SMI occurs
922 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
923 // Volume 3C, Section 34.4.1.1
925 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
;
926 if ((RegEdx
& BIT29
) != 0) {
927 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
929 if (FamilyId
== 0x06) {
930 if (ModelId
== 0x17 || ModelId
== 0x0f || ModelId
== 0x1c) {
931 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
936 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
937 // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size
938 // is rounded up to nearest power of 2.
940 TileSize
= sizeof (SMRAM_SAVE_STATE_MAP
) + sizeof (PROCESSOR_SMM_DESCRIPTOR
) + GetSmiHandlerSize () - 1;
941 TileSize
= 2 * GetPowerOfTwo32 ((UINT32
)TileSize
);
942 DEBUG ((EFI_D_INFO
, "SMRAM TileSize = %08x\n", TileSize
));
945 // If the TileSize is larger than space available for the SMI Handler of CPU[i],
946 // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
947 // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be
950 ASSERT (TileSize
<= (SMRAM_SAVE_STATE_MAP_OFFSET
+ sizeof (SMRAM_SAVE_STATE_MAP
) - SMM_HANDLER_OFFSET
));
953 // Allocate buffer for all of the tiles.
955 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
956 // Volume 3C, Section 34.11 SMBASE Relocation
957 // For Pentium and Intel486 processors, the SMBASE values must be
958 // aligned on a 32-KByte boundary or the processor will enter shutdown
959 // state during the execution of a RSM instruction.
961 // Intel486 processors: FamilyId is 4
962 // Pentium processors : FamilyId is 5
964 if ((FamilyId
== 4) || (FamilyId
== 5)) {
965 Buffer
= AllocateAlignedPages (EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1)), SIZE_32KB
);
967 Buffer
= AllocatePages (EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1)));
969 ASSERT (Buffer
!= NULL
);
972 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
974 gSmmCpuPrivate
->ProcessorInfo
= (EFI_PROCESSOR_INFORMATION
*)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION
) * mMaxNumberOfCpus
);
975 ASSERT (gSmmCpuPrivate
->ProcessorInfo
!= NULL
);
977 gSmmCpuPrivate
->Operation
= (SMM_CPU_OPERATION
*)AllocatePool (sizeof (SMM_CPU_OPERATION
) * mMaxNumberOfCpus
);
978 ASSERT (gSmmCpuPrivate
->Operation
!= NULL
);
980 gSmmCpuPrivate
->CpuSaveStateSize
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
981 ASSERT (gSmmCpuPrivate
->CpuSaveStateSize
!= NULL
);
983 gSmmCpuPrivate
->CpuSaveState
= (VOID
**)AllocatePool (sizeof (VOID
*) * mMaxNumberOfCpus
);
984 ASSERT (gSmmCpuPrivate
->CpuSaveState
!= NULL
);
986 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveStateSize
= gSmmCpuPrivate
->CpuSaveStateSize
;
987 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveState
= gSmmCpuPrivate
->CpuSaveState
;
990 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
992 mCpuHotPlugData
.ApicId
= (UINT64
*)AllocatePool (sizeof (UINT64
) * mMaxNumberOfCpus
);
993 ASSERT (mCpuHotPlugData
.ApicId
!= NULL
);
994 mCpuHotPlugData
.SmBase
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
995 ASSERT (mCpuHotPlugData
.SmBase
!= NULL
);
996 mCpuHotPlugData
.ArrayLength
= (UINT32
)mMaxNumberOfCpus
;
999 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
1000 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
1001 // size for each CPU in the platform
1003 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
1004 mCpuHotPlugData
.SmBase
[Index
] = (UINTN
)Buffer
+ Index
* TileSize
- SMM_HANDLER_OFFSET
;
1005 gSmmCpuPrivate
->CpuSaveStateSize
[Index
] = sizeof(SMRAM_SAVE_STATE_MAP
);
1006 gSmmCpuPrivate
->CpuSaveState
[Index
] = (VOID
*)(mCpuHotPlugData
.SmBase
[Index
] + SMRAM_SAVE_STATE_MAP_OFFSET
);
1007 gSmmCpuPrivate
->Operation
[Index
] = SmmCpuNone
;
1009 if (Index
< mNumberOfCpus
) {
1010 Status
= MpServices
->GetProcessorInfo (MpServices
, Index
, &gSmmCpuPrivate
->ProcessorInfo
[Index
]);
1011 ASSERT_EFI_ERROR (Status
);
1012 mCpuHotPlugData
.ApicId
[Index
] = gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
;
1014 DEBUG ((EFI_D_INFO
, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
1016 (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
,
1017 mCpuHotPlugData
.SmBase
[Index
],
1018 gSmmCpuPrivate
->CpuSaveState
[Index
],
1019 gSmmCpuPrivate
->CpuSaveStateSize
[Index
]
1022 gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
= INVALID_APIC_ID
;
1023 mCpuHotPlugData
.ApicId
[Index
] = INVALID_APIC_ID
;
1028 // Allocate SMI stacks for all processors.
1030 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
1032 // 2 more pages is allocated for each processor.
1033 // one is guard page and the other is known good stack.
1035 // +-------------------------------------------+-----+-------------------------------------------+
1036 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
1037 // +-------------------------------------------+-----+-------------------------------------------+
1039 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
1041 mSmmStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2);
1042 Stacks
= (UINT8
*) AllocatePages (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2));
1043 ASSERT (Stacks
!= NULL
);
1044 mSmmStackArrayBase
= (UINTN
)Stacks
;
1045 mSmmStackArrayEnd
= mSmmStackArrayBase
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
- 1;
1047 mSmmStackSize
= PcdGet32 (PcdCpuSmmStackSize
);
1048 Stacks
= (UINT8
*) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
));
1049 ASSERT (Stacks
!= NULL
);
1053 // Set SMI stack for SMM base relocation
1055 gSmmInitStack
= (UINTN
) (Stacks
+ mSmmStackSize
- sizeof (UINTN
));
1060 InitializeSmmIdt ();
1063 // Relocate SMM Base addresses to the ones allocated from SMRAM
1065 mRebased
= (BOOLEAN
*)AllocateZeroPool (sizeof (BOOLEAN
) * mMaxNumberOfCpus
);
1066 ASSERT (mRebased
!= NULL
);
1067 SmmRelocateBases ();
1070 // Call hook for BSP to perform extra actions in normal mode after all
1071 // SMM base addresses have been relocated on all CPUs
1073 SmmCpuFeaturesSmmRelocationComplete ();
1076 // SMM Time initialization
1078 InitializeSmmTimer ();
1081 // Initialize MP globals
1083 Cr3
= InitializeMpServiceData (Stacks
, mSmmStackSize
);
1086 // Fill in SMM Reserved Regions
1088 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedStart
= 0;
1089 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedSize
= 0;
1092 // Install the SMM Configuration Protocol onto a new handle on the handle database.
1093 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
1094 // to an SMRAM address will be present in the handle database
1096 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
1097 &gSmmCpuPrivate
->SmmCpuHandle
,
1098 &gEfiSmmConfigurationProtocolGuid
, &gSmmCpuPrivate
->SmmConfiguration
,
1101 ASSERT_EFI_ERROR (Status
);
1104 // Install the SMM CPU Protocol into SMM protocol database
1106 Status
= gSmst
->SmmInstallProtocolInterface (
1108 &gEfiSmmCpuProtocolGuid
,
1109 EFI_NATIVE_INTERFACE
,
1112 ASSERT_EFI_ERROR (Status
);
1115 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
1117 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
1118 Status
= PcdSet64S (PcdCpuHotPlugDataAddress
, (UINT64
)(UINTN
)&mCpuHotPlugData
);
1119 ASSERT_EFI_ERROR (Status
);
1123 // Initialize SMM CPU Services Support
1125 Status
= InitializeSmmCpuServices (mSmmCpuHandle
);
1126 ASSERT_EFI_ERROR (Status
);
1129 // register SMM Ready To Lock Protocol notification
1131 Status
= gSmst
->SmmRegisterProtocolNotify (
1132 &gEfiSmmReadyToLockProtocolGuid
,
1133 SmmReadyToLockEventNotify
,
1136 ASSERT_EFI_ERROR (Status
);
1138 GuidHob
= GetFirstGuidHob (&gEfiAcpiVariableGuid
);
1139 if (GuidHob
!= NULL
) {
1140 SmramDescriptor
= (EFI_SMRAM_DESCRIPTOR
*) GET_GUID_HOB_DATA (GuidHob
);
1142 DEBUG ((EFI_D_INFO
, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor
));
1143 DEBUG ((EFI_D_INFO
, "SMM S3 Structure = %x\n", SmramDescriptor
->CpuStart
));
1145 SmmS3ResumeState
= (SMM_S3_RESUME_STATE
*)(UINTN
)SmramDescriptor
->CpuStart
;
1146 ZeroMem (SmmS3ResumeState
, sizeof (SMM_S3_RESUME_STATE
));
1148 mSmmS3ResumeState
= SmmS3ResumeState
;
1149 SmmS3ResumeState
->Smst
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)gSmst
;
1151 SmmS3ResumeState
->SmmS3ResumeEntryPoint
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)SmmRestoreCpu
;
1153 SmmS3ResumeState
->SmmS3StackSize
= SIZE_32KB
;
1154 SmmS3ResumeState
->SmmS3StackBase
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN
)SmmS3ResumeState
->SmmS3StackSize
));
1155 if (SmmS3ResumeState
->SmmS3StackBase
== 0) {
1156 SmmS3ResumeState
->SmmS3StackSize
= 0;
1159 SmmS3ResumeState
->SmmS3Cr0
= gSmmCr0
;
1160 SmmS3ResumeState
->SmmS3Cr3
= Cr3
;
1161 SmmS3ResumeState
->SmmS3Cr4
= gSmmCr4
;
1163 if (sizeof (UINTN
) == sizeof (UINT64
)) {
1164 SmmS3ResumeState
->Signature
= SMM_S3_RESUME_SMM_64
;
1166 if (sizeof (UINTN
) == sizeof (UINT32
)) {
1167 SmmS3ResumeState
->Signature
= SMM_S3_RESUME_SMM_32
;
1172 // Check XD and BTS features
1174 CheckProcessorFeature ();
1177 // Initialize SMM Profile feature
1179 InitSmmProfile (Cr3
);
1182 // Patch SmmS3ResumeState->SmmS3Cr3
1186 DEBUG ((EFI_D_INFO
, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
1193 Find out SMRAM information including SMRR base and SMRR size.
1195 @param SmrrBase SMRR base
1196 @param SmrrSize SMRR size
1201 OUT UINT32
*SmrrBase
,
1202 OUT UINT32
*SmrrSize
1207 EFI_SMM_ACCESS2_PROTOCOL
*SmmAccess
;
1208 EFI_SMRAM_DESCRIPTOR
*CurrentSmramRange
;
1209 EFI_SMRAM_DESCRIPTOR
*SmramRanges
;
1210 UINTN SmramRangeCount
;
1216 // Get SMM Access Protocol
1218 Status
= gBS
->LocateProtocol (&gEfiSmmAccess2ProtocolGuid
, NULL
, (VOID
**)&SmmAccess
);
1219 ASSERT_EFI_ERROR (Status
);
1222 // Get SMRAM information
1225 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, NULL
);
1226 ASSERT (Status
== EFI_BUFFER_TOO_SMALL
);
1228 SmramRanges
= (EFI_SMRAM_DESCRIPTOR
*)AllocatePool (Size
);
1229 ASSERT (SmramRanges
!= NULL
);
1231 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, SmramRanges
);
1232 ASSERT_EFI_ERROR (Status
);
1234 SmramRangeCount
= Size
/ sizeof (EFI_SMRAM_DESCRIPTOR
);
1237 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
1239 CurrentSmramRange
= NULL
;
1240 for (Index
= 0, MaxSize
= SIZE_256KB
- EFI_PAGE_SIZE
; Index
< SmramRangeCount
; Index
++) {
1242 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
1244 if ((SmramRanges
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
1248 if (SmramRanges
[Index
].CpuStart
>= BASE_1MB
) {
1249 if ((SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
) <= BASE_4GB
) {
1250 if (SmramRanges
[Index
].PhysicalSize
>= MaxSize
) {
1251 MaxSize
= SmramRanges
[Index
].PhysicalSize
;
1252 CurrentSmramRange
= &SmramRanges
[Index
];
1258 ASSERT (CurrentSmramRange
!= NULL
);
1260 *SmrrBase
= (UINT32
)CurrentSmramRange
->CpuStart
;
1261 *SmrrSize
= (UINT32
)CurrentSmramRange
->PhysicalSize
;
1265 for (Index
= 0; Index
< SmramRangeCount
; Index
++) {
1266 if (SmramRanges
[Index
].CpuStart
< *SmrrBase
&& *SmrrBase
== (SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
)) {
1267 *SmrrBase
= (UINT32
)SmramRanges
[Index
].CpuStart
;
1268 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1270 } else if ((*SmrrBase
+ *SmrrSize
) == SmramRanges
[Index
].CpuStart
&& SmramRanges
[Index
].PhysicalSize
> 0) {
1271 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1277 DEBUG ((EFI_D_INFO
, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase
, *SmrrSize
));
1281 Configure SMM Code Access Check feature on an AP.
1282 SMM Feature Control MSR will be locked after configuration.
1284 @param[in,out] Buffer Pointer to private data buffer.
1288 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1293 UINT64 SmmFeatureControlMsr
;
1294 UINT64 NewSmmFeatureControlMsr
;
1297 // Retrieve the CPU Index from the context passed in
1299 CpuIndex
= *(UINTN
*)Buffer
;
1302 // Get the current SMM Feature Control MSR value
1304 SmmFeatureControlMsr
= SmmCpuFeaturesGetSmmRegister (CpuIndex
, SmmRegFeatureControl
);
1307 // Compute the new SMM Feature Control MSR value
1309 NewSmmFeatureControlMsr
= SmmFeatureControlMsr
;
1310 if (mSmmCodeAccessCheckEnable
) {
1311 NewSmmFeatureControlMsr
|= SMM_CODE_CHK_EN_BIT
;
1313 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1314 NewSmmFeatureControlMsr
|= SMM_FEATURE_CONTROL_LOCK_BIT
;
1318 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1320 if (NewSmmFeatureControlMsr
!= SmmFeatureControlMsr
) {
1321 SmmCpuFeaturesSetSmmRegister (CpuIndex
, SmmRegFeatureControl
, NewSmmFeatureControlMsr
);
1325 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1327 ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock
);
1331 Configure SMM Code Access Check feature for all processors.
1332 SMM Feature Control MSR will be locked after configuration.
1335 ConfigSmmCodeAccessCheck (
1343 // Check to see if the Feature Control MSR is supported on this CPU
1345 Index
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1346 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index
, SmmRegFeatureControl
)) {
1347 mSmmCodeAccessCheckEnable
= FALSE
;
1352 // Check to see if the CPU supports the SMM Code Access Check feature
1353 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1355 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) == 0) {
1356 mSmmCodeAccessCheckEnable
= FALSE
;
1360 // If the SMM Code Access Check feature is disabled and the Feature Control MSR
1361 // is not being locked, then no additional work is required
1363 if (!mSmmCodeAccessCheckEnable
&& !FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1368 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1370 InitializeSpinLock (&mConfigSmmCodeAccessCheckLock
);
1373 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1374 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1376 AcquireSpinLock (&mConfigSmmCodeAccessCheckLock
);
1379 // Enable SMM Code Access Check feature on the BSP.
1381 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index
);
1384 // Enable SMM Code Access Check feature for the APs.
1386 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1387 if (Index
!= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
1390 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1391 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1393 AcquireSpinLock (&mConfigSmmCodeAccessCheckLock
);
1396 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1398 Status
= gSmst
->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor
, Index
, &Index
);
1399 ASSERT_EFI_ERROR (Status
);
1402 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1404 while (!AcquireSpinLockOrFail (&mConfigSmmCodeAccessCheckLock
)) {
1409 // Release the Config SMM Code Access Check spin lock.
1411 ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock
);
1417 Perform the remaining tasks.
1421 PerformRemainingTasks (
1425 if (mSmmReadyToLock
) {
1427 // Start SMM Profile feature
1429 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1433 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1437 // Configure SMM Code Access Check feature if available.
1439 ConfigSmmCodeAccessCheck ();
1442 // Clean SMM ready to lock flag
1444 mSmmReadyToLock
= FALSE
;