4 Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #include "PiSmmCpuDxeSmm.h"
12 #include "SmmProfileInternal.h"
14 UINT32 mSmmProfileCr3
;
16 SMM_PROFILE_HEADER
*mSmmProfileBase
;
17 MSR_DS_AREA_STRUCT
*mMsrDsAreaBase
;
19 // The buffer to store SMM profile data.
21 UINTN mSmmProfileSize
;
24 // The buffer to enable branch trace store.
26 UINTN mMsrDsAreaSize
= SMM_PROFILE_DTS_SIZE
;
29 // The flag indicates if execute-disable is supported by processor.
31 BOOLEAN mXdSupported
= TRUE
;
34 // The flag indicates if execute-disable is enabled on processor.
36 BOOLEAN mXdEnabled
= FALSE
;
39 // The flag indicates if BTS is supported by processor.
41 BOOLEAN mBtsSupported
= TRUE
;
44 // The flag indicates if SMM profile starts to record data.
46 BOOLEAN mSmmProfileStart
= FALSE
;
49 // The flag indicates if #DB will be setup in #PF handler.
51 BOOLEAN mSetupDebugTrap
= FALSE
;
54 // Record the page fault exception count for one instruction execution.
58 UINT64 (*mLastPFEntryValue
)[MAX_PF_ENTRY_COUNT
];
59 UINT64
*(*mLastPFEntryPointer
)[MAX_PF_ENTRY_COUNT
];
61 MSR_DS_AREA_STRUCT
**mMsrDsArea
;
62 BRANCH_TRACE_RECORD
**mMsrBTSRecord
;
63 UINTN mBTSRecordNumber
;
64 PEBS_RECORD
**mMsrPEBSRecord
;
67 // These memory ranges are always present, they does not generate the access type of page fault exception,
68 // but they possibly generate instruction fetch type of page fault exception.
70 MEMORY_PROTECTION_RANGE
*mProtectionMemRange
= NULL
;
71 UINTN mProtectionMemRangeCount
= 0;
74 // Some predefined memory ranges.
76 MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate
[] = {
78 // SMRAM range (to be fixed in runtime).
79 // It is always present and instruction fetches are allowed.
82 { 0x00000000, 0x00000000 }, TRUE
, FALSE
86 // SMM profile data range( to be fixed in runtime).
87 // It is always present and instruction fetches are not allowed.
90 { 0x00000000, 0x00000000 }, TRUE
, TRUE
94 // SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).
95 // It is always present and instruction fetches are allowed.
96 // {{0x00000000, 0x00000000},TRUE,FALSE},
100 // Future extended range could be added here.
104 // PCI MMIO ranges (to be added in runtime).
105 // They are always present and instruction fetches are not allowed.
110 // These memory ranges are mapped by 4KB-page instead of 2MB-page.
112 MEMORY_RANGE
*mSplitMemRange
= NULL
;
113 UINTN mSplitMemRangeCount
= 0;
118 UINT32 mSmiCommandPort
;
121 Disable branch trace store.
129 AsmMsrAnd64 (MSR_DEBUG_CTL
, ~((UINT64
)(MSR_DEBUG_CTL_BTS
| MSR_DEBUG_CTL_TR
)));
133 Enable branch trace store.
141 AsmMsrOr64 (MSR_DEBUG_CTL
, (MSR_DEBUG_CTL_BTS
| MSR_DEBUG_CTL_TR
));
145 Get CPU Index from APIC ID.
156 ApicId
= GetApicId ();
158 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
159 if (gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
== ApicId
) {
169 Get the source of IP after execute-disable exception is triggered.
171 @param CpuIndex The index of CPU.
172 @param DestinationIP The destination address.
176 GetSourceFromDestinationOnBts (
181 BRANCH_TRACE_RECORD
*CurrentBTSRecord
;
187 CurrentBTSRecord
= (BRANCH_TRACE_RECORD
*)mMsrDsArea
[CpuIndex
]->BTSIndex
;
188 for (Index
= 0; Index
< mBTSRecordNumber
; Index
++) {
189 if ((UINTN
)CurrentBTSRecord
< (UINTN
)mMsrBTSRecord
[CpuIndex
]) {
193 CurrentBTSRecord
= (BRANCH_TRACE_RECORD
*)((UINTN
)mMsrDsArea
[CpuIndex
]->BTSAbsoluteMaximum
- 1);
197 if (CurrentBTSRecord
->LastBranchTo
== DestinationIP
) {
199 // Good! find 1st one, then find 2nd one.
203 // The first one is DEBUG exception
208 // Good find proper one.
210 return CurrentBTSRecord
->LastBranchFrom
;
221 SMM profile specific INT 1 (single-step) exception handler.
223 @param InterruptType Defines the type of interrupt or exception that
224 occurred on the processor.This parameter is processor architecture specific.
225 @param SystemContext A pointer to the processor context when
226 the interrupt occurred on the processor.
230 DebugExceptionHandler (
231 IN EFI_EXCEPTION_TYPE InterruptType
,
232 IN EFI_SYSTEM_CONTEXT SystemContext
238 if (!mSmmProfileStart
&&
239 !HEAP_GUARD_NONSTOP_MODE
&&
240 !NULL_DETECTION_NONSTOP_MODE
)
245 CpuIndex
= GetCpuIndex ();
248 // Clear last PF entries
250 for (PFEntry
= 0; PFEntry
< mPFEntryCount
[CpuIndex
]; PFEntry
++) {
251 *mLastPFEntryPointer
[CpuIndex
][PFEntry
] = mLastPFEntryValue
[CpuIndex
][PFEntry
];
255 // Reset page fault exception count for next page fault.
257 mPFEntryCount
[CpuIndex
] = 0;
265 // Clear TF in EFLAGS
267 ClearTrapFlag (SystemContext
);
271 Check if the input address is in SMM ranges.
273 @param[in] Address The input address.
275 @retval TRUE The input address is in SMM.
276 @retval FALSE The input address is not in SMM.
280 IN EFI_PHYSICAL_ADDRESS Address
285 if ((Address
>= mCpuHotPlugData
.SmrrBase
) && (Address
< mCpuHotPlugData
.SmrrBase
+ mCpuHotPlugData
.SmrrSize
)) {
289 for (Index
= 0; Index
< mSmmCpuSmramRangeCount
; Index
++) {
290 if ((Address
>= mSmmCpuSmramRanges
[Index
].CpuStart
) &&
291 (Address
< mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
))
301 Check if the memory address will be mapped by 4KB-page.
303 @param Address The address of Memory.
304 @param Nx The flag indicates if the memory is execute-disable.
309 IN EFI_PHYSICAL_ADDRESS Address
,
315 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
317 // Check configuration
319 for (Index
= 0; Index
< mProtectionMemRangeCount
; Index
++) {
320 if ((Address
>= mProtectionMemRange
[Index
].Range
.Base
) && (Address
< mProtectionMemRange
[Index
].Range
.Top
)) {
321 *Nx
= mProtectionMemRange
[Index
].Nx
;
322 return mProtectionMemRange
[Index
].Present
;
330 if (IsInSmmRanges (Address
)) {
339 Check if the memory address will be mapped by 4KB-page.
341 @param Address The address of Memory.
346 IN EFI_PHYSICAL_ADDRESS Address
351 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
353 // Check configuration
355 for (Index
= 0; Index
< mSplitMemRangeCount
; Index
++) {
356 if ((Address
>= mSplitMemRange
[Index
].Base
) && (Address
< mSplitMemRange
[Index
].Top
)) {
361 if (Address
< mCpuHotPlugData
.SmrrBase
) {
362 if ((mCpuHotPlugData
.SmrrBase
- Address
) < BASE_2MB
) {
365 } else if (Address
> (mCpuHotPlugData
.SmrrBase
+ mCpuHotPlugData
.SmrrSize
- BASE_2MB
)) {
366 if ((Address
- (mCpuHotPlugData
.SmrrBase
+ mCpuHotPlugData
.SmrrSize
- BASE_2MB
)) < BASE_2MB
) {
379 Initialize the protected memory ranges and the 4KB-page mapped memory ranges.
383 InitProtectedMemRange (
388 UINTN NumberOfDescriptors
;
389 UINTN NumberOfAddedDescriptors
;
390 UINTN NumberOfProtectRange
;
391 UINTN NumberOfSpliteRange
;
392 EFI_GCD_MEMORY_SPACE_DESCRIPTOR
*MemorySpaceMap
;
394 EFI_PHYSICAL_ADDRESS ProtectBaseAddress
;
395 EFI_PHYSICAL_ADDRESS ProtectEndAddress
;
396 EFI_PHYSICAL_ADDRESS Top2MBAlignedAddress
;
397 EFI_PHYSICAL_ADDRESS Base2MBAlignedAddress
;
398 UINT64 High4KBPageSize
;
399 UINT64 Low4KBPageSize
;
401 NumberOfDescriptors
= 0;
402 NumberOfAddedDescriptors
= mSmmCpuSmramRangeCount
;
403 NumberOfSpliteRange
= 0;
404 MemorySpaceMap
= NULL
;
407 // Get MMIO ranges from GCD and add them into protected memory ranges.
409 gDS
->GetMemorySpaceMap (
410 &NumberOfDescriptors
,
413 for (Index
= 0; Index
< NumberOfDescriptors
; Index
++) {
414 if (MemorySpaceMap
[Index
].GcdMemoryType
== EfiGcdMemoryTypeMemoryMappedIo
) {
415 NumberOfAddedDescriptors
++;
419 if (NumberOfAddedDescriptors
!= 0) {
420 TotalSize
= NumberOfAddedDescriptors
* sizeof (MEMORY_PROTECTION_RANGE
) + sizeof (mProtectionMemRangeTemplate
);
421 mProtectionMemRange
= (MEMORY_PROTECTION_RANGE
*)AllocateZeroPool (TotalSize
);
422 ASSERT (mProtectionMemRange
!= NULL
);
423 mProtectionMemRangeCount
= TotalSize
/ sizeof (MEMORY_PROTECTION_RANGE
);
426 // Copy existing ranges.
428 CopyMem (mProtectionMemRange
, mProtectionMemRangeTemplate
, sizeof (mProtectionMemRangeTemplate
));
431 // Create split ranges which come from protected ranges.
433 TotalSize
= (TotalSize
/ sizeof (MEMORY_PROTECTION_RANGE
)) * sizeof (MEMORY_RANGE
);
434 mSplitMemRange
= (MEMORY_RANGE
*)AllocateZeroPool (TotalSize
);
435 ASSERT (mSplitMemRange
!= NULL
);
438 // Create SMM ranges which are set to present and execution-enable.
440 NumberOfProtectRange
= sizeof (mProtectionMemRangeTemplate
) / sizeof (MEMORY_PROTECTION_RANGE
);
441 for (Index
= 0; Index
< mSmmCpuSmramRangeCount
; Index
++) {
442 if ((mSmmCpuSmramRanges
[Index
].CpuStart
>= mProtectionMemRange
[0].Range
.Base
) &&
443 (mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
< mProtectionMemRange
[0].Range
.Top
))
446 // If the address have been already covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz
451 mProtectionMemRange
[NumberOfProtectRange
].Range
.Base
= mSmmCpuSmramRanges
[Index
].CpuStart
;
452 mProtectionMemRange
[NumberOfProtectRange
].Range
.Top
= mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
;
453 mProtectionMemRange
[NumberOfProtectRange
].Present
= TRUE
;
454 mProtectionMemRange
[NumberOfProtectRange
].Nx
= FALSE
;
455 NumberOfProtectRange
++;
459 // Create MMIO ranges which are set to present and execution-disable.
461 for (Index
= 0; Index
< NumberOfDescriptors
; Index
++) {
462 if (MemorySpaceMap
[Index
].GcdMemoryType
!= EfiGcdMemoryTypeMemoryMappedIo
) {
466 mProtectionMemRange
[NumberOfProtectRange
].Range
.Base
= MemorySpaceMap
[Index
].BaseAddress
;
467 mProtectionMemRange
[NumberOfProtectRange
].Range
.Top
= MemorySpaceMap
[Index
].BaseAddress
+ MemorySpaceMap
[Index
].Length
;
468 mProtectionMemRange
[NumberOfProtectRange
].Present
= TRUE
;
469 mProtectionMemRange
[NumberOfProtectRange
].Nx
= TRUE
;
470 NumberOfProtectRange
++;
474 // Check and updated actual protected memory ranges count
476 ASSERT (NumberOfProtectRange
<= mProtectionMemRangeCount
);
477 mProtectionMemRangeCount
= NumberOfProtectRange
;
481 // According to protected ranges, create the ranges which will be mapped by 2KB page.
483 NumberOfSpliteRange
= 0;
484 NumberOfProtectRange
= mProtectionMemRangeCount
;
485 for (Index
= 0; Index
< NumberOfProtectRange
; Index
++) {
487 // If MMIO base address is not 2MB alignment, make 2MB alignment for create 4KB page in page table.
489 ProtectBaseAddress
= mProtectionMemRange
[Index
].Range
.Base
;
490 ProtectEndAddress
= mProtectionMemRange
[Index
].Range
.Top
;
491 if (((ProtectBaseAddress
& (SIZE_2MB
- 1)) != 0) || ((ProtectEndAddress
& (SIZE_2MB
- 1)) != 0)) {
493 // Check if it is possible to create 4KB-page for not 2MB-aligned range and to create 2MB-page for 2MB-aligned range.
494 // A mix of 4KB and 2MB page could save SMRAM space.
496 Top2MBAlignedAddress
= ProtectEndAddress
& ~(SIZE_2MB
- 1);
497 Base2MBAlignedAddress
= (ProtectBaseAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1);
498 if ((Top2MBAlignedAddress
> Base2MBAlignedAddress
) &&
499 ((Top2MBAlignedAddress
- Base2MBAlignedAddress
) >= SIZE_2MB
))
502 // There is an range which could be mapped by 2MB-page.
504 High4KBPageSize
= ((ProtectEndAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1)) - (ProtectEndAddress
& ~(SIZE_2MB
- 1));
505 Low4KBPageSize
= ((ProtectBaseAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1)) - (ProtectBaseAddress
& ~(SIZE_2MB
- 1));
506 if (High4KBPageSize
!= 0) {
508 // Add not 2MB-aligned range to be mapped by 4KB-page.
510 mSplitMemRange
[NumberOfSpliteRange
].Base
= ProtectEndAddress
& ~(SIZE_2MB
- 1);
511 mSplitMemRange
[NumberOfSpliteRange
].Top
= (ProtectEndAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1);
512 NumberOfSpliteRange
++;
515 if (Low4KBPageSize
!= 0) {
517 // Add not 2MB-aligned range to be mapped by 4KB-page.
519 mSplitMemRange
[NumberOfSpliteRange
].Base
= ProtectBaseAddress
& ~(SIZE_2MB
- 1);
520 mSplitMemRange
[NumberOfSpliteRange
].Top
= (ProtectBaseAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1);
521 NumberOfSpliteRange
++;
525 // The range could only be mapped by 4KB-page.
527 mSplitMemRange
[NumberOfSpliteRange
].Base
= ProtectBaseAddress
& ~(SIZE_2MB
- 1);
528 mSplitMemRange
[NumberOfSpliteRange
].Top
= (ProtectEndAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1);
529 NumberOfSpliteRange
++;
534 mSplitMemRangeCount
= NumberOfSpliteRange
;
536 DEBUG ((DEBUG_INFO
, "SMM Profile Memory Ranges:\n"));
537 for (Index
= 0; Index
< mProtectionMemRangeCount
; Index
++) {
538 DEBUG ((DEBUG_INFO
, "mProtectionMemRange[%d].Base = %lx\n", Index
, mProtectionMemRange
[Index
].Range
.Base
));
539 DEBUG ((DEBUG_INFO
, "mProtectionMemRange[%d].Top = %lx\n", Index
, mProtectionMemRange
[Index
].Range
.Top
));
542 for (Index
= 0; Index
< mSplitMemRangeCount
; Index
++) {
543 DEBUG ((DEBUG_INFO
, "mSplitMemRange[%d].Base = %lx\n", Index
, mSplitMemRange
[Index
].Base
));
544 DEBUG ((DEBUG_INFO
, "mSplitMemRange[%d].Top = %lx\n", Index
, mSplitMemRange
[Index
].Top
));
549 Update page table according to protected memory ranges and the 4KB-page mapped memory ranges.
570 UINTN NumberOfPdptEntries
;
571 UINTN NumberOfPml4Entries
;
572 UINTN NumberOfPml5Entries
;
573 UINTN SizeOfMemorySpace
;
576 BOOLEAN Enable5LevelPaging
;
578 Cr4
.UintN
= AsmReadCr4 ();
579 Enable5LevelPaging
= (BOOLEAN
)(Cr4
.Bits
.LA57
== 1);
581 if (sizeof (UINTN
) == sizeof (UINT64
)) {
582 if (!Enable5LevelPaging
) {
583 Pml5Entry
= (UINTN
)mSmmProfileCr3
| IA32_PG_P
;
586 Pml5
= (UINT64
*)(UINTN
)mSmmProfileCr3
;
589 SizeOfMemorySpace
= HighBitSet64 (gPhyMask
) + 1;
591 // Calculate the table entries of PML4E and PDPTE.
593 NumberOfPml5Entries
= 1;
594 if (SizeOfMemorySpace
> 48) {
595 NumberOfPml5Entries
= (UINTN
)LShiftU64 (1, SizeOfMemorySpace
- 48);
596 SizeOfMemorySpace
= 48;
599 NumberOfPml4Entries
= 1;
600 if (SizeOfMemorySpace
> 39) {
601 NumberOfPml4Entries
= (UINTN
)LShiftU64 (1, SizeOfMemorySpace
- 39);
602 SizeOfMemorySpace
= 39;
605 NumberOfPdptEntries
= 1;
606 ASSERT (SizeOfMemorySpace
> 30);
607 NumberOfPdptEntries
= (UINTN
)LShiftU64 (1, SizeOfMemorySpace
- 30);
609 Pml4Entry
= (UINTN
)mSmmProfileCr3
| IA32_PG_P
;
611 Pml5Entry
= (UINTN
)Pml4
| IA32_PG_P
;
613 NumberOfPml5Entries
= 1;
614 NumberOfPml4Entries
= 1;
615 NumberOfPdptEntries
= 4;
619 // Go through page table and change 2MB-page into 4KB-page.
621 for (Pml5Index
= 0; Pml5Index
< NumberOfPml5Entries
; Pml5Index
++) {
622 if ((Pml5
[Pml5Index
] & IA32_PG_P
) == 0) {
624 // If PML5 entry does not exist, skip it
629 Pml4
= (UINT64
*)(UINTN
)(Pml5
[Pml5Index
] & PHYSICAL_ADDRESS_MASK
);
630 for (Pml4Index
= 0; Pml4Index
< NumberOfPml4Entries
; Pml4Index
++) {
631 if ((Pml4
[Pml4Index
] & IA32_PG_P
) == 0) {
633 // If PML4 entry does not exist, skip it
638 Pdpt
= (UINT64
*)(UINTN
)(Pml4
[Pml4Index
] & ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
639 for (PdptIndex
= 0; PdptIndex
< NumberOfPdptEntries
; PdptIndex
++, Pdpt
++) {
640 if ((*Pdpt
& IA32_PG_P
) == 0) {
642 // If PDPT entry does not exist, skip it
647 if ((*Pdpt
& IA32_PG_PS
) != 0) {
649 // This is 1G entry, skip it
654 Pd
= (UINT64
*)(UINTN
)(*Pdpt
& ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
659 for (PdIndex
= 0; PdIndex
< SIZE_4KB
/ sizeof (*Pd
); PdIndex
++, Pd
++) {
660 if ((*Pd
& IA32_PG_P
) == 0) {
662 // If PD entry does not exist, skip it
667 Address
= (UINTN
)LShiftU64 (
669 LShiftU64 ((Pml5Index
<< 9) + Pml4Index
, 9) + PdptIndex
,
676 // If it is 2M page, check IsAddressSplit()
678 if (((*Pd
& IA32_PG_PS
) != 0) && IsAddressSplit (Address
)) {
680 // Based on current page table, create 4KB page table for split area.
682 ASSERT (Address
== (*Pd
& PHYSICAL_ADDRESS_MASK
));
684 Pt
= AllocatePageTableMemory (1);
688 for (PtIndex
= 0; PtIndex
< SIZE_4KB
/ sizeof (*Pt
); PtIndex
++) {
689 Pt
[PtIndex
] = Address
+ ((PtIndex
<< 12) | mAddressEncMask
| PAGE_ATTRIBUTE_BITS
);
692 *Pd
= (UINT64
)(UINTN
)Pt
| mAddressEncMask
| PAGE_ATTRIBUTE_BITS
;
693 } // end if IsAddressSplit
700 // Go through page table and set several page table entries to absent or execute-disable.
702 DEBUG ((DEBUG_INFO
, "Patch page table start ...\n"));
703 for (Pml5Index
= 0; Pml5Index
< NumberOfPml5Entries
; Pml5Index
++) {
704 if ((Pml5
[Pml5Index
] & IA32_PG_P
) == 0) {
706 // If PML5 entry does not exist, skip it
711 Pml4
= (UINT64
*)(UINTN
)(Pml5
[Pml5Index
] & PHYSICAL_ADDRESS_MASK
);
712 for (Pml4Index
= 0; Pml4Index
< NumberOfPml4Entries
; Pml4Index
++) {
713 if ((Pml4
[Pml4Index
] & IA32_PG_P
) == 0) {
715 // If PML4 entry does not exist, skip it
720 Pdpt
= (UINT64
*)(UINTN
)(Pml4
[Pml4Index
] & ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
721 for (PdptIndex
= 0; PdptIndex
< NumberOfPdptEntries
; PdptIndex
++, Pdpt
++) {
722 if ((*Pdpt
& IA32_PG_P
) == 0) {
724 // If PDPT entry does not exist, skip it
729 if ((*Pdpt
& IA32_PG_PS
) != 0) {
731 // This is 1G entry, set NX bit and skip it
734 *Pdpt
= *Pdpt
| IA32_PG_NX
;
740 Pd
= (UINT64
*)(UINTN
)(*Pdpt
& ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
745 for (PdIndex
= 0; PdIndex
< SIZE_4KB
/ sizeof (*Pd
); PdIndex
++, Pd
++) {
746 if ((*Pd
& IA32_PG_P
) == 0) {
748 // If PD entry does not exist, skip it
753 Address
= (UINTN
)LShiftU64 (
755 LShiftU64 ((Pml5Index
<< 9) + Pml4Index
, 9) + PdptIndex
,
761 if ((*Pd
& IA32_PG_PS
) != 0) {
764 if (!IsAddressValid (Address
, &Nx
)) {
766 // Patch to remove Present flag and RW flag
768 *Pd
= *Pd
& (INTN
)(INT32
)(~PAGE_ATTRIBUTE_BITS
);
771 if (Nx
&& mXdSupported
) {
772 *Pd
= *Pd
| IA32_PG_NX
;
776 Pt
= (UINT64
*)(UINTN
)(*Pd
& ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
781 for (PtIndex
= 0; PtIndex
< SIZE_4KB
/ sizeof (*Pt
); PtIndex
++, Pt
++) {
782 if (!IsAddressValid (Address
, &Nx
)) {
783 *Pt
= *Pt
& (INTN
)(INT32
)(~PAGE_ATTRIBUTE_BITS
);
786 if (Nx
&& mXdSupported
) {
787 *Pt
= *Pt
| IA32_PG_NX
;
802 DEBUG ((DEBUG_INFO
, "Patch page table done!\n"));
804 // Set execute-disable flag
812 To get system port address of the SMI Command Port in FADT table.
820 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE
*Fadt
;
822 Fadt
= (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE
*)EfiLocateFirstAcpiTable (
823 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE
825 ASSERT (Fadt
!= NULL
);
827 mSmiCommandPort
= Fadt
->SmiCmd
;
828 DEBUG ((DEBUG_INFO
, "mSmiCommandPort = %x\n", mSmiCommandPort
));
832 Updates page table to make some memory ranges (like system memory) absent
833 and make some memory ranges (like MMIO) present and execute disable. It also
834 update 2MB-page to 4KB-page for some memory ranges.
843 // The flag indicates SMM profile starts to work.
845 mSmmProfileStart
= TRUE
;
849 Initialize SMM profile in SmmReadyToLock protocol callback function.
851 @param Protocol Points to the protocol's unique identifier.
852 @param Interface Points to the interface instance.
853 @param Handle The handle on which the interface was installed.
855 @retval EFI_SUCCESS SmmReadyToLock protocol callback runs successfully.
859 InitSmmProfileCallBack (
860 IN CONST EFI_GUID
*Protocol
,
866 // Save to variable so that SMM profile data can be found.
871 EFI_VARIABLE_BOOTSERVICE_ACCESS
| EFI_VARIABLE_RUNTIME_ACCESS
,
872 sizeof (mSmmProfileBase
),
877 // Get Software SMI from FADT
879 GetSmiCommandPort ();
882 // Initialize protected memory range for patching page table later.
884 InitProtectedMemRange ();
890 Initialize SMM profile data structures.
894 InitSmmProfileInternal (
899 EFI_PHYSICAL_ADDRESS Base
;
902 UINTN MsrDsAreaSizePerCpu
;
905 mPFEntryCount
= (UINTN
*)AllocateZeroPool (sizeof (UINTN
) * mMaxNumberOfCpus
);
906 ASSERT (mPFEntryCount
!= NULL
);
907 mLastPFEntryValue
= (UINT64 (*)[MAX_PF_ENTRY_COUNT
])AllocateZeroPool (
908 sizeof (mLastPFEntryValue
[0]) * mMaxNumberOfCpus
910 ASSERT (mLastPFEntryValue
!= NULL
);
911 mLastPFEntryPointer
= (UINT64
*(*)[MAX_PF_ENTRY_COUNT
])AllocateZeroPool (
912 sizeof (mLastPFEntryPointer
[0]) * mMaxNumberOfCpus
914 ASSERT (mLastPFEntryPointer
!= NULL
);
917 // Allocate memory for SmmProfile below 4GB.
920 mSmmProfileSize
= PcdGet32 (PcdCpuSmmProfileSize
);
921 ASSERT ((mSmmProfileSize
& 0xFFF) == 0);
924 TotalSize
= mSmmProfileSize
+ mMsrDsAreaSize
;
926 TotalSize
= mSmmProfileSize
;
930 Status
= gBS
->AllocatePages (
932 EfiReservedMemoryType
,
933 EFI_SIZE_TO_PAGES (TotalSize
),
936 ASSERT_EFI_ERROR (Status
);
937 ZeroMem ((VOID
*)(UINTN
)Base
, TotalSize
);
938 mSmmProfileBase
= (SMM_PROFILE_HEADER
*)(UINTN
)Base
;
941 // Initialize SMM profile data header.
943 mSmmProfileBase
->HeaderSize
= sizeof (SMM_PROFILE_HEADER
);
944 mSmmProfileBase
->MaxDataEntries
= (UINT64
)((mSmmProfileSize
- sizeof (SMM_PROFILE_HEADER
)) / sizeof (SMM_PROFILE_ENTRY
));
945 mSmmProfileBase
->MaxDataSize
= MultU64x64 (mSmmProfileBase
->MaxDataEntries
, sizeof (SMM_PROFILE_ENTRY
));
946 mSmmProfileBase
->CurDataEntries
= 0;
947 mSmmProfileBase
->CurDataSize
= 0;
948 mSmmProfileBase
->TsegStart
= mCpuHotPlugData
.SmrrBase
;
949 mSmmProfileBase
->TsegSize
= mCpuHotPlugData
.SmrrSize
;
950 mSmmProfileBase
->NumSmis
= 0;
951 mSmmProfileBase
->NumCpus
= gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
;
954 mMsrDsArea
= (MSR_DS_AREA_STRUCT
**)AllocateZeroPool (sizeof (MSR_DS_AREA_STRUCT
*) * mMaxNumberOfCpus
);
955 ASSERT (mMsrDsArea
!= NULL
);
956 mMsrBTSRecord
= (BRANCH_TRACE_RECORD
**)AllocateZeroPool (sizeof (BRANCH_TRACE_RECORD
*) * mMaxNumberOfCpus
);
957 ASSERT (mMsrBTSRecord
!= NULL
);
958 mMsrPEBSRecord
= (PEBS_RECORD
**)AllocateZeroPool (sizeof (PEBS_RECORD
*) * mMaxNumberOfCpus
);
959 ASSERT (mMsrPEBSRecord
!= NULL
);
961 mMsrDsAreaBase
= (MSR_DS_AREA_STRUCT
*)((UINTN
)Base
+ mSmmProfileSize
);
962 MsrDsAreaSizePerCpu
= mMsrDsAreaSize
/ mMaxNumberOfCpus
;
963 mBTSRecordNumber
= (MsrDsAreaSizePerCpu
- sizeof (PEBS_RECORD
) * PEBS_RECORD_NUMBER
- sizeof (MSR_DS_AREA_STRUCT
)) / sizeof (BRANCH_TRACE_RECORD
);
964 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
965 mMsrDsArea
[Index
] = (MSR_DS_AREA_STRUCT
*)((UINTN
)mMsrDsAreaBase
+ MsrDsAreaSizePerCpu
* Index
);
966 mMsrBTSRecord
[Index
] = (BRANCH_TRACE_RECORD
*)((UINTN
)mMsrDsArea
[Index
] + sizeof (MSR_DS_AREA_STRUCT
));
967 mMsrPEBSRecord
[Index
] = (PEBS_RECORD
*)((UINTN
)mMsrDsArea
[Index
] + MsrDsAreaSizePerCpu
- sizeof (PEBS_RECORD
) * PEBS_RECORD_NUMBER
);
969 mMsrDsArea
[Index
]->BTSBufferBase
= (UINTN
)mMsrBTSRecord
[Index
];
970 mMsrDsArea
[Index
]->BTSIndex
= mMsrDsArea
[Index
]->BTSBufferBase
;
971 mMsrDsArea
[Index
]->BTSAbsoluteMaximum
= mMsrDsArea
[Index
]->BTSBufferBase
+ mBTSRecordNumber
* sizeof (BRANCH_TRACE_RECORD
) + 1;
972 mMsrDsArea
[Index
]->BTSInterruptThreshold
= mMsrDsArea
[Index
]->BTSAbsoluteMaximum
+ 1;
974 mMsrDsArea
[Index
]->PEBSBufferBase
= (UINTN
)mMsrPEBSRecord
[Index
];
975 mMsrDsArea
[Index
]->PEBSIndex
= mMsrDsArea
[Index
]->PEBSBufferBase
;
976 mMsrDsArea
[Index
]->PEBSAbsoluteMaximum
= mMsrDsArea
[Index
]->PEBSBufferBase
+ PEBS_RECORD_NUMBER
* sizeof (PEBS_RECORD
) + 1;
977 mMsrDsArea
[Index
]->PEBSInterruptThreshold
= mMsrDsArea
[Index
]->PEBSAbsoluteMaximum
+ 1;
981 mProtectionMemRange
= mProtectionMemRangeTemplate
;
982 mProtectionMemRangeCount
= sizeof (mProtectionMemRangeTemplate
) / sizeof (MEMORY_PROTECTION_RANGE
);
985 // Update TSeg entry.
987 mProtectionMemRange
[0].Range
.Base
= mCpuHotPlugData
.SmrrBase
;
988 mProtectionMemRange
[0].Range
.Top
= mCpuHotPlugData
.SmrrBase
+ mCpuHotPlugData
.SmrrSize
;
991 // Update SMM profile entry.
993 mProtectionMemRange
[1].Range
.Base
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)mSmmProfileBase
;
994 mProtectionMemRange
[1].Range
.Top
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)mSmmProfileBase
+ TotalSize
;
997 // Allocate memory reserved for creating 4KB pages.
999 InitPagesForPFHandler ();
1002 // Start SMM profile when SmmReadyToLock protocol is installed.
1004 Status
= gSmst
->SmmRegisterProtocolNotify (
1005 &gEfiSmmReadyToLockProtocolGuid
,
1006 InitSmmProfileCallBack
,
1009 ASSERT_EFI_ERROR (Status
);
1015 Check if feature is supported by a processor.
1019 CheckFeatureSupported (
1026 MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr
;
1028 if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask
) != 0) && mCetSupported
) {
1029 AsmCpuid (CPUID_SIGNATURE
, &RegEax
, NULL
, NULL
, NULL
);
1030 if (RegEax
>= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
) {
1031 AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO
, NULL
, NULL
, &RegEcx
, NULL
);
1032 if ((RegEcx
& CPUID_CET_SS
) == 0) {
1033 mCetSupported
= FALSE
;
1034 PatchInstructionX86 (mPatchCetSupported
, mCetSupported
, 1);
1037 mCetSupported
= FALSE
;
1038 PatchInstructionX86 (mPatchCetSupported
, mCetSupported
, 1);
1043 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
1044 if (RegEax
<= CPUID_EXTENDED_FUNCTION
) {
1046 // Extended CPUID functions are not supported on this processor.
1048 mXdSupported
= FALSE
;
1049 PatchInstructionX86 (gPatchXdSupported
, mXdSupported
, 1);
1052 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
1053 if ((RegEdx
& CPUID1_EDX_XD_SUPPORT
) == 0) {
1055 // Execute Disable Bit feature is not supported on this processor.
1057 mXdSupported
= FALSE
;
1058 PatchInstructionX86 (gPatchXdSupported
, mXdSupported
, 1);
1061 if (StandardSignatureIsAuthenticAMD ()) {
1063 // AMD processors do not support MSR_IA32_MISC_ENABLE
1065 PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported
, FALSE
, 1);
1069 if (mBtsSupported
) {
1070 AsmCpuid (CPUID_VERSION_INFO
, NULL
, NULL
, NULL
, &RegEdx
);
1071 if ((RegEdx
& CPUID1_EDX_BTS_AVAILABLE
) != 0) {
1073 // Per IA32 manuals:
1074 // When CPUID.1:EDX[21] is set, the following BTS facilities are available:
1075 // 1. The BTS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates the
1076 // availability of the BTS facilities, including the ability to set the BTS and
1077 // BTINT bits in the MSR_DEBUGCTLA MSR.
1078 // 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.
1080 MiscEnableMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_MISC_ENABLE
);
1081 if (MiscEnableMsr
.Bits
.BTS
== 1) {
1083 // BTS facilities is not supported if MSR_IA32_MISC_ENABLE.BTS bit is set.
1085 mBtsSupported
= FALSE
;
1096 ActivateSingleStepDB (
1102 Dr6
= AsmReadDr6 ();
1103 if ((Dr6
& DR6_SINGLE_STEP
) != 0) {
1107 Dr6
|= DR6_SINGLE_STEP
;
1122 DebugCtl
= AsmReadMsr64 (MSR_DEBUG_CTL
);
1123 if ((DebugCtl
& MSR_DEBUG_CTL_LBR
) != 0) {
1127 DebugCtl
|= MSR_DEBUG_CTL_LBR
;
1128 AsmWriteMsr64 (MSR_DEBUG_CTL
, DebugCtl
);
1132 Enable branch trace store.
1134 @param CpuIndex The index of the processor.
1144 DebugCtl
= AsmReadMsr64 (MSR_DEBUG_CTL
);
1145 if ((DebugCtl
& MSR_DEBUG_CTL_BTS
) != 0) {
1149 AsmWriteMsr64 (MSR_DS_AREA
, (UINT64
)(UINTN
)mMsrDsArea
[CpuIndex
]);
1150 DebugCtl
|= (UINT64
)(MSR_DEBUG_CTL_BTS
| MSR_DEBUG_CTL_TR
);
1151 DebugCtl
&= ~((UINT64
)MSR_DEBUG_CTL_BTINT
);
1152 AsmWriteMsr64 (MSR_DEBUG_CTL
, DebugCtl
);
1156 Increase SMI number in each SMI entry.
1160 SmmProfileRecordSmiNum (
1164 if (mSmmProfileStart
) {
1165 mSmmProfileBase
->NumSmis
++;
1170 Initialize processor environment for SMM profile.
1172 @param CpuIndex The index of the processor.
1176 ActivateSmmProfile (
1181 // Enable Single Step DB#
1183 ActivateSingleStepDB ();
1185 if (mBtsSupported
) {
1187 // We can not get useful information from LER, so we have to use BTS.
1194 ActivateBTS (CpuIndex
);
1199 Initialize SMM profile in SMM CPU entry point.
1201 @param[in] Cr3 The base address of the page tables to use in SMM.
1212 mSmmProfileCr3
= Cr3
;
1215 // Skip SMM profile initialization if feature is disabled
1217 if (!FeaturePcdGet (PcdCpuSmmProfileEnable
) &&
1218 !HEAP_GUARD_NONSTOP_MODE
&&
1219 !NULL_DETECTION_NONSTOP_MODE
)
1225 // Initialize SmmProfile here
1227 InitSmmProfileInternal ();
1230 // Initialize profile IDT.
1235 // Tell #PF handler to prepare a #DB subsequently.
1237 mSetupDebugTrap
= TRUE
;
1241 Update page table to map the memory correctly in order to make the instruction
1242 which caused page fault execute successfully. And it also save the original page
1243 table to be restored in single-step exception.
1245 @param PageTable PageTable Address.
1246 @param PFAddress The memory address which caused page fault exception.
1247 @param CpuIndex The index of the processor.
1248 @param ErrorCode The Error code of exception.
1252 RestorePageTableBelow4G (
1262 BOOLEAN Enable5LevelPaging
;
1264 Cr4
.UintN
= AsmReadCr4 ();
1265 Enable5LevelPaging
= (BOOLEAN
)(Cr4
.Bits
.LA57
== 1);
1270 if (Enable5LevelPaging
) {
1271 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 48, 56);
1272 ASSERT (PageTable
[PTIndex
] != 0);
1273 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
1279 if (sizeof (UINT64
) == sizeof (UINTN
)) {
1280 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 39, 47);
1281 ASSERT (PageTable
[PTIndex
] != 0);
1282 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
1288 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 30, 38);
1289 ASSERT (PageTable
[PTIndex
] != 0);
1290 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
1295 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 21, 29);
1296 if ((PageTable
[PTIndex
] & IA32_PG_PS
) != 0) {
1302 // Record old entries with non-present status
1303 // Old entries include the memory which instruction is at and the memory which instruction access.
1306 ASSERT (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
);
1307 if (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
) {
1308 PFIndex
= mPFEntryCount
[CpuIndex
];
1309 mLastPFEntryValue
[CpuIndex
][PFIndex
] = PageTable
[PTIndex
];
1310 mLastPFEntryPointer
[CpuIndex
][PFIndex
] = &PageTable
[PTIndex
];
1311 mPFEntryCount
[CpuIndex
]++;
1317 PageTable
[PTIndex
] = (PFAddress
& ~((1ull << 21) - 1));
1318 PageTable
[PTIndex
] |= (UINT64
)IA32_PG_PS
;
1319 PageTable
[PTIndex
] |= (UINT64
)PAGE_ATTRIBUTE_BITS
;
1320 if ((ErrorCode
& IA32_PF_EC_ID
) != 0) {
1321 PageTable
[PTIndex
] &= ~IA32_PG_NX
;
1327 ASSERT (PageTable
[PTIndex
] != 0);
1328 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
1333 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 12, 20);
1336 // Record old entries with non-present status
1337 // Old entries include the memory which instruction is at and the memory which instruction access.
1340 ASSERT (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
);
1341 if (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
) {
1342 PFIndex
= mPFEntryCount
[CpuIndex
];
1343 mLastPFEntryValue
[CpuIndex
][PFIndex
] = PageTable
[PTIndex
];
1344 mLastPFEntryPointer
[CpuIndex
][PFIndex
] = &PageTable
[PTIndex
];
1345 mPFEntryCount
[CpuIndex
]++;
1351 PageTable
[PTIndex
] = (PFAddress
& ~((1ull << 12) - 1));
1352 PageTable
[PTIndex
] |= (UINT64
)PAGE_ATTRIBUTE_BITS
;
1353 if ((ErrorCode
& IA32_PF_EC_ID
) != 0) {
1354 PageTable
[PTIndex
] &= ~IA32_PG_NX
;
1360 Handler for Page Fault triggered by Guard page.
1362 @param ErrorCode The Error code of exception.
1366 GuardPagePFHandler (
1372 UINT64 RestoreAddress
;
1373 UINTN RestorePageNumber
;
1376 PageTable
= (UINT64
*)AsmReadCr3 ();
1377 PFAddress
= AsmReadCr2 ();
1378 CpuIndex
= GetCpuIndex ();
1381 // Memory operation cross pages, like "rep mov" instruction, will cause
1382 // infinite loop between this and Debug Trap handler. We have to make sure
1383 // that current page and the page followed are both in PRESENT state.
1385 RestorePageNumber
= 2;
1386 RestoreAddress
= PFAddress
;
1387 while (RestorePageNumber
> 0) {
1388 RestorePageTableBelow4G (PageTable
, RestoreAddress
, CpuIndex
, ErrorCode
);
1389 RestoreAddress
+= EFI_PAGE_SIZE
;
1390 RestorePageNumber
--;
1400 The Page fault handler to save SMM profile data.
1402 @param Rip The RIP when exception happens.
1403 @param ErrorCode The Error code of exception.
1407 SmmProfilePFHandler (
1414 UINT64 RestoreAddress
;
1415 UINTN RestorePageNumber
;
1418 UINT64 InstructionAddress
;
1419 UINTN MaxEntryNumber
;
1420 UINTN CurrentEntryNumber
;
1421 BOOLEAN IsValidPFAddress
;
1422 SMM_PROFILE_ENTRY
*SmmProfileEntry
;
1426 EFI_SMM_SAVE_STATE_IO_INFO IoInfo
;
1428 if (!mSmmProfileStart
) {
1430 // If SMM profile does not start, call original page fault handler.
1432 SmiDefaultPFHandler ();
1436 if (mBtsSupported
) {
1440 IsValidPFAddress
= FALSE
;
1441 PageTable
= (UINT64
*)AsmReadCr3 ();
1442 PFAddress
= AsmReadCr2 ();
1443 CpuIndex
= GetCpuIndex ();
1446 // Memory operation cross pages, like "rep mov" instruction, will cause
1447 // infinite loop between this and Debug Trap handler. We have to make sure
1448 // that current page and the page followed are both in PRESENT state.
1450 RestorePageNumber
= 2;
1451 RestoreAddress
= PFAddress
;
1452 while (RestorePageNumber
> 0) {
1453 if (RestoreAddress
<= 0xFFFFFFFF) {
1454 RestorePageTableBelow4G (PageTable
, RestoreAddress
, CpuIndex
, ErrorCode
);
1456 RestorePageTableAbove4G (PageTable
, RestoreAddress
, CpuIndex
, ErrorCode
, &IsValidPFAddress
);
1459 RestoreAddress
+= EFI_PAGE_SIZE
;
1460 RestorePageNumber
--;
1463 if (!IsValidPFAddress
) {
1464 InstructionAddress
= Rip
;
1465 if (((ErrorCode
& IA32_PF_EC_ID
) != 0) && (mBtsSupported
)) {
1467 // If it is instruction fetch failure, get the correct IP from BTS.
1469 InstructionAddress
= GetSourceFromDestinationOnBts (CpuIndex
, Rip
);
1470 if (InstructionAddress
== 0) {
1472 // It indicates the instruction which caused page fault is not a jump instruction,
1473 // set instruction address same as the page fault address.
1475 InstructionAddress
= PFAddress
;
1480 // Indicate it is not software SMI
1482 SmiCommand
= 0xFFFFFFFFFFFFFFFFULL
;
1483 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1484 Status
= SmmReadSaveState (&mSmmCpu
, sizeof (IoInfo
), EFI_SMM_SAVE_STATE_REGISTER_IO
, Index
, &IoInfo
);
1485 if (EFI_ERROR (Status
)) {
1489 if (IoInfo
.IoPort
== mSmiCommandPort
) {
1491 // A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port.
1493 SoftSmiValue
= IoRead8 (mSmiCommandPort
);
1494 SmiCommand
= (UINT64
)SoftSmiValue
;
1499 SmmProfileEntry
= (SMM_PROFILE_ENTRY
*)(UINTN
)(mSmmProfileBase
+ 1);
1501 // Check if there is already a same entry in profile data.
1503 for (Index
= 0; Index
< (UINTN
)mSmmProfileBase
->CurDataEntries
; Index
++) {
1504 if ((SmmProfileEntry
[Index
].ErrorCode
== (UINT64
)ErrorCode
) &&
1505 (SmmProfileEntry
[Index
].Address
== PFAddress
) &&
1506 (SmmProfileEntry
[Index
].CpuNum
== (UINT64
)CpuIndex
) &&
1507 (SmmProfileEntry
[Index
].Instruction
== InstructionAddress
) &&
1508 (SmmProfileEntry
[Index
].SmiCmd
== SmiCommand
))
1511 // Same record exist, need not save again.
1517 if (Index
== mSmmProfileBase
->CurDataEntries
) {
1518 CurrentEntryNumber
= (UINTN
)mSmmProfileBase
->CurDataEntries
;
1519 MaxEntryNumber
= (UINTN
)mSmmProfileBase
->MaxDataEntries
;
1520 if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer
)) {
1521 CurrentEntryNumber
= CurrentEntryNumber
% MaxEntryNumber
;
1524 if (CurrentEntryNumber
< MaxEntryNumber
) {
1526 // Log the new entry
1528 SmmProfileEntry
[CurrentEntryNumber
].SmiNum
= mSmmProfileBase
->NumSmis
;
1529 SmmProfileEntry
[CurrentEntryNumber
].ErrorCode
= (UINT64
)ErrorCode
;
1530 SmmProfileEntry
[CurrentEntryNumber
].ApicId
= (UINT64
)GetApicId ();
1531 SmmProfileEntry
[CurrentEntryNumber
].CpuNum
= (UINT64
)CpuIndex
;
1532 SmmProfileEntry
[CurrentEntryNumber
].Address
= PFAddress
;
1533 SmmProfileEntry
[CurrentEntryNumber
].Instruction
= InstructionAddress
;
1534 SmmProfileEntry
[CurrentEntryNumber
].SmiCmd
= SmiCommand
;
1536 // Update current entry index and data size in the header.
1538 mSmmProfileBase
->CurDataEntries
++;
1539 mSmmProfileBase
->CurDataSize
= MultU64x64 (mSmmProfileBase
->CurDataEntries
, sizeof (SMM_PROFILE_ENTRY
));
1549 if (mBtsSupported
) {
1555 Replace INT1 exception handler to restore page table to absent/execute-disable state
1556 in order to trigger page fault again to save SMM profile data..
1566 Status
= SmmRegisterExceptionHandler (&mSmmCpuService
, EXCEPT_IA32_DEBUG
, DebugExceptionHandler
);
1567 ASSERT_EFI_ERROR (Status
);