2 SMM profile internal header file.
4 Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef _SMM_PROFILE_INTERNAL_H_
16 #define _SMM_PROFILE_INTERNAL_H_
18 #include <Protocol/SmmReadyToLock.h>
19 #include <Library/UefiRuntimeServicesTableLib.h>
20 #include <Library/DxeServicesTableLib.h>
21 #include <Library/CpuLib.h>
22 #include <IndustryStandard/Acpi.h>
24 #include "SmmProfileArch.h"
27 // Configure the SMM_PROFILE DTS region size
29 #define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M
31 #define MAX_PF_PAGE_COUNT 0x2
33 #define PEBS_RECORD_NUMBER 0x2
35 #define MAX_PF_ENTRY_COUNT 10
38 // This MACRO just enable unit test for the profile
42 #define IA32_PF_EC_ID (1u << 4)
44 #define SMM_PROFILE_NAME L"SmmProfileData"
47 // CPU generic definition
49 #define CPUID1_EDX_XD_SUPPORT 0x100000
50 #define MSR_EFER 0xc0000080
51 #define MSR_EFER_XD 0x800
53 #define CPUID1_EDX_BTS_AVAILABLE 0x200000
55 #define DR6_SINGLE_STEP 0x4000
56 #define RFLAG_TF 0x100
58 #define MSR_DEBUG_CTL 0x1D9
59 #define MSR_DEBUG_CTL_LBR 0x1
60 #define MSR_DEBUG_CTL_TR 0x40
61 #define MSR_DEBUG_CTL_BTS 0x80
62 #define MSR_DEBUG_CTL_BTINT 0x100
63 #define MSR_DS_AREA 0x600
65 #define HEAP_GUARD_NONSTOP_MODE \
66 ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)
68 #define NULL_DETECTION_NONSTOP_MODE \
69 ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)
72 EFI_PHYSICAL_ADDRESS Base
;
73 EFI_PHYSICAL_ADDRESS Top
;
80 } MEMORY_PROTECTION_RANGE
;
84 UINT64 MaxDataEntries
;
86 UINT64 CurDataEntries
;
104 extern SMM_S3_RESUME_STATE
*mSmmS3ResumeState
;
105 extern UINTN gSmiExceptionHandlers
[];
106 extern BOOLEAN mXdSupported
;
107 X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported
;
108 extern UINTN
*mPFEntryCount
;
109 extern UINT64 (*mLastPFEntryValue
)[MAX_PF_ENTRY_COUNT
];
110 extern UINT64
*(*mLastPFEntryPointer
)[MAX_PF_ENTRY_COUNT
];
113 // Internal functions
117 Update IDT table to replace page fault handler and INT 1 handler.
126 Check if the memory address will be mapped by 4KB-page.
128 @param Address The address of Memory.
133 IN EFI_PHYSICAL_ADDRESS Address
137 Check if the memory address will be mapped by 4KB-page.
139 @param Address The address of Memory.
140 @param Nx The flag indicates if the memory is execute-disable.
145 IN EFI_PHYSICAL_ADDRESS Address
,
150 Page Fault handler for SMM use.
154 SmiDefaultPFHandler (
161 @param SystemContext A pointer to the processor context when
162 the interrupt occurred on the processor.
167 IN OUT EFI_SYSTEM_CONTEXT SystemContext
170 #endif // _SMM_PROFILE_H_