1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Code template of the SMI handler for a particular processor
19 ;-------------------------------------------------------------------------------
22 ; Variables referenced by C code
24 EXTERNDEF SmiRendezvous:PROC
25 EXTERNDEF CpuSmmDebugEntry:PROC
26 EXTERNDEF CpuSmmDebugExit:PROC
27 EXTERNDEF gcSmiHandlerTemplate:BYTE
28 EXTERNDEF gcSmiHandlerSize:WORD
29 EXTERNDEF gSmiCr3:DWORD
30 EXTERNDEF gSmiStack:DWORD
31 EXTERNDEF gSmbase:DWORD
32 EXTERNDEF mXdSupported:BYTE
33 EXTERNDEF gSmiHandlerIdtr:FWORD
35 MSR_IA32_MISC_ENABLE EQU 1A0h
36 MSR_EFER EQU 0c0000080h
40 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
50 ; Constants relating to CPU State Save Area
55 PROTECT_MODE_CS EQU 08h
56 PROTECT_MODE_DS EQU 20h
63 gcSmiHandlerTemplate LABEL BYTE
67 ; The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
68 ; bit addressing mode. And that coincidence has been used in the following
69 ; "64-bit like" 16-bit code. Be aware that once RDI is referenced as a
70 ; base address register, it is actually BX that is referenced.
72 DB 0bbh ; mov bx, imm16
73 DW offset _GdtDesc - _SmiEntryPoint + 8000h ; bx = GdtDesc offset
75 DB 2eh, 0a1h ; mov ax, cs:[offset16]
76 DW DSC_OFFSET + DSC_GDTSIZ
79 mov [rdi], eax ; mov cs:[bx], ax
80 DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
81 DW DSC_OFFSET + DSC_GDTPTR
83 mov [rdi + 2], ax ; mov cs:[bx + 2], eax
85 lgdt fword ptr [rdi] ; lgdt fword ptr cs:[bx]
86 ; Patch ProtectedMode Segment
87 DB 0b8h ; mov ax, imm16
88 DW PROTECT_MODE_CS ; set AX for segment directly
90 mov [rdi - 2], eax ; mov cs:[bx - 2], ax
91 ; Patch ProtectedMode entry
92 DB 66h, 0bfh ; mov edi, SMBASE
94 lea ax, [edi + (@ProtectedMode - _SmiEntryPoint) + 8000h]
96 mov [rdi - 6], ax ; mov cs:[bx - 6], eax
97 ; Switch into @ProtectedMode
111 mov ax, PROTECT_MODE_DS
117 DB 0bch ; mov esp, imm32
122 DB 0b8h ; mov eax, offset gSmiCr3
125 mov eax, 668h ; as cr4.PGE is not set here, refresh cr3
126 mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
128 sub esp, 8 ; reserve room in stack
130 mov eax, [rsp + 2] ; eax = GDT base
133 mov [rax + TSS_SEGMENT + 5], dl ; clear busy flag
137 ; enable NXE if supported
138 DB 0b0h ; mov al, imm8
143 ; Check XD disable bit
145 mov ecx, MSR_IA32_MISC_ENABLE
148 push rdx ; save MSR_IA32_MISC_ENABLE[63-32]
149 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
151 and dx, 0FFFBh ; clear XD Disable bit if it is set
156 or ax, MSR_EFER_XD ; enable NXE
163 ; Switch into @LongMode
164 push LONG_MODE_CS ; push cs hardcore here
165 call Base ; push return address for retf later
167 add dword ptr [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg
171 or ah, 1 ; enable LME
174 or ebx, 080010023h ; enable paging + WP + NE + MP + PE
177 @LongMode: ; long mode (64-bit code) starts here
178 mov rax, offset gSmiHandlerIdtr
180 lea ebx, [rdi + DSC_OFFSET]
181 mov ax, [rbx + DSC_DS]
183 mov ax, [rbx + DSC_OTHERSEG]
187 mov ax, [rbx + DSC_SS]
189 ; jmp _SmiHandler ; instruction is not needed
192 mov rbx, [rsp] ; rbx <- CpuIndex
204 mov rax, CpuSmmDebugEntry
208 mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous
212 mov rax, CpuSmmDebugExit
218 ; Restore FP registers
225 mov rax, offset ASM_PFX(mXdSupported)
229 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
232 mov ecx, MSR_IA32_MISC_ENABLE
234 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
240 gcSmiHandlerSize DW $ - _SmiEntryPoint