1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Code template of the SMI handler for a particular processor
19 ;-------------------------------------------------------------------------------
22 ; Variables referrenced by C code
25 %define MSR_IA32_MISC_ENABLE 0x1A0
26 %define MSR_EFER 0xc0000080
27 %define MSR_EFER_XD 0x800
30 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
32 %define DSC_OFFSET 0xfb00
33 %define DSC_GDTPTR 0x30
34 %define DSC_GDTSIZ 0x38
38 %define DSC_OTHERSEG 20
40 ; Constants relating to CPU State Save Area
42 %define SSM_DR6 0xffd0
43 %define SSM_DR7 0xffc8
45 %define PROTECT_MODE_CS 0x8
46 %define PROTECT_MODE_DS 0x20
47 %define LONG_MODE_CS 0x38
48 %define TSS_SEGMENT 0x40
51 extern ASM_PFX(SmiRendezvous)
52 extern ASM_PFX(gSmiHandlerIdtr)
53 extern ASM_PFX(CpuSmmDebugEntry)
54 extern ASM_PFX(CpuSmmDebugExit)
56 global ASM_PFX(gSmbase)
57 global ASM_PFX(mXdSupported)
58 global ASM_PFX(gSmiStack)
59 global ASM_PFX(gSmiCr3)
60 global ASM_PFX(gcSmiHandlerTemplate)
61 global ASM_PFX(gcSmiHandlerSize)
67 ASM_PFX(gcSmiHandlerTemplate):
69 mov bx, _GdtDesc - _SmiEntryPoint + 0x8000
70 mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
73 mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
75 o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
76 mov ax, PROTECT_MODE_CS
78 DB 0x66, 0xbf ; mov edi, SMBASE
79 ASM_PFX(gSmbase): DD 0
80 lea eax, [edi + (@ProtectedMode - _SmiEntryPoint) + 0x8000]
93 mov ax, PROTECT_MODE_DS
99 DB 0xbc ; mov esp, imm32
100 ASM_PFX(gSmiStack): DD 0
105 DB 0xb8 ; mov eax, offset gSmiCr3
106 ASM_PFX(gSmiCr3): DD 0
108 mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3
109 mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
111 sub esp, 8 ; reserve room in stack
113 mov eax, [rsp + 2] ; eax = GDT base
116 mov [rax + TSS_SEGMENT + 5], dl ; clear busy flag
120 ; enable NXE if supported
121 DB 0xb0 ; mov al, imm8
122 ASM_PFX(mXdSupported): DB 1
126 ; Check XD disable bit
128 mov ecx, MSR_IA32_MISC_ENABLE
131 push rdx ; save MSR_IA32_MISC_ENABLE[63-32]
132 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
134 and dx, 0xFFFB ; clear XD Disable bit if it is set
139 or ax, MSR_EFER_XD ; enable NXE
146 ; Switch into @LongMode
147 push LONG_MODE_CS ; push cs hardcore here
148 call Base ; push return address for retf later
150 add dword [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg
154 or ah, 1 ; enable LME
157 or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
160 @LongMode: ; long mode (64-bit code) starts here
161 mov rax, strict qword 0 ; mov rax, ASM_PFX(gSmiHandlerIdtr)
162 SmiHandlerIdtrAbsAddr:
164 lea ebx, [rdi + DSC_OFFSET]
165 mov ax, [rbx + DSC_DS]
167 mov ax, [rbx + DSC_OTHERSEG]
171 mov ax, [rbx + DSC_SS]
173 mov rax, strict qword 0 ; mov rax, _SmiHandler
178 mov rbx, [rsp + 0x8] ; rcx <- CpuIndex
190 call ASM_PFX(CpuSmmDebugEntry)
193 call ASM_PFX(SmiRendezvous)
196 call ASM_PFX(CpuSmmDebugExit)
201 ; Restore FP registers
208 lea rax, [ASM_PFX(mXdSupported)]
212 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
215 mov ecx, MSR_IA32_MISC_ENABLE
217 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
223 ASM_PFX(gcSmiHandlerSize) DW $ - _SmiEntryPoint
225 global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
226 ASM_PFX(PiSmmCpuSmiEntryFixupAddress):
227 lea rax, [ASM_PFX(gSmiHandlerIdtr)]
228 lea rcx, [SmiHandlerIdtrAbsAddr]
229 mov qword [rcx - 8], rax
231 lea rax, [_SmiHandler]
232 lea rcx, [_SmiHandlerAbsAddr]
233 mov qword [rcx - 8], rax